CALIFORNIA STATE u~IVERSITY, NORTHRIDGE

COMPUTER MEMORY '" DESIGN AND ANALYSIS

A thesis submitted in partial satisfaction of the requirements for the degree of Master of Science in Engineering by Leo George -Zaretsky

January, 1980 p '

The Thesis of Leo George Zaretsky is Approved:

Professor R. Abbott

Professor E. Hri~

California State University, Northridge

ii TABLE OF CONTENTS

Section Title Page List of Illustrations vii List of Tables ix

Abstract X Introduction 1 1 Introduction to Computer Memories 2 1.1 General 2 1. 2 Magnetic 'Nemories 3 1.3 Semiconductor Memories 6 1.4 Memory Applications 8 2 Memory Selection and Design 10 2. 1 Memory Selection Criteria 10 2.2 Design Concept 10 2.3 Design Variables 11 2.4 Design Criteria 11 2. 4. 1 Cost 12 2. 4. 2 Size, Form Factor and Weight 12 2.4. 3 Speed 12 2.4.4 Power Consumption 13 2.4. 5 Input/Output Requirements 13 2.4.6 Control Signal Requirements 13 2.4. 7 Data Retention 14 2.4.8 Reliability 14 2.4.9 Maintainability 14 2.4.10 Repairability 15

iii Section Title Page 2.4.11 Reproducibility 15 2.4.12 Temperature 15 2.5 Requirement Summary and Justification for Selection 15 2.6 Component Selection 20 '2.6.1 Memory Elements 20 2. 6. 2 Control Logic 20 2. 6. 3 Power Regulator 22 3 Design Analysis 24 3.1 General 24 3. 1. 1 Timing Analysis Philosophy 24 3.1. 2 Input/Output Loading Analysis Philosophy 25 3.1.3 Power Analysis Philosophy 26 3. 1.4 Data Retention and Power Sequencing Analysis Philosophy 28

3.2 Timing Analysis 29 3. 2. 1 Address Input Circuit 37 3.2.2 CNOS RAM Chip Enable 45 3.2.3 CMOS RAM Write Enable 51 3.2.4 CMOS RAM Data Output Enable 54 3.2.5 Data Output Buffer Enable/ Disable (TACC RAM) 57 3.2.6 Data Ready Computation (DREADY~~) 58

.h 3.2.7 Input Data Buffer Enable (CIE") 59

iv Section Title Page 1 3.2.8 UVE PROM Chip Enable (CE1 < - CE4~~) 62 3.2.9 UVE PROM Output Enable

... ~,.. ..)~ (OEl" - OE4") 63 3.2.10 UVE PROM Data Output Time 64 3.2.11 UVE PROM Output Buffer Enable

(TACC PROM) 64 3.2.12 Data Ready PROM (DREADY")"· 65 3. 2.13 Memory Busy (NBUSY~·.-) 66 3.2.14 Cycle Initiate (CI) 66 3.3 Input/Output Loading Analysis 67 3.4 Power Analysis 67 3.5 Data Retention Switch Analysis 67 3.5.1 Transistor Parameters 68 3.5.2 Zener Diode Parameter 69 3.5.3 Niscellaneous Computation 70 3.5.4 Calculation of Resistor Values 71 3.5.5 Power Computation of Data Retention Components 74 3.5.6 Total Power Consumption of the Data Retention Switch 80 3. 5. 7 Output Short Circuit Considerations 81 3.5.8 Computation of Threshold Voltage 81 3.5.9 Turn Off Analysis 82 3.5.10 Turn On Analysis 88

v Section Title Page 4 Hemory Analysis Summary 97 4.1 Timing Analysis Summary 97 4.2 Input/Output Loading Summary 97 4.3 Power Analysis Summary 97 4.4 Data Retention Switch Analysis Summary 97 5 Conclusion 106 Bibliography and References 108 Appendix A 110 Appendix B 130

vi LIST OF ILLUSTRATIONS

Figure No. Page 2.1 Semiconductor Memory Block Diagram 21 3.1 Semiconductor Memory Timing Diagram 31 3.2 Address Pullup Circuit 39 3.3 Address Input Equivalent Circuit 39 3.4 Basic Data Retention Switch 83 3.5 Simplified Data Retention Switch 83

3.6 Circuit for Computing Vcc3 Decay Time 85 3.7 Circuit for Computing VDD Decay Time 85

3.8 Circuit for Computing VCC 3 ' Vcc4 and VDD Time Response 89

3.9 Simplified Vcc3 Time Resgonse Circuit 89 A1 O··fQS RAM Address Buffer Schematic 111 A2 Ct-10S RAM Data Input/Output Buffer Schematic 112 A3 CHOS RAM Data Input/Output Buffer Schematic 113 A4 CMOS RAN Data Input/Output Buffer Schematic 114 AS CNOS RAM Data Input/Output Buffer Schematic 115 A6 CMOS RAM Schematic 116 A7 CMOS RAH Schematic 117 A8 CMOS RM-'1 Schematic 118 A9 CHOS RAM Schematic 119

vii Figure No. Page AlO CMOS RAM Schematic 120" All PROM Memory Schematic 121 Al2 PROt-1 Memory Schematic 122 Al3 PROM Memory Schematic 123 Al4 WE PROH Output Buffer Schematic 124

Al5 ~!E PROM Decoder Schematic 125 Al6 Semiconductor Memory Timing Schematic 126 A17 Semiconductor Memory Address Latches Schematic 127

A18 Semiconductor ~!emory Address Decoder Schematic 128 A19 Semiconductor Memory Data Retention Switch Schematic 129

viii LIST OF TABLES

Table No. Page 2.1 Preliminary Memory Selection 16 2.2 Memory Figures of Merit 18 2.3 Memory Combination Selection 19 3.1 Memory Timing Requirements 30 3.2 Active Component Tolerances 34 3.3 Passive Component Tolerances 36 4.1 Timing Analysis Summary 98 4.2 Power Analysis Summary 102 4.3 Data Retention Switch Analysis Summary 103 Bl Input/Output Loading 131 B2 Standby Mode Power Computation 146

B3 CMOS RAM Cycling Power Computation 147

B4 lNE PRO!v! Cycling Power Computation 148

135 Programming ~lode Power Computation 149

B6 Component Power Dissipation 150

ix ABSTRACT

COMPUTER MEMORY DESIGN AND ANALYSIS by Leo George Zaretsky Master of Science in Electrical Engineering

This paper deals with the design and analysis of a computer memory for space and airborne equipment. A dis­ cussion of two basic computer memory technologies and three applications are presented in order to acquaint the. reader with memory functions and utility. The two memory technologies discussed are:

Magnetic ~!emeries Semiconductor Memories The three applications discussed are: Scratch pad Permanent/Semipermanent Storage Mass Storage

X Selection of the type of memory is based on the esta­ blished requirements and weighted design criteria. The memory that meets all the design requirements and has a minimum weighting factor is the memory selected. The se­ lected memory is a 4K x 20 bit CMOS RAM (Read and Write Memory) and a 8K x 20 bit PROM (Programmable Read Only Memory). Following the selection, memory design proceeds to the conceptual design stage - component selection, memory element configuration and control logic design. In this design, as in most memory designs, the memory is treated as a self-contained unit: that is, a system that generates all its required control signals. Some basic control sig­ nals such as memory cycle initiate, address data, input data and mode control (read/write) select are the only in­ put requirements. Memory output requirements consist of output data, data ready and memory busy signals. A thorough analysis is performed on the conceptual design. The analysis demonstrates that the design meets the required specifications.

The design analysis is divided in~o four categories: Timing Analysis Input/Output Loading Analysis Power Analysis Data Retention Switch Analysis A summary table provides a quick comparison of the

xi analysis results to the original requirements. It also demonstrates at a glance that the memory design meets the established design requirements.

xii INTRODUCTION

Advances in the development of space vehicles have generated a requirement for a memory. This memory must utilize a design that will optimize power consumption, weight and size without a sacrifice in reliability and data access time. Several memory technologies exist that can satisfy the basic requirement; but, not every one will satisfy all the requirements. As a result, a formalized evalu­ ation process is necessary to select the optimum type of memory that satisfies most or all requirements. Once the type of memory and technology is selected, a thorough worst case analysis and detailed design is per­ formed, that will insure reliable performance under adverse conditions in space. Components selected must be operated well below their maximum ratings and must have established reliability ra­ tings and life times. The objective is to obtain an optimum design and prove by means of an analysis that the design is sound and fault free.

1 CHAPTER 1

INTRODUCTION TO COMPUTER MEMORIES

1.1 GENERAL Computer memories are devices capable of storing di­ gital information for retrieval at some later date. This information is generally stored in a memory in the form of words - that is, blocks of binary data. Each possible word location is known as an "address" and denotes a spe­ cific physical location within the memory. Each piece of binary information "bit" is located in a single memory cell. A word composed of 20 bits requires 20 memory cells and the physical location of these 20 cells is the address of that word. Entering information into memory is called "writing". Extracting information is called "rea­ ding". Memory capacity is normally expressed as the num­ ber of 'vords times the number of bits. As an example a memory consisting of 10,000 x 20 bit words would be writ­ ten as lOK x 20 bits. Memories may have either restricted or random access. In a restricted access memory, information can be written and read only in a certain fixed pattern. In a random access memory information can be written and accessed at any location. Readout of information from a memory may be either destructive or nondestructive. Destructive readout causes the memory elements to reset to a zero

2 3

information state. Nondestructive readout leaves the in­ formation in the memory elements intact after a read. Computer memories are generally divided into two technologies: Magnetic Memories Semiconductor Memories

1.2 MAGNETIC MEMORIES Magnetic memories are basically comprised of core memories, plated wire memories and the most recent addi­ tion the bubble memory. A core memory consists of toroidal shaped ferrites with two stable states. Magnetizing a ferrite clockwise stores a binary "0", magnetizing it counterclockwise stores a "1". Once the direction of magnetization is set, it acts like a permanent magnet and retains the polariza­ tion information indefinately. Switching time of the core is a function of the core's magnetic properties and magnetizing currents, and is normally expressed as Ts = Sw/(I-I0 ) where Sw is the switching coefficient of the core, I the applied current and I 0 a constant representing the threshold current. Switching time Ts and applied current I are figures of merit for a core memory, because they determine power consumption, access time and memory cycle time. A plated wire·memory consists of storage elements fabricated by electroplating of a nickel - iron alloy 4 onto a substrate of berillium - copper wire, these are called digit lines. Orthogonal conductive ribbons act as word lines. The magnetic alloy has a hysteresis curve that depends on the direction of magnetization. During manufacture the easier to magnetize direction is established around the circumference of the digit line, while the more difficult magnetic direction is along the digit line. In order to read information stored in the plated wire, a word current is applied to the word line. This word current produces a "1" or a "0" on the digit line. The magnitude of this signal is the same for both "1" or "0", but the polarity is reversed. In the write operation current is passed through the word and the digit lines. This combination is sufficient to tip the magnetization vector of the alloy beyond the difficult to magnetize axes and polarize it in the oppo­ site direction. As can be seen from the description of plated wire memories they do not exhibit a destructive readout. That is, the information read does not have to be restored as in a core memory. A magnetic bubble memory is produced by growing a thin sheet of magnetic garnet on a nonmagnetic substrate, Two permanent magnets, one on each side of the garnet are used to align the magnetic domains in the direction of the 5 field of these magnets. Magnetic bubbles are created by a small localized magnetic flux in the opposite direction of the permanent magnets. This localized magnetic flux is produced by a small current loop above the surface of the magnetic garnet. The field created by the permanent mag­ nets is strong enough to contain this magnetic domain re­ versal as a small cylindrical bubble but not strong enough to dissolve this bubble once the generating current is re­ moved. The bubble is then propagated along a magnetic path created by changing the magnetization of tiny perm­ alloy magnets on top of the garnet that attract the bubble from one permalloy magnet to another. This change in mag­ netization is produced by a changing current in the ortho­ gonal coils around the magnetic garnet and substrate but sandwiched between the previously mentioned permanent mag­ nets. This changing current cyclicaly reversed produces a rotating field which causes ~~e change in magnetic attrac­ tion of the permalloy magnets and propulsion of the magne­ tic bubble. Binary information is represented as the presence or absence of a bubble at clock time in a detector. Logic ones are most commonly detected by passing bubbles across a permalloy strip whose magnetoresistance is changed by the bubbles' field. Synchronization is achieved by a strobed sense amplifier. In essence, a magnetic bubble memory resembles a shift register or better yet a delay line. Except, in a delay line we have electric pulses propagating around an electric circuit, whereas in a bubble memory magnetic bub­ bles are propagating along a closed magnetic path. Since, magnetic bubbles are not destroyed during a read operation, the memory is a nondestructive readout memory and certainly non volatile - that is, domains can remain at rest indefi­ nitely. A logic zero is created by destroying a bubble by the same current loop that created it by reversing the current, such that it will add to the magnetic field of the perma­ nent magnets, and consequently will dissolve the bubble.

1.3 SEMICONDUCTOR ~10RIES Three semiconductor technologies are currently avail- able for computer memory applications: Bipolar (TTL) Metal - oxide (MOS) Charge coupled device (CCD) Applicationwise these memories are subdivided into two categories: those that have read and write capability and those that have the ability to retain data permanently. A prime distinction in the read and write (RAM) memo­ ries lies in the manner in which data is written (stored) and read (accessed). Random - access memories have the ability of direct addressing of every memory cell; whereas in serial - access memories data in a particular cell is T accessed in a predetermined sequence, consequently access time is a variable. The charge coupled device memory (CCD) is an example of a serial - access memory. Memories that exhibit permanence of data; that is, memories with no ability to change data are called read only memories (ROM). These memories are hardwired -nor­ mally mask programmed at the factory and cannot be changed in the field. These memories are also non volatile - that is, they do not lose data following a power interrupt. A variation of these memories called programmable read only memories (PROM) exhibit either a one shot write ability or an ability to have the constants erased and then repro­ grammed. An example of the first is a fused memory and an example of the second is an ultraviolet light erasable memory. In a fused memory, a programming sequence burns out fuses thereby programming each cell into a desired perma­ nent logic "1" or "0" state. In the ultraviolet light erasable memory an ultraviolet light's enrgy is used to erase all of the rnernor/, normally to a logic "1" state. Following the erasure each cell can then selectively be programmed to a logic "0" state. This process can be re­ peated as many times as desired. Another division in performance are static and dyna­ mic memories. Static memories retain data for as long as power is applied to the memory whereas dynamic memories 8 will lose data if periodically not refreshed. All semicon­ ductor read and write (RAM) memories are volatile - that is they will lose data during power shutdown. Some memories consume so little power that they can retain data as long as a small battery voltage is applied to the memory, this voltage can be as low as 2.0 volts and because of the very low power consumption will last a long time.

1.4 MEMORY APPLICATIONS The three basic memory applications are: Scratchpad Permanent/semipermanent storage Mass storage Scratchpad is usually used to designate a random ac­ cess very fast read and write memory, i.e. for temporary storage of data. The required capacity of such a memory in aerospace computers is not very large, generally lK to 4K words. Memory types used for this application are - core, plated wire or semiconductor RAMS. Permanent/semipermanent storage memories are used in the following applications: table look-up, code conversion or generation, character generation, and microprogramming. In a look-up table a stored word is used as a reference to find a new related word. Examples of such use are sine, cosine or other tables that have a mathematical relation. Code conversion and generation implies translation between functions that do not have any mathematical relation. 9

Character generators feature selection of dot, segment or other patterns used for visual display. Microprogramming is generally understood as a technique for controlling com­ puters by means of data stored in memory. Generally these memories require quick data access; consequently they are usually of the random access variety. Core and plated wire memories can be used, however semiconductor ROMS and PROMS are most cost effective. Mass storage or bulk memories are used to permanently store large amounts of data, e.g. data that is rarely chan­ ged. Normally these are magnetic or paper tapes, disks, drums and similar devices. Access time of such memories is not as important as nonvolatility and nondestructive readout. It is expected that as the price of bubble memo­ ries decreases that they will take over more and more of this function. CHAPTER 2

MEMORY SELECTION AND DESIGN

2.1 MEMORY SELECTION CRITERIA Memory selection is based on the requirements of a rocket guidance system. The dedicated control application of this system requires that the hardware perform a limited task repeatedly on demand. There is only a limited need to process data from various sensors. The requirements are unique and precisely defined, however some provision must exist for changing the dedicated program. The minimum re­ quirements ares lK x 20 bits of scratchpad 8K x 20 bits of programmed memory 3K x 20 bits of diagnostic memory The scratchpad memory must be a read/write memory, nonvolatile for short power failures. The programmed me­ mory is basically a read only memory with some capability of reprogramming. The diagnostic memory must be of the read/write type.

2.2 DESIGN CONCEPT Ten possible candidates have been selected for initial considaration in this design. Ferrite Core Memory (RAM) ... nonvolatile Plated Wire Memory (RAM) - nonvolatile Bubble Memory (RAM) ... nonvolatile

10 11

Charge Coupled Device Memory (RAM) - volatile Bipolar Transistor Memory (RAM) - volatile Bipolar Transistor Memory (ROM) - nonvolatile MOS Memory (RAM) - volatile MOS Memory (ROM) - nonvolatile MOS Memory (PROM) - nonvolatile CMOS t-1emory (RAM) - semivolatile Of these ten different types only the first three satisfy the nonvolatility and read/write requirements. However, combinations of the others are possible.

2.3 DESIGN VARIABLES The only permissible unconstrained variable in this design is the one that defines packaging. Packaging con­ sists of selecting components and hardware form factors, number of components and layout. In other words, there is complete flexibility in selecting monolithic integrated circuits, hybrid circuits or discrete devices, the number of printed circuit: boards with single or multilayer connec­ tions, the type of connectors, materials and hardware. Constraint variables such as cost, size, power con­ sumption, mean time to failure have an upper or lower bou~d. Obviously optimization of these variables makes a more viable and competitive product.

2.4 DESIGN CRITERIA Design criteria are normally dictated by the type of 12

application and the customer. Often they are also a re­ sult of preliminary design, previous design or trade-off studies. The most important design criteria are discussed in the following sections.

2.4 .1 COST In order to be cost competitive, cost of the memory must not exceed $4,500, This cost is a budgeted part of the total system cost. Should this cost become larger, then the system cost may become larger, resulting in the loss of this contract to another manufacturer. Budgeted cost of the memory was based on past manufacturing costs of similar memories of between ¢2 to ¢4 per bit.

2.4. 2 SIZE, FORM FACTOR AND WEIGHT Size/form factors are constrained by the space allot­ ted for the memory inside the rocket to a maximum of 10" x 7" x 2". \.Yeight is constrained by the total payload to less than 2 lb.

2.4. 3 SPEED Speed consists of memory access time and memory cycle time. Access time is the time at which valid data becomes available following a memory cycle initiate. This has to be less than 1.5 microseconds. Cycle time consists of one read and one write cycle and must be less than three microseconds. Longer cycle or access times will not pro­ vide timely flight corrections. 13

2.4 .4 POWER CONSUMPTION Power consumption is an important parameter. Too much power consumption will produce excessive internal heat which will cause the temperature to rise above the opera- ting temperature of silicon semiconductor junctions, resul- ting in a memory failure. As a result power consumption must be limited to 7.5 watts.

2.4.5 INPUT/OUTPUT REQUIREMENTS Input signals supplied to the memory by the control processor consist of 14 binary coded address bits (AOO - Al3) for memory cell selection and 20 data bits (DIOO - DI19). Each line will be capable of driving two standard 54 series T2L loads. Data outputs consisting of 20 data bits (DOOO - D019) must be of the tri-state or open collector type because they time share the data buss.

2.4.6 CONTROL SIGNAL REQUIREMEl~TS The only memory control signals available from the central processor are memory cycle initiate (CI) and a read/write mode control signal (MC). A 8 MH2 clock (8MHZCL) is also available if needed. Each of these is capable of driving two standard 54 series r 2L loads. A required output synchronizing signal - a data ready (DREADY) must be available to indicate presence of valid data. This signal must be capable of driving two standard 14 series 54 T2L loads.

2.4.7 DATA RETENTION The semiconductor memory must as a minimum retain data in the 8K x 20 bits of programmed memory during power off, that is it must be nonvolatile. It must also be capable of not losing data in the lK x 20 bits of scratchpad for power interrupts of less than 300 milliseconds. No data retention on the 3K x 20 bits of diagnostic memory is required; since, this memory is only used on the ground for the purposes of system checkout.

2.4.8 RELIABILITY The memory must be very reliable. It must utilize components with established reliability numbers. Since, redundancy will be contained in the software, none is re­ quired in the hardware. The software will be organized so that as many as two memory cell failures will not affect normal operation.

2.4. 9 MAINTAIN ABILITY Since, the memory will only be used once and then dis­ carded, maintainability is not a requirement. The memory is only used to guide the first and second stage of a rocket. After these stages have burned out they are dis­ carded together with the memory. 15

2.4.10 REPAIRABILITY The memory must consist of modular components that can be readily replaced.

2.4.11 REPRODUCIBILITY Production units must be reproducible, that is they should not require special individual adjustments or design changes.

2.4.12 TEMPERATURE Memory must be capable of operating in an ambient temperature of -55°C to +100°C, or specifically a heat sink temperature of -55°C to +100°C.

2.5 REQUIREMENT SUM~~RY AND JUSTIFICATION FOR SELECTION In order to narrow down the choice a table, table 2.1 has been constructed. This table lists the required para­ meters versus the different types of memories. By inspection of the table it becomes obvious that only the CMOS RAM meets all the requirements, though condi­ tionally. Based on the table the following combinations have been selected: 1. CMOS RAM for Diagnostic, Core Memory for Scratch­ pad and Programmed Memory. 2. CMOS RAM for Diagnostic, MOS PROM for Programmed Memory and Core for Scratchpad. 3. CMOS RAM for Diagnostic and Scratchpad and MOS PROM for Programmed Memory. Table 2.1 Preliminary Memory Selection REQlJIREMENTS HEMORY TYPES Core Plated Bubble CCD Bipolar MOS CMOS \vire RAM ROM PROM RAM ROM PROM RAM Cost ($4, 500 X X v v X X X v v v v Size ( 10 .. ';':7"1'2" v v v v v v v v v v v I Weight <2lb X X v v v v v v v v v I Cycle ttme <3us v v X X v v v v v v v I v v v ! Access time <1. Sus v v X X v v v v ! Power consumption <7. 5 watts X X v v X X X X X X v Programmed memory nonvolatile and reprogrammable v v v B X X X X X v B Scratchpad data retention <300ms v v v B X X X X X X B Diagnostic read/ write capability v v v v v X X v X X v . 0 T~nperasure -55 c to +100 C v X X X v v v v v v v I Military I specifications v X X X v v v v v v v Where.V - meets requirements X - does not meet requirements B - meets requirements with a battery

t--1 0\ 17 ~ .

To select the optimum memory combination it is neces- sary to construct a table of weighted requirements versus the three memory combinations. Based on customer and com- pany preference the following weighted values were estab- lished: 4 wl = 2.22xl0- /cost in $ 2 3 w2 = 3.57xl0- /in 1 w3 = 5.00xl0- /lb w4 = 5/cycle time

w5 = 10/access time 1 \ii6 = 5xl0- /watt 6 w7 = 3.47xl0- /deviation in I/O requirements 6 Wg = 3.47x10- /deviation in control requirements 5 ~y9 = lxl0- /retention time w10 = 1. hour 8 \v11 = 2x10- /cost to repair in $ 5 \>/12 = 2xl0- /MTTF 5 w13 = lxl0- /adjustment In addition we have the following estimates tabulated in table 2.2. Table 2.3 consisting of the weighted requirements Wx x Rx x N versus the three memory requirements is used as an aid in selecting the optimum memory combination. Based on table 2.3, combination #3 is the obvious optimum combination. Table 2.2 Memory Figures of Merit FUNCTION CORE CMOS RAH MOS PROM ¢0.8 Cost/bit = R1 ¢5.0 ¢1.0 3.6*10-4 in3 8. 3;"10- 5 in3 4 • 2,.-1 o-5 in 3 Size/bit = R2 1.4,.~1o- 5 lb 3,51-10-6 lb 3.4•'-10- 6 lb Weight/bit = R1 600 ns Cycle time = R4 1.0 us 600 ns 350 ns 350 ns 450 ns Access time = R5 o-4 9.6*10-6 w 3,6td0-S w Power consumption/bit = R6 2.9•'>1 w meets, 0 meets, 0 meets, 0 I/O requirements = R7 meets, 0 meets, 0 meets, 0 Control signal requirements = R8 Oo 400 ms 15 years Data retention time = R9 61.4k hours MTBF in hours = 1/R10 20k hours 3.2m hours $150 $80 $160 Avg~ cost to repair = R11 15 min. 10 min. -10 mi.n. MTTR = R12 6 0 0 Number of adjustments = R13

...... (X). 19

Table 2.3 Memory Combination Selection WEIGHTED REQUIREMENTS COMBINATIONS IFl 112 1!3 3K CMOS RAM 3K CMOS RAM 4K CMOS RAM 9K Core 8K NMOS PROM 8K NMOS PROM Cost 2.56 0.77 0.55 Size 2.98 0.81 0.57 Weight 1.64 0.63 0.50 Cycle Time 1. 30 0.91 0.87 Access Time 1. 01 1.19 1.20 Power 31.65 7.29 4.06 I/O Requ. 0 0 0 Control Requ. 0 0 0 Data Retention 0.29 0.29 o. 29 MTBF 10.82 4.35 3.16 Repair Cost 0.77 0.80 0.76 MTTR 1.32 1. 08 0.96 Adjustments 0.36 0.04 0 Total 54.70 18.16 12.92 20

2.6 COMPONENT SELECTION Based on space and weight constraints, it was decided to use the largest memory capacity packages available and to use multiple resistor packages wherever possible.

2.6.1 MEMORY ELEMENTS The selection of memory elements was governed by the availability and military standards compliance. In each case the highest density memory element available and meeting the specifications was selected. For the scratchpad and diagnostic memory a HARRIS HM-6514, 1024 x 4 bit CMOS RAM was selected - 20 of these are required to make up the 4K x 20 bit memory. For the semipermanent memory an INTEL 2716, a 2048 x 8 bit uV eras­ able PROM was selected - 12 of these are required to make up the 8K x 20 bit memory. FAIRCHILD 54LS368 Hex buffers were selected as address and data input and output buffers. Figure 2.1 is a block diagram representation of the memory. Figures Al - AlO in Appendix A are detailed sche­ matics of the CMOS RAM portion of the memory and figures All - A15 in Appendix A are schematics of the PROM portion.

2.6.2 CONTROL LOGIC The control logic must provide the semiconductor me­ mory with all internally required timing and control sig­ nals. DIOO­ '""'\. Dl19 -o Meu.sy 8MHZCl o-- * TIMtNG -u DRE4DY* t> coe• CI AND cts* MfMJ: o-- CONTROL l lNPUT/ .()OOQ­ PRoc/' o- 4800- ADDRESS A BOo~- 4 k >< 24 BIT MDOO- OUTPUT r-o ~BO'l BUffeRS -'180'} CMOS fUIM MD I '1 DOI'i r;E)1Dj Wf{J:- BUFFERS CLL 1 WIEI~Wtll ADO­ 1- SME:Jt 0- J.i 13 {)-TYPE DMf I :ft_ PM£~" ):)!c.OD£1(5 L"'TCHES -1810- ~ Me. '-" ,l)813 (R/W) Pr.11•- PM4;a l -o Vppi­ VOlTAGE Vop Vpp'f

~ Vc.c.1 '-' SWITCH Vccz. Poe* .. ____ .. c:s•*- l f--· L_.____.____ STR. tit Cf4"*" MPOO- OUTPUT 8 K X 24 BIT P~OG, DECODfRS ;---' MPI'l BUFFERS OEI- UVE. PROM ()-----·------... * PGMP o•.;..• f)'IPOO-

MPI'1 -~-~--

SEMICONDUCTO MEMORY BLOCK DIAGRAM FIGURE 2.1

N...... 22

Two eight bit shift registers timed by an external

8 MH2 clock are used to generate a memory cycle time of 1. 1 us and an access time of 700 ns. Address and R/W mode control signals are stored in look ahead type registers. Three line to eight line deco- ders are used to generate 1K select lines used for the CMOS RAM and 2K select lines used for the uv PROM selec- tion. Figures A16 - A18 are schematic representations of the control logic.

2.6.3 POWER REGULATOR Since, the main +5.0 V regulator in the control pro- 1 cesser is capable of supplying an additional 2 amperes of current for the memory, no additional power regulator is required. The +5.0 V regulator in the central processor is a highly efficient switching regulator capable of maintain­ ing the +5.0 V at t 5% over the required temperature and load variations. However, since the regulator delivers a total of about 10 amperes to its combined loads, its equi­ valent load resistance is 0.5 ohms. This 0.5 ohms in par­ allel with about 5,000 uf of filter capacitance produces a shutoff voltage decay time constant of 2.5 ms. The re- quirement however is to maintain voltage above 2.0 V for more than 300 ms for the scratchpad memory. Increase of the 5,000 uf filter capacitor to 0,6 farads is mechanically 23 not feasible. In order to accomplish this feat, a voltage switch is designed in. This voltage switch disconnects t?e VDD sup­ ply of the scratchpad memory from the main supply at the instant the main supply drops below 3.5 v. Such a circuit is illustrated by schematic diagram figure A19 in Appendix A. CHAPTER 3

DESIGN ANALYSIS

3.1 GENERAL The purpose of the design analysis is to show that all design criteria have been met and that all components are operated within their specifications and well below their maximum ratings. As a minimum requirement the analysis must consist of the following: Timing Analysis Input/Output Loading Analysis Power Analysis Data Retention and Power Sequencing Analysis

3.1.1 TIMING ANALYSIS PHILOSOPHY A timing analysis is always necessary regardless of the type of memory designed. Whether it be for commercial or aerospace applications. The only difference between aerospace and commercial applications exists in the degree of component worst casing. That is, derating for tempera­ ture and life. A timing analysis must be so performed that it not only guarantees specifications, but also performance. The analysis must consider the interaction and sequencing of signals to ensure that an erroneous state is never assumed. The computation of propagation delays must consist of

24 25 the addition of propagation delays of components in each independent path. Normally all the minimum delays are ad­ ded to form a minimum delay path, all the typical delays are added to obtain a typical delay path and all the maxi­ mum delays added to form a maximum delay path. As a re­ sult each independent path will have three delays: a mini­ mum, a typical and a maximum. When comparing propagation delays for interaction, the minimum path of one is compared to the maximum of an­ other and vice versa. Common path must use the same worst case numbers up to their last point of commonality, or the common path subtracted before making a comparison. In a case where the logic path consists of more than ten components, a statistical analysis instead of an abso­ lute worst case analysis may be acceptable. It is common practice to use 50% to 50% propagation delays in a timing analysis for simplicity and uniformity. That is, propagation delays are specified from the 50% voltage point of the rising or falling input signal to the

50~~ voltage point of the resultant rising or falling out­ put signal.

Section 3.2 exemplifies the above described a~alysis by an illustrative example of computing the timing analy­ sis of the memory designed in chapter 2.

3.1. 2 INPUT/OUTPUT LOADING ANALYSIS PHILOSOPHY Input/output loading analysis is an essential part of 26

every design. The reason for performing such an analysis lies in the finite drive capability of logic elements and loading by the input circuits. A simple addition of loads to match the number of source loads is not always practi­ cal because of interfacing with different logic families, the use of pullup or terminating resistors, or in some cases transistor loads. The only logical approach is to use the output drive capability of each source in both the logic "0" and logic "1" state and compare that to the sum of all the load cur­ rents for the logic "0" and logic "1" inputs; provided the logic level requirements are satisfied. In commercial and less stringent designs it is suffi­ cient to demonstrate that the drive capability exceeds or equals the load requirements. In aerospace and military applications the drive capability is decreased by 10% be­ fore it is compared to the load requirements which are increased 10% to allow for life derating. Loading ratios are often used to come up with figu­ res of merit such as mean time to or between failures. The above requirements are illustrated by an example in section 3.3. In section 3.3 a computation of Input/ OUtput loading is performed on the memory design of chap­ ter 2.

3.1. 3 POWER ANALYSIS PHILOSOPHY A power analysis is required in order to budget power 27 for the memory in a system power supply or when designing a power supply for the memory, It is not sufficient to only compute the maximum po­ wer requirements. The knowledge of the maximum power re­ quirement does not tell the power supply designer anything about the transient requirements and load fluctuations. A good memory design generally has enough capacitive filtering to integrate fast load transients into much slo­ wer fluctuations. The knowledge of such load changes is essential to a power supply designer if he is to maintain voltage ripple below a certain maximum. Since, power consumption of most semiconductor memo­ ries increases during read or write from that in standby; a computation of power consumption in both modes is essen­ tial. Another important reason for computing the power con­ sumption of the memory and each individual component is to be able to properly heat sink the memory and its compo­ nents. This is important in maintaining components below their maximum operating temperature, at maximum ambient temperatures. Knowledge of the maximum operating temperature and power dissipation permits the computation of a stress ra­ tio, which is used in reliability calculations of mean time to failure or mean time between failure figures of merit. A typical power analysis is performed in section 3.4 on the memory designed in chapter 2.

3.1.4 DATA RETENTION AND POWER SEQUENCING ANALYSIS PHYLOSOPHY This type of analysis is essential in almost all type of read/write memories. Even nonvolatile core memories require power sequencing in order to prevent a write cycle during power turn on or off from erasing data. The requirements differ from memory to memory, also from design to design; consequently, one can only say that some kind of sequencing is generally required in memories with read and write capabilities. For example, CMOS RAM memories are volatile, that is they lose data when power is turned off. However, because of their low power consumption in standby a voltage on the CMOS RAM can be maintained by a battery or a bank of char­ ged up capacitors. Regardless of whichever source is used to maintain the voltage, a switch is required to disconnect the CNOS RAM from the primary power which is dropping and to connect it to a battery or a bank of capacitors. How­ ever, in doing this, one must bear in mind the possibility of a latch up in the CMOS RAH should an input or output port voltage exceed its power supply voltage. This latch up is due to parasitic isolation PNP/NPN junctions forming an SCR (Silicon Controlled Rectifier). This SCR when fired at the gate acts like a switch between the CMOS RAM supply and ground, conducting 200 rna - 400 rna of current for the devices used in this design. This current will flow until it is reduced below a holding current of about 5 rna. At this point the SCR shuts off. Currents of this magnitude not only cause malfunction of the memory element, but if prolonged will cause over heat­ ing, possible metal migration and eventual distruction. From the above discussion it becomes obvious that a loss of voltage on the CMOS RAM must be avoided if data retention is required, and latch up prevented. As a result a thorough analysis of these pertinent parameters is required in order to ensure complience. To exemplify the above discussion an analysis on a capacitive bank standby supply and power sequencing of the circuit in chapter 2 is performed in section 3.5.

3.2 TIMING ANALYSIS The basic philosophy of the semiconductor memory ti­ ming analysis is to compute propagation delays and pulse width of the internally generated control signals. These pulse width and timing delays must satisfy the switching characteristics of the memory elements. Table 3.1 is a comparison table of computed results versus requirements. Figure 3.1 represents the complete semiconductor memory timing including computed results. Before performing a worst case computation it is ne­ cessary to determine the component tolerances. Tables 3.2 Table 3.1 Memory Timing Requirements SIGNAL DESIGNATION COt-IPUTER GIVEN TIMING/ COMPUTED TIMING MEMORY REQUIREMENT Start Time End Time Start Time End Time Min. Max. Hin. Max. t-1in. Max. Min. Max. CI -125 0 160 min. p.w. -125 0 67.7 min. p.w. MEME N.R. -200 160 min. p.w. -125 0 67.7 min. p.w. AXX N.R. -200 160 min. p.w. -125 0 67.7 min. p.w. R/W Mode N.R. -200 16 0 min • p • w. -125 0 67.7 min. p.w. -/( MEMBUS 0 100 N. R. 1100 15.3 72.3 968.5 1086.9 DREADY * 600 900 700 1000 648.8 736.0 776.5 877.9 TACC RAM N.R. 800 N. R, 1200 522.5 623.4 963.5 1066.6 TACC PROM N.R. 900 N.R. 1200 535.5 698.9 970.5 1111.8 DI N.R. 0 1000 134.6 901.0 8MHZCL s.oo MH ± .01% 8.00 MHz ! .01%

2 ------·~

w 0 TIME IN NANOSECONI>S To 125' 2SO 37S S'OO 625 75"0 375" 1000 I JlS' J'2SO

8MHZCL

CI '~ 2lJOMIN ~

-. ME M t=. _}f 2 oo A1'"' r- }OO/v,IN ----;:.[ R>

/'S• .3 11 IN '16.8.5 MIN 30->TYP q'I8.5'"Typ I {) 8(, •'I 1Y1 MEM~U.Sy * 7 2.3 """"' "X SZ2., MIN --1 Str8.S TYP ------' '.B. 4 M /i)( j I u '£! ... •p ., l TAcc RRM 6.. !.8MIN' 6 72.ST>P --··-~~ ,:;,. 736.() /VI~I( - DJtT_qR. l<.fJM \ __),

SENICONDUCTOR :t-1ENORY TI!vliNG DIAGRAN FIGURE 3. 1

...... w TIME .II'~ N.t~ H65f.COI'IDS

To 12.5" 250 2-7.> 5oo b2.5' ?so 87.5' /DOD 1125" IZSo

8MHZCL

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13>7,1 !VII~ lf'/O.'tf11N f- 22].'J8o/C. /JoZ. 'J.qve;,. r----, I ---.it_ 1 i ,!f__M~_i(_ .. !'f-.37 ~7 M1_~ fU~ /VI D 11 T 11 OUT

SEtviiCONDUCTOR HEMORY TIMING DIAGRAH FIGURE 3. 1

w N TIME IN Nh!'!0SE.C.Of'IPS To 12r- Z5o. 3 75" 500 62~ 7SO 875" /ooo )I 2S"" 125'0

BMHZCL

fD,o "11~'~ CJ6/3.!> MIN 2D.o TYP 999. 5" TYP · *­ SJ.'j Mfl-< I{) 85, ~ 11~>( CEX - \ ..._ -17S".5/<-Ji~ - I no.f:fr..~,~, ___,, -1'1-t.oTyp L f<:- J4)1,o TYf • -c,g,,fv/A)( r i .ltl.21'vJ.q)t -- -· - - - --· -- OE'*

2J3,S't-1 1 N Ct72.0/VIIH - 1 /O>''J,O Tyf' 3o~,;TyP 531,6 fvl~))( 12.13,0 IVJ"/X PROM DRTR y;.:}L/0 ou-r 5_35"",<;" fVIJ"f 9 70,!: lvi/N S71,,o TYI) ---·?j /c)()o,S 7y/' ~cc. PROM , 69J.'j MJ1>( 1 ,,,,.~. /'4}1)( ~r------7/.}.• l/Nit../ 7 'I it. 0 T Y {' -----,.1 8 .!. 7, 2. /'·II-))( DltT..&~R. * PR.0/'1 iJ 1t3.) M/f'l 871f,S'TvP "'G. I,"! M"J)(

SEMICONDUCTOR MEMORY TIMING DIAGRAM FIGURE 3.1

w w 34'

Table 3.2 Active Component Tolerances Device Item Initial Value End of Life Unit Type at 25°C -55 S TA $+100°C vee = 5v 4 • 755 VCC ~ 5 • 25V Hin Nom Max Min Nom Max

54LS368 tPLH 3.5 7.0 15.0 3.5 10.0 21.5 ns tPHL 5.8 11.5 18.0 5.8 17.7 27.7 ns tPZH 9.0 18.0 35.0 9.0 25.7 50.1 ns tPZL 14.0 28.0 45.0 14.0 43.1 69.3 ns tPHZ 8.0 16.0 32.0 8.0 22.9 45.8 ns tPLZ 9.0 18.0 35.0 9.0 27.7 53.9 ns 54LS00 tPlH 4.5 9.0 15.0 4.5 12.9 21.5 ns 54LS04 54LS10 tPHL 5.0 10.0 15.0 5.0 15.4 23.1 ns 54LS20

54LS32 tPLH s.o 10.0 15.0 5.0 15.4 21.5 ns tPHL 7.0 14.0 22.0 7.0 21.6 33.9 ns 54LS08 tPLH 4.0 8.0 15.0 4.0 11.4 21.5 ns 54LS21 tPHL s.o 10.0 20.0 5.0 15.4 30.8 ns 54LS138 tPLH 9.0 18.0 27.0 9.0 25.7 38.7 ns tPHL 13.0 26.0 39.0 13.0 40.0 60. 1 ns S4LS86 tPLH 6.0 12.0 23.0 6.0 17.2 33.0 ns (other input tPHL 5.0 10.0 17.0 5.0 15.4 26.1 ns low) (other tPLH 10.0 20.0 30.0 10.0 28.7 43.0 ns input high) tPHL 6.5 13.0 22.0 6.5 20.1 34.0 ns 35

Table 3.2 Active Component Tolerances Device Item Initial Value End of Life Unit Type at 25°C -55 STA :$+100°C

vee = sv 4 e 7 5 $ VCC $ 5 • 2SV Min Nom Max Min Nom Max 34.4 57.3 ns 54LS75 t PLH 12.0 24.0 40.0 12.0 (D-Q~<) tPHL 3.5 7,0 15.0 3.5 10.0 23.1 ns J,. (G-Q") tPLH 8.0 16.0 30.0 8.0 22.8 43.0 ns tPHL 3.5 7.0 15.0 3.5 10.8 23.1 ns (G-Q) tPLH 7.5 15.0 27.0 7.5 21.5 38.7 ns tPHL 4,5 9.0 17.0 4.5 13.9 26.2 ns (Setup) tSET 20.0 ns 54LS164 tPLH 8.5 17.0 27.0 8.5 24.3 38.7 ns (Clock) (Clear) tPHL 12.0 24.0 36.0 12.0 37.0 55.4 ns 54LS01 tPLH 8.5 17.0 32.0 8.5 24.3 45.9 ns tPRL 7.5 15.0 28.0 7.5 23.1 43.1 ns Table 3.3 Passive Component Tolerances Resistance & Capacitance Initial Tol. Temp. Affects Life Final RSS Symbols at 25°C -55°C to 100°C Tolerance· CSR Type Capacitor C1 - C10 10% 10% 11.8% 20% CKR Type Capacitor Cl1 - C52 10% 15% 22.9% 30% RNR Type Resistor I

I R1 - R41 1% .4% 1.1% 2.5% I RLR Type Resistor R42 - R46 2% 1.6% 1.4% 5.0% RNR Type Resistors R43 - R45 1% .4% 1.1% 2.5% i

w 0! 37'

and 3.3 represents such tabulated tolerances; they were de- rived from manufacturer's data sheets. The data sheets have been further derated to allow for perfomance over the required temperature range, voltage range and end of life. In order to simplify the timing analysis it was sub­ divided into the following sub-analysis.

3.2.1 ADDRESS INPUT CIRCUIT Addresses AOO - Al3 are latched on the negative going edge of CLL and remain latched for the duration of a memo­ ry cycle. Refer to figure 2.1 and Al6- A19 in Appendix A for details. Addresses from the processor will be stable a minimum of 200 nanoseconds before CI.

3.2.1.1 Computation of Latest Possible Address Based on the signal path of figures Al6 - Al9 in Appendix A the following computation is performed:

DEVICES TYPE OF DELAY DELAY IN NA.f\:OSECONDS Min Typ Max

54LS20 TPHL -5.0 -10.0 -23.1 54LS00 TPLH -4.5 -9.0 -21.5 54LS368 TPHL -5.8 -11.5 -27.7 54LS75 I SETUP +22.0 +10.0 +5.0 TOTAL +6.7 -20.5 -67.3

As a result addresses have to be stable a minimum of 6.7 nanoseconds before CI. Therefore, the 200 nanoseconds number is acceptable. 38' p '

3.2.1.2 Computation of Time at which Valid Addresses are Present at the CMOS RAM Inputs Since, nonstandard logic levels are required at the inputs of the CMOS RAM use of SO% propagation delay num­ bers are no longer valid at this interface. The logic le­

vels required are Vcc 1-2v min. for logic "1" instead of 2.0v min. As a result of this, pullup resistors are re­

quired to guarantee the Vcc 1-2v level and provide satis­ factory noise margins at the logic "1" state. Figure 3.2 a simplification of figures A1 and A6 - A10 in Appendix A represents this typical interface cir­ cuit. Figure 3.3 is a simplified equivalent of figure 3.2.

3.2.1.2.1 Address Input L to H Transition The 54LS368 output is guaranteed to provide 2.4v at the rated output current, beyond this Rp is required to charge the input capacitance to VCCl-2v (Required voltage for minimum input high in CMOS). The time required to

reach VCCl-2v is t 1 + t 2 • Where t 1 is the time required to reach the maximum output capability of the buffer, and

time t 2 is the time required to raise it from 2.4v to vccl-2v. wnere t = t 1 + t 2 • Time t 1 Calculation

To calculate t 1 it is required to establish a simpli­ fied circuit model for the buffer in the high or logic "1" output state. Resistor Ra and voltage Va represent the HM65'14

A6XX

.5"4LS..368

ADDRESS PULLUP CIRCUIT FIGURE 3.2

Vcct

LOW TO HIGH TRANSITION HIGH TO LOW TR&~SITION EQUIVALENT CIRCUIT 3.3-A EQUIVALENT CIRCUIT 3.3-B C represents equivalent input capacitance of 24 CHOS RAHS plus stray capacitance.

ADDRESS INPUT EQUIVALENT CIRCUIT FIGURE 3.3 40 internal black-box output parameters of the 54LS368 device. The following represent 54LS368 parameters taken from a manufacturer's data sheets and application notes. Condition 1 - Output short circuited to ground. I min 30 rna 08 = I typ = 80 rna 08 I s max 130 rna 0 = Condition 2 Output current, I 1 rna 0 = V min 2.4 v 0 = v typ = 3.4 v 0 V max= 4.4 v 0 The computation of worst case Va and Ra parameters were made in conformance with the following table:

VCCl s.s v 4.4 v Min Min 130 rna s.o v 3.4 v Typ Typ 80 rna 4.5 v 2.4 v Max Max 30 rna

Based on figure 3.3-A the following equations were established. Where Rp has been open circuited. VCCl-V a VCC1-V a-Vo and Ra = Ios Ra = Io Therefore

and

Substituting numbers in accordance with the above 41 table. the following were obtained:

Ra max= 82.8 ohms Va max = 2. 0 2 v Ra typ = 43.0 ohms V a typ = 1.56 v Ra min= 34,4 ohms V a min = 1. 0 7 v

Having computed Va and Ra we can now use them in the model of figure 3.3-A to compute the t in the L to H tran- sition analysis. In the Laplace domain

VCCl V a v. ~s____ -=-s ___ -_v~o + = (v - -!)cs Ra 0 s v. ~ s +

Where Vi = initial voltage on C. Taking the inverse Laplace transform and solving for t, the following is ob- tained.

therefore

Time t 2 Calculation

At V0 = Vccl - Va' the buffer cannot source any more current, consequently Rp (Pullup Resistor) will have to charge the capacitor to the required logic ••1 .. voltage (VINH). Since Ra and Va are now out of the circuit, that is are open circuited; the equation for t can be equated to t 2 by open circuiting Ra and va. This results in the followings

where V = 0 VINH and Vi= Vcc 2 - Va this reduces to v 2 - v ln CC V INH a consequently

VCC2 - VINH - RpC ln ~~v:-:"'·-_;;;,..._"""'"' a

VCC2 - VI:t"-;"'H where -RpC ln V must be greater or equal to 0. a Computation of t \vas made using the following table:

Parameter tmin ttyp tmax

VCC1 4.50 v 5.00 v 5.50 v va 1.07 v 1.56 v 2.02 v . v.1. 0.40 v 0.20 v 0.10 v VINH 1.50 v 2.00 v 3.50 v Ra 34.4 ohms 43.0 ohms 82.8 ohms Rp 984 ohms 1000 ohms 1016 ohms c 160 pf 200 pf 250 pf t 23.5 ns 32.5 ns 62.7 ns 43

In order to compute the total delay it is necessary to add gate and flip-flop propagation delays. In addition it is known that address data will be stable at least 50 ns before cr. The following example illustrates the required calcu- lation.

DEVICES TYPE OF DELAY IN NANOSECONDS DELAY Min Typ Max

Stable Addr. TLH -200.0 -200.0 -200.0 54LS75 TPHL 3.5 7.0 23.1 54LS368 TPLH 3.5 7.0 21.5 Pullup TLH 23.5 32.5 62.7 Total TLH -169.5 -153.5 -92.7

3.2.1.2.2 Address In:Qut H to L Transition The 54LS368 output is guaranteed to sink the following currents:

1os min = -30 rna 1os typ = -80 rna 1os max= -130 rna Since the load capacitance is larger than that speci- fied for the 54LS368 device, its propagation delay has to be derated for the added load capacitor of 250 pf - 235 pf max., 188 pf typ. and 150 pf min. Figure 3.3-B is an equivalent model for the H to L transition. Where Vi is the initial voltage and C the load capacitor. 44' ~ '

In the Laplace domain

v.cs - v ocs + -~- and

v 0

Taking the inverse Laplace and solving for t, the following is obtained:

where t = VCCl and Vo = VINL therefore VCC1 - VINL - IoRP t -RpC ln = IoRP

Computation of t was made using the following tablec

Parameter tmin ttyp tmax

VCCl 4.50 v 5.00 v 5.50 v VINL 2.00 v 1.50 v 0.80 v Io 130 rna 80 rna 30 rna Rp 1016 ohms 1000 ohms 984 ohms c 150 p£: 188 pf 235 pf t 2.9 ns 8.4 ns 40.1 ns

Again in order to compute the total delay it is ne- cessary to add gate and flip-flop propagation delays. The following example illustrates the required calcu- lations: 45 ~ '

DEVICES TYPE OF DELAY IN NANOSECONDS DELAY Min Typ Max

Stable Addr. THL -200.0 -200.0 -200,0 54LS 75 TPLH 12.0 24.0 57.3 54LS368 TPHL 5,8 11.5 27.7 C load THL 2.9 8.4 40.1 Total THL -179.3 -156.1 -74.9

3.2.2 CMOS RAM CHIP ENABLE Computation of time at which valid Chip Enables are present at the CMOS RAM Chip Enable Inputs •

.,)~ 3.2.2.1 First 1K of CMOS RAM (SHE1") From schematic figures Al6 - Al8 in Appendix A it is

.,)~ evident that SME1" exhibits a problem similar to that de- scribed in section 3.2.1.2. However, since the 54LS01 driver has an open collector output, the analysis presen- ted in that section has to be slightly modified.

3.2.2.1.1 Low to High Transition ·'# Since only a 2,05K resistor is driving the SHEl" line to the required threshold the equivalent circuit is redu- ced to the following: VDD where vl = initial voltage c = load capacitance = input gvo capacitance of six C~lOS inputs and the output of 1cvl the 54LS01. Rp = value of pullup resistor. 46

In the Laplace domain v 0

taking the inverse Laplace

Vo - VDD solving for t we obtain t - -R C ln - p V1 - VDD

Computation of t was made using the following table:

Parameter tmin ttyp t max

VDD 4.50 v 5.00 v 5.50 v vo 1.50 v 2.00 v 3.50 v v1 0.40 v 0.20 v 0.10 v Rp 1999 ohms 2050 ohms 2101 ohms c 43.5 pf 54.4 pf 68.0 pf t 27.2 ns 52.4 ns 141.9 ns

In order to compute the total delay it is necessary to add gate and flip-flop propagation delays. The following example illustrates the required calcu- lation, 47

DEVICES TYPE OF DELAY IN NANOSECONDS DELAY Min Typ Max

54LS164 !CLOCK 875.0 875.0 875.0 54LS164 TPLH 8.5 17.0 38.7 54LS138 TPLH 9.0 18.0 38.7 54LS00 TPHL 5.0 10.0 23.1 54LS01 TPLH 8.5 17.0 45.9 Pullup TLH 27.2 52.4 141.9 Total TLH 933.2 989.4 1163.3

3.2.2.1.2 High to Low Transition The 54LS01 output is guaranteed to sink the following:

1os min = -30 rna 1os typ = -80 rna 1os max = -130 rna Since, the load capacitance is larger than that spe­ cified for the 54LS01 device, its propagation delay has to be derated for the added load capacitance of 60 pf - 15 pf or 45 pf max., 36 pf typ. and 28.8 pf min. Figure 3.3-B is an equivalent model for the H to L transition. Where v1 is the initial voltage and C the load capacitance. Consequently from section 3. 2 .1. 2.-2

Computation of t was made using the following table: 48.

Parameter tmin ttyp tmax vccl 4.50 v 5.00 v 5.50 v VINL 2.00 v 1.50 v 0.80 v Io 130 rna 80 rna 30 rna Rp 2101 ohms 2050 ohms 1999 ohms c 28.8 pf 36.0 pf 45.0 pf t 0.6 ns 1.6 ns 7.3 ns

The following example illustrates computation of the total delay.

DEVICES TYPE OF DELAY IN NANOSECONDS DELAY Min Typ Max

54LS164 TPLH 8.5 17.0 38.7 54LS138 TFHL 13.0 26.0 60.1 54LS00 TPLH 4.5 9.0 21.5 54LS01 TPHL 7.5 15.0 43.1 Pullup THL 0.6 1.6 7.3 Total THl 34.1 68.6 170.7

3.2.2.2 Second through fourth lK of CMOS RA!v1

..;,. .;~ (DMEl" - DME3") From the schematic figures A16 - A18 in Appendix A

..;,. ..;,. it is evident that DMEl" - DME3" exhibit a problem similar to that described in section 3.2.1.2, except that the dri­ ving element is a 54LS138 decoder.

3.2.2.2.1 Low to Hogh Transition Proceeding as in section 3.2.1.2 it is first necessary to find values of Ra and Va corresponding to the 54LS138. The 54LS138 parameters taken from a manufacturer's data 49"

sheets and application notes are as follows: Condition 1 - Output short circuited to ground. I s min = 30 rna 0 I s typ = 80 rna 0 I s max = 130 rna 0 Condition 2 Output current, I = 400 ua. 0 vo min = 2.4 v vo typ : 3.4 v vo max = 4.4 v Using computation techniques identical to those in section 3.2.1.2, the following was computed:

Ra max= 81.1 ohms va max = 2.07 v Ra typ = 42.7 ohms va typ = 1.58 v Ra min = 34.3 ohms va min = 1.04 v Having computed Va and Ra we can now use them in the model of figure 3. 3 - A to compute the time t in the L to H transition analysis. Time t Calculation

= -

VCC2 - VINH -Rpc ln --~~v~-=~ a Computation of t was made using the following table: so

Parameter t m1.n . ttyp t max

VCC1 /VCC2 4.50 v 5.00 v s.so v va 1.04 v 1.58 v 2.07 v v1 0.40 v 0.20 v 0.10 v VINH 1.50 v 2.00 v 3.50 v Ra 34.3 ohms 42.7 ohms 81.1 ohms Rp 1999 ohms 2050 ohms 2101 ohms c 28.8 pf 36.0 pf 45.0 pf t 5.3 ns 7.5 ns 16.6 ns

The following example illustrates computation of the total delay.

DEVICES TYPE OF DELAY IN NANOSECONDS DELAY Min Typ Max

54LS164 TCLCCK 875.0 875.0 875.0 54LS164 TPLH 8.5 17.0 38.7 54LS138 TPLH 9.0 18.0 38.7 Pullup TLH 5.3 7.5 16.6 Total 'T'... LH 897.8 917.5 969.0

3.2.2.2.2 HiBh to Low Transition Since, the sink capability of the 54LS138 is identical to the 54LS01, computation is identical to that in section 3.2.2.1.2 for the High to Low transition, or tmin = 0.6 ns, ttyp = 1.6 ns and tmax = 7.3 ns. The following example illustrates computation of the delay. SI f '

DEVICES TYPE OF DELAY IN N&~OSECONDS DELAY Min Typ Max

54LS164 TPLH 8.5 17.0 38.7 54LS138 TPHL 13.0 26.0 60.1 C load THL 0.6 1.6 7.3 Total THL 22.1 44.6 106.1

3.2.3 CMOS RAM WRITE ENABLE Computation of the time at which valid Write Enables are present at the CMOS RAM Write Enable inputs.

J. 3.2.3.1 First 1K of CMOS RA.i"-1 (WE1") From schematic figures A16 - A18 in Appendix A it is

J. evident that WE1~ exhibits a problem similar to that de- scribed in section 3.2.1.2. However, since the 54LS01 driver has an open collector output, the analysis is iden­ tical to that in section 3.2.2.1.

3.2.3.1.1 Low to High Transition From section 3.2.2.1 tmin = 27.2 ns, ttyp = 52.4 ns and t max = 141.9 ns. In order to compute the total delay it is necessary to add gate and flip-flop propagation delays. The following example illustrates the required calcu­ lation. 52'

DEVICES TYPE OF DELAY IN NANOSECONDS DELAY Min Typ Max

54LS164 TCLOCK 875.0 875 .o 875.0 54LS164 TPLH 8.5 17.0 38.7 54LS138 TPLH 9.0 18.0 38.7 54LS10 TPHL 5.0 10.0 23.1 54LS01 TPLH 8.5 17.0 45.9 Pullup TLH 27.2 52.4 141.9 Total TLH 933.2 989.4 1163.3

3.2.3.1.2 £iiBh to Low Transition

From section 3.2.2.1 'tmin = 0.6 ns, ttyp = 1.6 ns and t max = 7. 3 ns. In order to compute the total delay it is necessary to add gate and flip-flop propagation delays. The following example illustrates the required calcu ... lation:

DEVICES TYPE OF DELAY IN NANOSECONDS DELAY Min Typ Max

54LS164 TPLH 8.5 17.0 38.7 54LS138 TPHL 13.0 26.0 60.1 54LS10 TPLH 4.5 9.0 21.5 54LS01 TPHL 7.5 15.0 43.1 C load THL 0.6 1.6 7.3 Total THL 34.1 68.6 170.7 ..... 3.2.3.2 Remaining 3K of CMOS RAM (TNE2") From schematic figures Al6 - Al8 in Appendix A it is evident that WE2"·'· exhibits similar problems to those des- cribed in section 3.2.1.2. However, since the 54LS01 dri- 53 ver has an open collector output, the analysis is identical to that in section 3.2.2.1, except for added C and decrea- sed Rp.

3.2.3.2.1 ~to High Transition Computation for t was made using the equation from ,, section 3.2.2.1 and the following table.

Parameter tmin ttyp tmax

VDD 4.50 v s.oo v 5.50 v vo 1.50 v 2.00 v 3.50 v v1 0.40 v 0.20 v 0.10 v Rp 1502 ohms 1540 ohms 1579 OhnlS c 120.3 pf 150.4 pf 188.0 pf t 56.4 ns 108.9 ns 294.8 ns

In order to compute the total delay it is necessary to add gate and flip-flop propagation delays. The following example illustrates the required calcu- lation.

DEVICES TYPE OF DELAY IN NANOSECONDS DELAY Min Typ rv!ax

54LS164 I CLOCK 875.0 875.0 875.0 54LS164 TPLH 8.5 17.0 38.7 54LS138 TPLH 9.0 18.0 38.7 54LS10 TPHL 5.0 10.0 23.1 54LS01 TPLH 8.5 17.0 45.9 Pullup TLH 56.4 108.9 294.8 Total TLH 962.4 1045.9 1316.2 54

3.2.3.2.2 High to Low Tran~ition Computation of t was made using the equation for t from section 3.2.2.1 and the following table:

Parameter tmin ttyp tmax 4.50 v 5.00 v 5.50 v 2.00 v 1.50 v 0.80 v 130 rna 80 rna 30 rna 1502 ohms 1540 ohms 1579 ohms 120.3 pf 150.4 pf 188.0 pf 2.3 ns 6.9 ns 32.2 ns

The following example illustrates computation of the total delay.

DEVICES TYPE OF DELAY IN NANOSECOI'·IDS DELAY Min Typ Max

54LS164 TPLH 8.5 17.0 38.7 54LS138 TPHL 13.0 26.0 60.1 54LS10 TPLH 4.5 9.0 21.5 54LS01 TPHL 7.5 15.0 43.1 C load THL ---2.3 6.9 ---32.2 Total THL 35.8 73.9 195.6

3.2.4 CMOS R&~ DATA OUTPUT TIME The signal path is per schematic figures Al - AlO and A16 - A18 in Appendix A. In section 3.2.2 it was determi- ned that the latest Chip Enable occurres at the input of the first lK of CMOS RAM, consequently the latest access time will also occur in the first lK of CMOS :RM-1. 3.2.4.1 Low to High Transition Analysis From figures A1 - A10 in Appendix A it becomes appa- rent that in order to produce a logic 11 1" data output, the 6514 output must be at logic "0". Since a 5.9K pullup re­ sistor is present at the output of the 6514 CMOS RAM, not all its output current will be available to discharge the load capacitance. Consequently, the circuit must be dera­ ted for the extra load capacitance and the pullup resistor.

The access time of the 6514 CMOS RAM is specified dri­ ving one TTL load and 50 pf. The load at the output of the RAM is one low power Shottky TTL load, about 50 pf max. and a 5.9K pullup resistor. Input current of a TTL load is 1.6 ma max. and of the 5.9K and low power Shottky combina­ tion 1.3 rna, which is less than 1.6 rna, therefore no dera- ting of the CMOS RAM is required. The following example illustrates the access time com- putation.

DEVICES TYPE OF DELAY IN NANOSECONDS DELAY Min Typ Max

54LS164 TPLH 8.5 17.0 38.7 54LS138 TPHL 13.0 26.0 60.1 54LS00 TPLH 4.5 9.0 21.5 54LS01 TPHL 7.5 15.0 43.1 C load THL 0.6 1.6 7.3 6514 TACC 100.0 150.0 300.0 54LS368 TPLH 3.5 7.0 21.5 Total TPLH 137.1 225.6 492.2 The following example illustrates the computation of the time at which data is no longer valid at the output.

DEVICES TYPE OF DELAY IN NANOSECO~'DS DELAY Min Typ Max

54LS164 TCLOCK 875.0 875.0 875.0 54LS164 TPLH 8,5 17.0 38.7 54LS138 TPLH 9.0 18.0 38.7 54LS00 TPHL s.o 10.0 23.1 54LS01 TPLH 8.5 17.0 45.9 Pullup TLH 56.4 108.9 294.8 6514 TPDH 25.0 50.0 100.0 54LS368 TPHL 5,8 11.5 27.7 Total THL 993.2 1107.7 1443.9

3.2.4.2 High to Low Transition Analysis From figures A1 - AlO in Appendix A it become appa- rent that in order to produce a logic "0" data output, the 6514 CMOS RAM output must be at logic "1". The access time of the CMOS RAM is specified driving one TTL load and 50 pf. The load at the output of the RAM is actually a low power Shottky input load, about 50 pf max. and a 5.9K pullup resistor. In this case the 5.9K pullup resistor actually decreases the access time. How- ever, since worst case numbers are sought its effect is neglected and the actual RAM access time used. The following example illustrates the access time com­ putation. DEVICES TYPE OF DELAY IN N&~OSECONDS DELAY Min Typ Max

54LS164 TPLH 8.5 17.0 38. 7 54LS138 TPHL 13.0 26.0 60.1 54LS00 TPLH 4.5 9.0 21.5 54LS01 TPHL 7.5 15.0 43.1 C load THL 0.6 1.6 7.3 6514 TACC 100.0 150.0 300.0 54LS368 TPHL 5.8 11.5 27.7 Total THL 139.9 230.1 498.4

The following example illustrates the computation of the time at which data is no longer valid at the output.

DEVICES TYPE OF DELAY IN NANOSECONDS DELAY Nin Typ Nax

54LS164 TCLOCK 875.0 875.0 875.0 54LS164 TPLH 8.5 17.0 38.7 54LS 138 TPLH 9.0 18.0 38.7 54LS00 TPHL 5.0 10.0 23.1 54LS01 TPLH 8.5 17.0 45.9 Pullup TLH 56.4 108.9 294.8 6514 TPDH 25.0 50.0 100.0 54LS368 TPLH 3.5 7.0 21.5 Total TPLH 990.9 1102.9 1437. 7

3.2.5 DATA OUTPUT BUFFER ENABLE/DISABLE (TACC RAM) Data output buffers must be enabled when data becomes available and disabled at the end of a cycle. The following is a computation of output data enable time. See figures Al6 - A18 in Appendix A for the signal 53· path.

DEVICES TYPE OF DELAY IN NANOSECONDS DELAY Min Typ Hax

54LS164 TCLOCK 500.0 500.0 500.0 54LS164 TPLH 8.5 17.0 38.7 54LS10 TPHL 5.0 10.0 23.1 54LS368 TPZL/TPZH 9.0 21.5 61.6 Total TPZL/TPZH 522.5 548.5 623.4

The following represents a computation of output dis- able time.

DEVICES TYPE OF DELAY IN NANOSECONDS DELAY Min Typ Max

54LS164 TCLOCK 875.0 875.0 875.0 54LS164 TPLH 8.5 17.0 38.7 54LS04 TPHL 5.0 10.0 23.1 54LS10 .TPLH 4.5 9.0 21.5 54LS368 TPLZ/TPHZ 8.0 17.0 53.9 Total TPLZ/TPHZ 901.0 928.0 1012.2

1 3.2.6 DATA READY CONFUTATION (DREADY :) Data Ready strobe must be present during the time that data is available to indicate the presence of valid data. The following is a computation of the Data Ready strobe. See figures A16 - Al8 in Appendix A for the signal path. 59

DEVICES TYPE OF DELAY IN NANOSECONDS DELAY Min Typ Max

54LS164 TCLOCK 625.0 625.0 625.0 54LS164 TPLH 8.5 17.0 38.7 54LS00 TPHL 5.0 10.0 23.1 54LS00 TPLH 4.5 9.0 21.5 54LS368 TPHL 5.8 11.5 27.7 Total TPHL 648.8 672.5 736 .o

DEVICES TYPE OF DELAY IN NANOSECOf\ll)S DELAY Min Typ Max

54LS164 TCLOCK 750.0 750.0 750.0 54LS164 TPLH 8.5 17.0 38.7 54LS04 TPHL 5.0 10.0 23.1 54LS00 TPLH 4.5 9.0 21.5 54LS00 TPHL 5.0 10.0 23.1 54LS368 TPLH 3.5 7.0 21.5 Total TPLH 776.5 803.0 877.9

.,)# 3.2.7 INPUT DATA BUFFER ENABLE (CIE") Data must be present at the input of the CMOS RAM for at least 200 ns before Write Enable goes to the logic "1" state. Since nonstandard logic levels are required at the inputs of the CMOS RAM, computation is similar to that of section 3.2.1.2. The following is a computation of Input Data require- rnents at the CMOS RAM input.

3.2.7.1 Losic "1" Input Computation Time t was. computed using the equation for t from section 3.2.1.2 and the following tables 60'

Parameter t . m~n

VCCl s.so v va 2.02 v v1 0.10 v VINH 3.50 v Ra 82.8 ohms Rp 6064 ohms c 50 pf t 3.5 ns 7.0 ns 22.7 ns (TPLH of (TPLH of 54LS368) 54LS368)

In order to compute the total delay it is necessary to add gate and flip-flop propagation delays. The following is an example of the computation:

Computation of Start Time

DEVICES TYPE OF DELAY IN NANOSECONDS DELAY Min Typ Nax

54LS164 TPLH 8.5 17.0 38.7 54LS10 TPHL s.o 10.0 23.1 54LS368 TPZH 9.0 18.0 so .1 Pullup TLH 22.7 Total TLH 22.5 45.0 134.6 6l

Computation of End Time

DEVICES TYPE OF DELAY IN N&~OSECO~~S DELAY Min Typ Max

54LS164 TCLOCK 875.0 875.0 875.0 54LS164 TPLH 8.5 17.0 38.7 54LS04 TPHL 5.0 10.0 23.1 54LS10 TPLH 4.5 9.0 21.5 54LS368 TPHZ 8.0 16.0 45.8 Total TPHZ 901.0 927.0 1004. 1

3.2.7.2 Logic "0" In2ut Com2utation Propagation delay of the 54LS368 is specified driving a 50 pf and one TTL load, therefore no other derating is necessary.

Computation of Start Time

DEVICES TYPE OF DELAY IN NAi.'l"OSECOf.l"'DS DELAY Min Typ Max

54LS164 TPLH 8.5 17.0 38.7 54LS10 TPHL s.o 10.0 23.1 54LS368 TPZL 14.0 28.0 69.3 Total TPZL 27.5 55.0 131.1

ComEutation of End Time ~- --

62

DEVICES TYPE OF DELAY IN NANOSECONDS DELAY Min Typ Max

54LS164 I CLOCK 937.5 937.5 937.5 54LS164 TPLH 8.5 17.0 38.7 54LS04 TPLH 4.5 9.0 21.5 54LS04 TPHL 5,0 10.0 23.1 54LS10 TPLH 4.5 9.0 21.5 54LS368 TPLZ 9,0 18.0 53.9 Total TPLZ 969.0 1000.5 1096. 2 "'* .),. 3.2.8 UVE PROM CHIP ENABLE (CEl" - CE4") Address decoding path assumes that strobe is present.

3.2.8.1 Start of ChiD Enable

DEVICES TYPE OF DELAY IN NANOSECONDS DELAY Min Typ Max Stable Addr. TLH/THL -200.0 -200.0 -200.0 54LS75 TPHL/TPLH 4.5 12.0 38.7 54LS138 TPHL 13.0 26 .o 60.1 54LS86 TPHL 5.0 10.0 26. 1 54LS32 TPHL 7.0 14.0 33.9 Total TPHL -170.5 -138.0 -41.2

Strobe path assume addresses are present.

DEVICES TYPE OF DELAY IN NANOSEC0~1)S DELAY Min Typ Nax

54LS00 TPHL 5.0 10.0 23.1 54LS08 TPHL ~ -10.0 30.8 Total TPHL 10.0 20.0 53.9 63'

3.2.8.2 End of Chin Enable

DEVICES TYPE OF DELAY IN N&~OSECONDS DELAY Min Typ Max

54LS04 TPLH 4.5 9.0 21.5 54LS164 TCLOCK 937.5 937.5 937.5 54LS164 TPLH 8.5 17.0 38.7 54LS04 TPLH 4.5 9.0 21.5' 54LS04 TPHL 5.0 10.0 23.1 54LS00 TPLH 4.5 9.0 21.5 54LS08 TPLH 4.0 8.0 21.5 Total TPLH 968.5 999.5 1085.3

.r,. >k 3.2.9 UVE PROM OUTPUT ENABLE (OEl"' - OE4"')

DEVICES TYPE OF DELAY IN N&~OSECONDS DELAY Min Typ Max Stable Addr. TLH/THL -200,0 -200.0 -200.0 54LS75 TPHL/TPLH 4.5 12.0 38.7 54LS 138 TPHL 13.0 26.0 60.1 54LS86 TPHL 5.0 10.0 26.1 54LS32 TPHL 7.0 14.0 33.9 Total TPHL -170.5 -148.0 -41.2

DEVICES TYPE OF DELAY IN NAJ.~OSECONDS DELAY Min Typ Hax Stable Addr. TLH/THL -200.0 -200.0 -200,0 54LS75 TPLH/TPHL 4.5 12.0 38.7 54LS138 TPLH 9.0 18.0 38.7 54LS86 TPLH 6.0 12.0 33.0 54LS32 TPLH 5.0 10.0 21.5 Total TPLH -175.5 -148.0 -68.1 64

3.2.10 LVE PROM DATA OUTPUT TIME

DEVICES TYPE OF DELAY IN NANOSECONDS DELAY Min Typ Max

...~ CEX" from To THL 10.0 20.0 53.9 M2716 TACC 200.0 280.0 450.0 54LS368 TPLH/TPHL 3.5 9.3 27.7 Total TPLH/TPHL 213.5 309.3 531.6

DEVICES TYPE OF DELAY IN NANOSECONDS DELAY Min Typ Max

''~ CEX" from To TLH 968.5 999.5 1085.3 M2716 TPF o.o 50.0 100.0 54LS368 TPLH/TPHL 3.5 9.5 27.7 Total TPLH/TPHL 972.0 1059.0 1213.0

3.2.11 L7E PROM OUTPUT BUFFER ENABLE (TACC PROM)

DEVICES TYPE OF DELAY IN NANOSECONDS DELAY Min Typ Max

54LS164 TCLOCK 500.0 500.0 500.0 54LS164 TPLH 8.5 17.0 38. 7• 54LS 138 TPHL 13.0 26.0 60.1 54LS21 TPHL 5.0 10.0 30.8 54LS368 TPZL/TPZH 9.0 23.0 69.3 Total 1PZL/TPZH 535.5 576.0 698.9 - ·- - -· - -~ ------.. ------

65 p '

DEVICES TYPE OF DELAY IN NANOSECONDS DELAY Min Typ 't>'lax

54LS04 TPLH 4.5 9.0 21.5 54LS164 TCLOCK 937.5 937.5 937.5 54LS164 TPLH 8.5 17.0 38.7 54LS138 TPLH 9.0 18.0 38.7 54LS21 TPLH 4.0 8.0 21.5 54LS368 TPLZ/TPHZ 7.0 11.0 53.9 Total TPLZ/TPHZ 970.5 1000.5 1111.8

..J~ 3.2.12 DATA READY PROM (DRE.ADY")

DEVICES TYPE OF DELAY IN NAL'10SECOf.iDS DELAY Min Typ Max

54LS04 TPLH 4.5 9.0 21.5 54LS164 TCLCCK 687.5 687.5 687.5 54LS164 TPLH 8.5 17.0 38.7 54LS00 TFHL 5.0 10.0 38.7 54LS00 TPLH 4.5 9.0 23.1 54LS368 TPHL 5.8 11.5 --27.7 Total TPHL 715.8 744.0 837.2

DEVICES TYPE OF DELAY IN NANOSECOl:'iuS DELAY Min Typ Max

54LS04 TPLH 4.5 9.0 21.5 54LS164 TPLH 8.5 17.0 38.7 54LS164 TCLOCK 812.5 812.5 812.5 54LS04 TPHL 5.0 10.0 23.1 54LS00 TPLH 4.5 9.0 21.5 54LS00 TPHL 5.0 10.0 23.1 54LS368 TPLH 3.5 7.0 21.5 Total TPLH 843.5 874.5 961.9 66

.J. 3.2.13 MEHORY BUSY (MBUSY")

DEVICES TYPE OF DELAY IN NANOSECONDS DELAY Min Typ Max

54LS20 TPHL 5.0 10.0 23.1 54LS00 TPLH 4.5 9.0 21.5 54LS368 TPHL 5.8 11.5 27.7 Total TPHL 15.3 30.5 72.3

DEVICES TYPE OF DELAY IN NANOSECO~'US DELAY Min Typ Max

54LS04 TPLH 4.5 9.0 21.5 54LS164 TCLOCK 937.5 937.5 937.5 54LS164 TPLH 8.5 17.0 38.7 54LS04 TPHL 5.0 10.0 23.1 54LS00 TPLH 4.5 9.0 21.5 54LS00 T 5.0 10.0 23.1 PHI. 54LS368 TPLH 3.5 7.0 21.5 Total TPLH 968.5 998.5 1086.9

3.2.14 CYCLE INITIATE (CI) Start

DEVICES TYPE OF DELAY IN N&~OSECONDS DELAY Min Typ Max

54LS20 TPHL 5.0 10.0 23.1 54LS00 TPLH 4.5 9.0 21.5 54LS164 TSEIUP 3.8 7.5 21.5 Total TLH 13.3 26.5 66.1

End 67

DEVICES TYPE OF DELAY IN NANOSECONDS DELAY Min Typ Max

S4LS20 TPt':L s.o 10.0 23.1 54LS00 TPLH 4.5 9.0 21.5 54LS00 TPHL s.o 10.0 23.1 Total TPHL 14.5 29.0 67.7

3.3 INPUT/OUTPUT LOADING ANALYSIS The loading analysis of the semiconductor memory is tabulated in table B1 in Appendix B. The current convention used, specifies conventional current flowing into a device as positive, current flowing out of a device as negative.

3.4 POWER &~ALYSIS The power is calculated for four modes of operation: Standby Mode, table B2 in Appendix B

CMOS RAM Cycling, table B3 in Appendix B UVE PROM Cycling, table B4 in Appendix B Programming Mode, table BS in Appendix B

Component Power Dissipation, table B6 in Appen- dix B

3.5 DATA RETENTION SWITCH ANALYSIS The data retention switch is analyzed for turn-on and turn-off characteristics, data retention time and power dissipation. Figure A19 in Appendix A is a schematic representation of the data retention switch. 68

3.5.1 TRANSISTOR PARAMETERS The following transistor parameters were used in the computations that follow. 3.5.1.1 . Ql, Q3, Q4 - 2N3762A Transistors Temperature HFE @ Ic = SO rna Min Typ Max -55°C 23 57 91 +.94% +25°C 40 100 160 +100°C 64 160 256 +.80%

HFE @ Ic = 1 amp -55°C 19 57 81 +.72% +25°C 30 90 120 +100°C 37 110 14 7 +.30%

-55°C • 76v .90v 1.04v -1.7mv +25°C .62v • 76v .90v +100°C .49v .63v .77v -1. 7mv

-55°C .97v 1.23v 1.4 7v -.90mv +25°c .90v l.lSv 1.40v +100°C .84v 1.09v 1.34v -.7Smv

veE sat @ Ic = SO rna -SS°C .04Sv .065v .085v +.lmv +25°C • 053v • 073v .093v +100°C .060v .080v .100v +.lmv

VCE sat @ Ic = 1 amp -55°C .116v .496v .876v +.3mv +25°C .140v .520v .900v +100°C .196v .576v ,956v +. 75mv 69

Temperature HFER @ Ic = 25 rna Min Typ Max 2 4 8 3.5.1.2 Q2- 2N2369A Transistor Temperature Min Typ Max -SS°C 20 so 60 +. 75% +25°C 40 100 120 +100°C 52 130 156 +.40%

-55°C .84v .9lv .99v -1. 7mv +25°C .70v • 78v .8Sv +100°C .57v .65v .72v -1. 7mv

VeE sat @ Ic = 5 rna -S5°C .Olv ,08v .23v +.3mv +25°C .03v .lOv .2Sv +100°C .OSv .12v .27v +.3mv 3.5.2 ZENER DIODE PARAMETER The following zener diode parameters were used in the computations that follow. 3.5.2.1 D1 - 1N4371A Zener Diode

Temperature VZ @ r 2 = 20 rna 1:::. /°C Min Typ Max -55°C 2.729v 2.862v 3.016v -.08% +25°C 2.565v 2.700v 2.835v +100°C 2.411v 2.527v 2.66Sv -.08% 70

3.5.3 MISCELLANEOUS COMPUTATION

3.5.3.1 Computation of IDD- Hold Current During Power Off

Devices Type IDD Current in ua Min Typ Max M1 - MS HM6514-2 .05 .so 250 .o R11 2.05K .02 .10 105.0 Rl2 2.05K .02 .10 105.0 Ql 2N3762A .01 • 10 10.0 Q2 2N2369A .01 .10 18.0 Q3 2N3762A .01 .10 10.0 Total .12 1.00 498.0

3.5.3.2 Computation of RLD - Equival~nt Load Resistor on VDD VDD Equivalent RLD ~ ---I DD Sv RLD typ ~ 1.0 ua ~ s.o Megohms 4.75v RLD max = :TLua ~ 39.58 Megohms 5.25v RLD min = 498 ua = 10.54 Kelohms

3.5.3.3 Computation of RIN - Equivalent Load Resistor on VCCl Module Standby Current in rna Min Typ Max 285.75 571.50 970.23 71 ~ '

vcc1 \Vhere equivalent = RIN Icc1 5.25v RIN min = 970.2"3 rna = 5.41 ohms 5.00v RIN typ = 571.50 rna = 8.75 ohms 4.75v RIN max = 2'85.75 rna = 16.62 ohms

3.5.3.4 Computation of CIN - Equivalent Load Capacitor

----on VCC1 CIN typ = (88 uf + 1.3 uf) ~ 20% = 89.3 uf ~ 20% CIN min = 71.4 uf CIN max= 107.2 uf

3.5.3.5 Computation of CLD - Equivalent Load Capacitor on VDD

CLD typ = (66 uf + .2 uf) ~ 20% = 66.2 uf + 20% CLD min = 53.0 uf CLD max= 79.4 uf

3.5.4 CALCULATION OF RESISTOR VALUES

3.5.4.1 R39 Calculation

VCC1 - vz - VBE2 VCC1 - Vz Iz = R39 + R3g let Iz = 20 rna and Ic2 = 10 rna max VCC1 - vz - VBE2 then r 82 = R39 7Z

- VBE2 and R39 = therefore 1c2 HFE 4.75v- 3.016v- .99v R39 max = rr rna = 744.0 ohms 10-

let R39 = 715 ohms

3.5.4.2 R38 Calculation

VCCl - Vz R38 = ~.;;....;;...-.:-:-~--::-:-- VCCl - VBE2 1z - R39 5.00v- 2.70v R38 typ = S.OOv- .7ov~ = 128.6 ohms 20 rna - 715 let R38 = 121 ohms

3.5.4.3 R41 Calculation

Let lEBO~ ICEX = 10 ua max @ 100°C let VBC~ VBE :S.49v@ 100°C to maintain cutoff v 9 then R41 = I:~ and R41 max = id ~a = 49 Kohms

Storage Char8e Considerations

cib = 80 pf T = CibxR41 S 500 ns

and R41 5 s~g ~; = 6. 25 Kohms let R41 = 4.87 Kohms

3.5.4.4 R42 Calculations

Since the transistor is rated at I max = 1. 5 amps, c the B to E diode should withstand at least 1/10 of Ic max or 150 rna. 73

VCCl - VBE3 R42 = and 1B3 5.25v - .84v R42 min = 150 rna = 29.4 ohms let R42 = 33 ohms

3.5.4.5 R40 Calculation

R40 where Icl =

let 1DD = 35 rna max, then 4.7Sv 1. 04v - .23v R40 max= - = 940.2 ohms ~5 rna + T.04v - .084v IO 4.75r--- let R40 = 909 ohms

3.5.4.6 R43 Calculation Let max. tolerable voltage drop across R43 during discharge = VR 43 = 100 mv VR43 R43 100 mv = 1DD- and R4 3 max = 5TS"Ua = 19 3 • 1 ohms let R43 = 187 ohms

3.5.4.7 R44 Calculation Let R45 = 4.7 Kohms! 10%

VCC1 - VBE1 - Vsat2 R44 = where Ic = = 70 rna 1c4 VBE4 4 HFE + R45""

R44 max 4.75v- 1.04v- .87v = 70 rna + l.04v = 393.4 ohms . 10 4:DK 74

let R44 = 383 ohms

3.5.4.8 R46 Calculation IcE(Q3) S 75% of ICE max = .7Sxl.5 amps= 1.125 amps vCCl - vsat3 veel - v sat3 ( 3 ) and R46 = ICE Q = R46 ICE3 . 5.25v - .OSv _ h R46 m1 n = 1.125 amps - 4 • 62 0 ms let R46 = 5.6 ohms

3.5.5 POWER COMPUTATION OF DATA P~T&~TION COMPONENTS

3. 5. 5.1 Dl - 1N4371A, 2. 7v Zener Diode

I 2 nom = 20 rna VCCl - Vz - VBE2 VCCl - Vz Iz = - R39 + R38 2 2 VCClVz - Vz - VzVBE2 VCClVZ- Vz

Pz = IzXVz = R39L + R"'8...)

S.Ox2.7 - 2.72 - 2.7x.78 + 5x2.7 - 2.72 Pz typ = IS 121

= 57. 1 mw 2 P 5.2Sx2.411 - 2.411 - 2.411x.S7 2 max..-= 697.! 2 + 5.2Sx2.411 - 2.411 = . mw - I18.0 65 9 4. 7Sx3. 016 3.0162 - 3.016x.99 Pz min = - 723.9 4.75x3.016 - 3. 016 2 + t24.o = 45.2 mw 75

3.5.5.2 R38 - 121 ohms + 2.5% 2

P typ = (5.0- 2.7)2- 43.7 mw 121.0 -

5 25 2 411 2 P max= < · 118.0- · ) = 68.3 mw

4 75 16 2 P min= < · 124:u2 l- = 24.2 mw

3.5.5.3 R39 - 715 ohms ~ 2.5%

2 p typ = (5.0- 2i~- .78) = 3.2 mw

(5.25 - 2.411 - .57) 2 - 7 4 P max = 697.1 - · mw

. (4. 75 - 3.016 - .99) 2 0 P m~n = 723 •9 =· .8 mw

3.5.5.4 R40 - 909 ohms ~ 2.5% 2 (VCC1 - VBEl - Vsat2) p = R40

(5.0- .76- .1)2 18.9 mw P typ = 909 =

(5.25 - .49 - .05) 2 P max= 886.3 = 25.0 mw (4.75 1.04 - .23) 2 P min = 931.- i = 13.0 mw 76

3.5.5.5 R41, R45 - 4.87: Kohms + 2.5% 2 2 VBCl VBE4 P =--RZIT = R45

0.76 2 p typ = 4:g7K = 118.6 uw

1. 04 2 P max= 4.?SK = 227.7 uw

0.492 P min= 4~~ = 48.1 uw

3.5.5.6 R42 - 33 ohms + 5%

p =

2 p typ (5.0- · 76 ) = 498.2 mw short circuit = 33

5 2 49 2 p max= < • §2: 2· ) = 703.7 mw short circuit

4 7 1 04 2 p min= < • §3: 8 • ) = 407.2 mw short circuit P max operating = 0,0 mw

3.5.5.7 R43 - 187 ohms ± 2.5%

2 073 P typ = {2~i 8 ; ) = 129.8 mw short circuit ? p max= ( 5 •25 - · 045 )- 148.6 mw short circuit 182.3 = 7T

2 P min= < 4 ·i~r:,~l_ = 112.8 mw short circuit

P max operating= 0.0 mw

3.5.5.8 R44 - 383 ohms ~ 2.5% 2 (VCCl - VBE4 - Vsat2) p = Rq:q-----

p typ = (5.0- .76- .1)2 = 44.8 mw 383.0

(5.25 - .49 - .05) 2 59 P max = 373 •4 = .4 mw

·n = (4.75- 1.04- .23) 2 P ml. 392.6 = 30 •8 mw

3.5.5.9 R46 - 5. 6 ohm~s-~__,.;.5~%

p tv"'p = (5.05:0 +- 187.07)2 x 5 • 6-- 3 • 7 mw

25 2 P max= (~·. 88 +- i~i~. . .) ) x5.88 = 4.5 mw

3.5.5.10 Q1- 2N3762A Transistor

p = 1DDVsatl + IBVBE1

v 1 - VBEl - vsat2 where IB = CC R4U---- 78

2 p typ = .025x.073 + 5 • 0 X· 76 ~~~lx. 7 £ = 5.2 mw

2 p max= . 0377x.l + 5.25x1.04 - 8 ~ 6 ~j - .Olxl.04 = 8. 3 mw 2 .0005x. + 4.75x.49- .49 - .Olx.49 P min = 045 931.7 = 2.2 mw

3.5.5.11 Q2 - 2N2369A Transistor

- - p VCCl vz VBE2 VCCl - VBE1 - Vsat2 V = R39 -. VBE2 + R40 sat2

p 5.0 2.7 78 5.0 - .76 - .1 1 typ = - 715.0- · x. 78 + 909.0 - x. = 2.1 mw

p 5.25 2.411 - 99 max= - 697. I • x.99

25 76 23 + ~ - 886.3· - • x.23 = 3.7 mw 4.75 3.016 57 P min = -732.9 - · x.S7 4.75 - .77 - 01 + 931.7 · x.01 = 0.9 mw

3.5.5.12 Q3- 2N3762A Transistor p = 1B3VBE3 + Vsat31C3 79

VCC1 - VBE3 VCC1 - Vsat3 + p = R42 VBE3 + ( "R46 + Rzu- 1DD) Vsat3

= 5.25 - 1.04 1 04 + (5.25 - .1 ) 10 P max 31.4 X • 5. 32 + l8D x. = 145.6 mw

P typ = 0.0 mw Transistor normally cutoff

P min = 0.0 mw Transistor normally cutoff

3.5.5.13 Q4 - 2N3762A Transistor p = IB4VBE4 + Vsat4ICC2

"eel - "BE4 - v sat2 v p = R44 BE4 + Vsat4 1CC2 5 0 P typ = • - 38;~ 0 =---J:.x.76 + .073x.0244 = 10.0 mw 5 P max= • 25 - 3 t1?~ -~xl.04 + .lx.0681 = 18.4 mw P min= 4 • 75 jgz~g- ·23x.49 + .Olx.0011 = 5.0 mw 3.5.6 Total Power Consumption of the Data Retention Switch

Devices Type Current in rna Power in mw Typical Maximum Typical Maximum Dl 1N4371A 20.0 27.3 57.1 65.9 Ql 2N3762A 5.2 8.3 Q2 2N2369A 2.1 3.7 Q3 2N3762A o.o o.o Q4 2N3762A 10.0 18.4 R38 121 ohms 43.7 68.3 R39 715 ohms 3.2 7.4 R40 909 ohms 4.6 5.3 18.9 25.0 R41 4.87 kohms 0.1 0.2 R42 33 ohms o.o o.o R43 187 ohms o.o o.o R44 383 ohms 10.8 12.6 4LJ.8 59.4 R45 4.87 kohms 0.1 0.2 RlJ6 5.6 ohms o.o o.o Total 35.4 45.2 185.2 256.8

()) 0 81'

3.5.7 OUTPUT SHORT CIRCUIT CONSIDERATIONS Current through the B - E junction of Q3 is limited by R42 a 33 ohms resistor to well within its maximum ra- ting. Current through the E - C junction of Q3 is limited by R46 and R43 a total resistance of 185.6 ohms to a cur- rent well within its rating. Current through the E - C junction of Q1 is limited by R43 a 180 ohms resistor to a current well within its rating.

3.5.8 COMPUTATION OF THRESHOLD VOLTAGE

Cutoff occurs when rB 2 = 0 or v 0 ~ VBE 2. Consequent­ ly the switch circuit can be reduced to the following cir- cuit:

- Where v21 = v2 20 rna x Rz

R38 121

I = VTH - Vz + 20 rna x Rz R + RJ8 z 2

(VTH - Vz + 20 rna x R2 ) R38 VBE = R38Iz = Rz + R38 82

V BE(Rz + R38) R38" · + v 2 - 2 0 rna x Rz vTH typ = · 78 i~~.6 0 121 ) + 2.700- 20 rna x 30 = 3.07v 99 30 117 98 VTH max= • ( 117.98+ · 1 + 3.016 - 20 rna x 30 = 3.66v 57 30 124 03 ~,'TH mLn· = • ( 124.03+ • ) + 2.411- 20 rna x 30 = 2.52v

3.5.9 TURN OFF &~ALYSIS

3.5.9.1 Computation of VTH Time (t) ::... Time t is the time at which the switch Ql shuts off due to VCCl dropping below the threshold voltage. The circuit figure 3.4 represents the basic data re­ tention switch. In order to determine turn off time it has been further simplified to that of figure 3.5. The circuit of figure 3.5 can be simplified to the following:

Sl ~ I

\Vhere the currents r2 and IcEl have been neglected because IRIN>) ICEl- r2 as shown in the computation be­ lmv-. Switch Sl closes at time t = 0 and opens at time t 83

Icse Ql Vee I Yoo I.itr Rr"" erN Dl va~ R.L..

;ug

- . - - 1- -

BASIC DATA RETENTION SWITCH FIGURE 3.4

----~------~------~~ VrH

Assuming Vsatl and VBEZ are negligible also RL >> RIN

SIMPLIFIED DATA RETENTION SWITCH FIGURE 3.5 84 when V = VTH

5 0 = • ia~ = 10.53 rna where VCCl is the initial charge on CL.

r 2 = 20.0 rna as shown earlier. Consequently both currents are negligible when compared to IIN which is 571.5 rna typical. As a result the following equation is written by in­ spection of the above simplified circuit. -t VTH or t = - R C ln ---­ IN IN VCCl t min = 5.41x7·1.4x10-6 ln l:~~ = 100.7 us

6 t typ = 8. 75x89.3x1o- ln §:§6 = 381.1 us

6 t max= 16.62x107.2xlo- ln §:~~ = 1.351 ms

3.5.9.2 Computation of Voltage Hold Time For the below computation refer to the simplified circuit of figure 3.5 and figure 3.6.

where VCL = initial voltage.

VTH = VCC 3(1 + R43CLS) - VCLR43CL also 85 f.'

0 y

Switches Sl and S2 close at T~O and open when V=VTH

CIRCUIT FOR COMPUTING VCC 3 DECAY TIME FIGURE 3.6

c':-1Sl R. 't.3

C.~_ l VDD . fl... J...

- -

CIRCUIT FOR CONFUTING VDD DECAY TIME FIGURE 3.7 86

Where VCIN = VCL = VCCl = initial condition, solving for

VCC 3 we obtain: CIN + CL 1 ( ~ ~ + ) . R4 3CL CIN CINRIN VCC3 = ----~C~-~+~C~--~~-==------S 2 + ( IN L + 1 ) S + 1 R43CLCIN CINRIN R43c1 ciNRIN

AVCCl + SVCCl let VCC 3 = s2 +AS+.~

A A2 1 also a = - I + SQR (~ - B)

A A2 1 and b = - 1 - SQR (~ - B) then

v = eel ((A+ a)eat _ (A+ b)ebt) a - b

Parameter Settings for VCC 3 at Cutoff Time 87

Parameter VCC 3 min VCC3 typ VCC3 max

RIN 16.62 ohms 8.75 ohms 5.41 ohms CIN 107.2 uf 89,3 uf 71.4 uf R43 182.33 ohms 187.00 ohms 191.68 ohms CL 54.0 uf 66.2 uf 79.4 uf VCCl 4.75 v 5.00 v 5.25 v VTH 2.52 v 3.07 v 3.66 v 3 3 A 714.00 1.420x10 2. 728xl0 6 B 17. 54xlo-6 9.673xlo-6 5.879xl0- a -91.60 -77.00 -64.00 . 3 3 b -622.4 -1. 343xl0 -2. 664xl0 t 1. 351 ms 381.1 us 100.7 us VCC3 4.568 v 4. 968 v 5.246 v

3.5.9.3 Computation of VDD Decay Time from VTH to Minimum CMOS RAM Holding Voltage From this voltage the circuit is discharging through

~only. See figure 3.7 for details.

-t RCL VDD(final) = VDD(initial) e

VCC 3(initial) where R = R43 + RL = Icc (Stb.) 3 VDD(final) t = - RCL ln VDD(initial)

RLVCC 3(initial) VDD( initial) = R43 + RL 88"

The Following Parameter Settings were Used for t

Parameter ttyp

VCC3f 2.095 v 2.000 v 2.000 v VCC3i 4.568 v 4.968 v 5.246 v RL 10.54 Kohms 5.000 Mohms 39.58 Mohms CL 53.0 uf 66.2 uf 79.4 uf R43 182.33 ohms 187.00 ohms 191.68 ohms VDDf 2.000 v 2.000 v 2.000 v VDDi 4.477 v 4.968 v 5.246 v t 457.9 ms 301.2 sec 3030 sec

3.5.10 TURl\T ON ANALYSIS The circuit figure 3.8 is a simplified circuit used to calculate "eel' VCC 3' Vcc 2 and VDD time responses. Switch Sl turns on when Vcc 1 = VBEJ Switch S2 turns on when Vccl = VTH The circuit of figure 3.8 is a simplified figure A19 in Appendix A.

3.5.10.1 VCCl Response with Sl and S2 Open

where vcc 1 = vBE3 89'

0

~-o ~-----?--~ Voo .$/

CIRCUIT FOR COMPUTING VCC 3' VCC4 AND v00 TIME RESPONSE FIGURE 3.8

Ir.N R43 II R4z V(~"2 ~ vw ()/ > Ycc.3 j_ CrN IK!ri c.J.. I V· - I -

l - r

SIMPLIFIED VCC 3 TIME RESPONSE CIRCUIT FIGURE 3.9 90

t 1 = time at which Sl closes and VBE 3 starts conducting. The Following Parameter Settings were Used to Compute

tl

Parameter tl min tl typ t 1 max

1IN 3.0 amps 2. 5 amps 2.0 amps RIN 16.62 ohms 8.75 ohms 5.41 ohms CIN 71.4 uf 89.3 uf 107.2 uf '~1 BE3 0.49 v 0.76 v 1.04 v tl 11.84 us 27.63 us 58.61 us VCC1 --- 41.39 v/ms 27.51 v/ms 17.74 v/ms t1

3.5.10.2 VCC 1 Response from S1 Closure to S2 Closure The affect of ~4 is considered to be negligible. The circuit of figure 3.8 can be simplified to that of figure 3.9. From figure 3.9

\T"CCl 1 91' I '

Bl ' - Bo + s + vis 'eel - (S + a)(S + b) -at -bt2 2 Bl Bl Bl av. -) - ~-CBo bV.) vcclCt) = ~ - a

IIN Vi(CIN + CL) IIN where R -- + and Bl ~a - CIN RCINCL = RCINCL

Parameter t . t m~n typ tmax

IIN 3.0 amps 2. 5 amps 2.0 amps RIN 16.62 ohms 8.75 ohms 5.41 ohms CIN 71.4 uf 89.3 uf 107.2 uf CL 53.0 uf 66.2 uf 79.4 uf R42 34.65 ohms 33.00 ohms 31.35 ohms R43 191.68 ohms 187.00 ohms 182.33 ohms VTH 2.52 v 3.07 v 3.66 v R 29.35 ohms 28.05 ohms 26.75 ohms vi 0.49 v 0.76 v 1.04 v 3 3 3 Bo 42.566x10 28.707x10 19.509x10 6 6 6 B1 27 .011x10 15. 076x10 8. 784x10 a 332.25 373.81 374. 17 b 1.6305xl03 1.8437x103 2 .1697x103 VCCl 4. 75 v 5.00 v 5.25 v t2 @ VCC1 = VTH 50.4 us 92.3 us 187.3 us t3 @ VCC1 = VTH t4 @ VCC1 = VCC1 109.9 us 181.9 us 350.0 us ------

92

Parameter tmin t typ tmax

VCCl VTH -=- 50.0 v/rns 33.3 v/ms 19.5 v/ms t2 t2 VCCl VTH-VBE --= 50.0 v/ms 33.3 v/rns 19.5 v/ms t3 t3

"eel--= "eel- "BE 43.2 v/ms 27.5 v/ms 15.0 v/ms t4 t4

3.5.10.3 "ceJ Response from Sl Closure until VCel Reaches Final Vcel

Using the circuit and equation from the previous sec- tion and solving for "ccJ' the following is obtained:

therefore vcct and

"cc3 = A1 A2 s s let "cc3 = (s + a)(s + b) then

A2 -A1 -at4 A1 -A2 -bt4 A1 -A2 "cc3(t) == a(b - a) e + b(b - a) e + ab

1 where A - 1 - RCL CIN

b =

The Following Parameter Settings were used

Parameter VCCJ min VCC3 typ VCC 3 max

1IN 3. 0 amps 2. 5 amps 2.0 amps RIN 16.62 ohms 8.75 ohms 5.41 ohms CIN 71.4 uf 89.3 uf 107.2 uf CL 79.4 uf 66.2 uf 53.0 uf R42 34.65 ohms 33.00 ohms 31.35 ohms R43 191.68 ohms 187.00 ohms 182.33 ohms R 29.35 ohms 28.05 ohms 26.75 ohms v. 1.04 v 0.76 v 0.49 v 1. 6 6 6 Al 6.0100xl0 6.0306xl0 6.5797x10 3 3 Az 361.61xl0 689.2lx10 1. 2162xl03 a 239.57 373.81 544.43 b 1.5094xl03 1.8437xl03 2.2339xl03 "eel 4.75 v 5.00 v 5.25 v t4 109.9 us 181.9 us 350.0 us "cc3 32.0 mv 77.4 mv 295.3 mv 94

Parameter VCCJ min VCC3 typ

0.291 v/ms 0.426 v/rns 0.844 v/ms

3.5.10.4 vcc 3 Response from Time VCCl = Vccl(final) -'~-- Until Switch Sl Shuts Off The equivalent circuit is reduced to the following:

VBE R43

R42

VCC3 CL

I- v. - ~ l--

SR42CL(S + R42IC__ + n45c ) - L 1\: L

s + 1 1 R4 2CL + R43CL 95

Switch Sl shuts off when VCC 3 = VCC 1 - VBE' therefore R42R43CL VBER42 t5 = - R42 + R41 ln((R42 + R43)(VCC 1 +Vi) + VBER43) The Following Parameter Settings were Used

Parameter ttyp

VCCl 4. 75 v 5.00 v 5.25 v CL 53.0 uf 66.2 uf 79.4 uf VBE 0.49 v o. 76 v 1.04 v 295.3 mv 77.4 mv 32.0 mv v.]_ R42 31.35 ohms 33.00 ohms 34.65 ohms R43 182.33 ohms 187.00 ohms 191.68 ohms t5 6.1399 ms 7.2719 ms 8.5185 ms VCC3 0.646 v/ms 0.572 v/ms 0.490 v/ms t5

3.5.10.5 Vcc 3 Response to 1% of Final Value from the Time Sl Shuts Off This simply involves an RC time constant computed as follows:

v. "eel + ]_ s + I R43CL 96

Now VCC 3 = 0,99 of VCCl' consequently

0 •99VCC1- VCCl -.OlVCCl t = -R43CL ln( V V ) = -R43CL ln( ) 6 i - cc 1 vi - vcc 1

The Following Parameter Setting~were Used

Parameter t mLn . ttyp tmax

VCCl 4.75 v 5.00 v 5.25 v v i 4.26 v 4.24 v 4.21 v R43 182.33 ohms 18 7. 00 ohms 191.68 ohms CL 53.0 uf 66.2 uf 79.4 uf t6 22.551 ms 33.688 ms 45.488 ms VCC3 0.020 v/ms 0.021 v/ms 0.022 v/ms t6

Total time for VCC 3 to reach VCCl within 1~{ of final value = tT = t 1 + t 4 + t 5 + t 6 CHAPTER 4

MEMORY ANALYSIS SUMMARY

4.1 TIMING ANALYSIS SUMMARY The results of the timing analysis are summarized in table 4.1.

4.2 INPUT/OUTPUT LOADING SL~ARY Based on the analysis in section 3.3 and table Bl in Appendix B, no logic input or output loading problems exist. The drive capability of all outputs exceeds the load requirements.

4.3 POWER ANALYSIS SUMMARY The results of the power analysis are summarized in table 4.2. In the power analysis it was assumed that the regulator operates at rated output current from 0.0 v and up to 5.0 v. In actuality this is not the case, because the regulator input voltage also has some rise time. This rise time was not considered in this analytical computa­ tion.

4.4 DATA RETENTION SWITCH ANALYSIS Su~RY The results of the data retention switch analysis are tabulated in table 4.3

97 TIMING ANALYSIS SUMMARY TABLE 4.1 Signal Designation Requirements Computed Results Time for stable addresses 200 ns before CI 6.7 ns before CI Stable addresses at input Be stable before SMEl.,.~, Stable 14.9 ns after CI ...... ,_ "'< to CMOS RAM DMEl ', DM£2'', or DHE3' or 106.1 ns max. after CI SMEl "' Start As early as possible after 170.7 ns max. after CI CI but<. 200 ns

SMEl""'· End Minimum pulse width of I 933.7-170,7 = 763.0 ns 300 ns DMEX * Start As early as possible after 106.1 ns max. after CI CI but:$ 200 ns I DMEX--!~ End Minimum pulse width of 897.8-106.1 = 791.7 ns 300 ns - - WEI * Start At the same time or after 170.7 ns max. after CI SMEl'-J,• or 170.7 ns max after CI

·------·--·---- -~------·-·---··--~----- WEl'i'< End Minimum pulse width of 933.2-170.7 = 762.5 ns 300 ns '- ----

"'OJ. TIMING ANALYSIS SUMMARY TABLE 4.1 CONI. Signal Designation Requirements Computed Results .,_ WE2" Start At the same time or after 195.6 ns after CI DMEl*, DME2*, DME3* or 106.1 ns max. after CI .,_ \vE2" End Minimum pulse width of 962.4-195.6 = 766.8 ns 300 ns CMOS RAM Data output time Less than the leading edge 494.8 ns max "/,• of DREADY' or 736.0 ns CMOS RAM End of data More than the trailing 990.0 ns max. ,~:; I edge of DREADY or 887.9 ns CNOS RAM Data output Less than the leading edge 623.4 ns max ""· buffer enable I of DREADYn or 498.4 ns CMOS RAH Data output 1 More than the trailing 1012.2 ns min. t.j, buffer disable edge of DREADY or 990.0 ns DREADY"""· Start 800 ns max. 736.0 ns max. .,_ DREADY" End 1200 ns max. 88 7. 9 ns max.

\0 \0' TIMING ANALYSIS SUMMARY TABLE 4.1 CONT. Signal Desighation Requirements Computed Results

..... -.1.- Data input buffer enable At or before WEI", WE2" 134.6 ns max. or 170.7 ns max. Data input buffer After... the end of WE1 * , 963.5 ns min. disable WE2#' or 962.4 ns min. UVE PROM Chip enable As early as possible after 53.9 ns max. start CI to meet data output time - UVE PROM Chip enable end After the trailing edge of 968.5 ns min. .J.. DREADYn or 960.9 ns min. UVE PROM output enable As early as possible after -41.2 ns max. start CI to meet data output time UVE PROM output enable end After .,,the trailing edge of Cycle time-175.5 ns min. DREADY or 990.9 ns max. UVE PROM Access time 900 ns max. 531.6 ns max. lNE PROM Data output end 1200 ns max. 1213 ns max. time

...... 0 o. TIMING ANALYSIS SUMMARY TABLE 4. 1 CONT.

I Signal Designation Requirements Computed Results ' Before leading edge of 698.9 ns max lNE PROM output buffer .... enable DREADY" 900 ns max. After trailing edge of 970.5 ns min. UVE PROM output buffer .... disable DREADY" or 961.9 ns min. DREADY * Start, UVE PROM 900 ns max. 837.2 ns max. DREADY* End, UVE PROM 1200 ns max. 961.9 ns max. MBusy* Start 100 ns max. 72.3 ns max. MBUSY* End 1100 ns max. 1086.9 ns max. CI with respect to clock No requirement 13.3 ns min. 66.1 ns max. I cr End Pulse width of 100 ns Pulse width of 67.7 ns min. min. I

...... 0 ...... 102

POWER ANALYSIS Su~ARY TABLE 4.2

Condition Requirement Computed Results Standby Current 1.7 amps max. . 97 amps max. Standby Power 7.5 watts max. 5.1 watts max. Cycling Current 1.7 amps max. 1.2 amps max. Cycling Power 7.5 watts max. 6.0 watts max. Programming Current N.R. 1.9 amps max. Programming Power N.R. 12.8 watts max. DATA RETENTION SWITCH ANALYSIS TABLE 4.3 Parameter Computed Results Requirements Min Typ Max 11.84 us 27.63 us 58.61 us None T1 (time at which VDD turns on) T2 (time at which VCC 2 turns 62.20 us 119.9 us 245.9 us None on) T2 = t 1 + t 2 r 3 (time at which Ql turns on) None T3 == t1 + t3 62.20 us 119.9 us 245.9 us I

T4 (time at which Vccl reaches 121.7 us 209.5 us 408,6 us None final value) T4. = t 1 + t4 r (time at which Q3 turns off) l 5 ' Ts = tl + t4 + ts 6.261 ms 7,481 ms 8.927 ms None I I r 6 (time at which VCCJ reaches 1% of final value) T6 = tl + t4 + ts + t6 28.812 ms 41.169 ms 54.415 ms 50 ms i .. vccl -r-- (slope of Vcc 1 from t 0 to 1 tl) 17.74v/ms 27.5lv/ms 41. 39v/ms None

1-' 0 w. DATA RETENTION SWITCH ANALYSIS TABLE 4.3 CONT. Parameter Computed Results Requirements Min Typ Max

j VCCl I -T~ (slope of VCCl from t 1 to 2 t2) 19.Sv/ms 33.3v/ms SO.Ov/ms , None VCCl -f-- (slope of VCCl from t to 3 1 t3) 19.Sv/ms 33.3v/ms SO.Ov/ms None vccl -r-- (slope of VCCl from t 1 to 4 t4) lS.Ov/ms 27.Sv/ms 43.2v/ms None VCC3 ~ (slope of Vcc 3 from t 3 to t4) .29lv/ms .426v/ms .844v/ms None VCC3 -rs- (slope of Vcc 3 from t 4 to ts) .490v/ms .572v/ms .646v/ms None

1-0 0 .P.. DATA RETENTION SWITCH ANALYSIS TABLE 4.3 CONT. Parameter Computed Results Requirements -· Min Typ Max - vcc3 -f6- (slope of "ccJ from t 5 to 1% of final value) .020v/ms .02lv/ms .022v/rns None ' "TH (Threshold Voltage) 2.52v 3.07v 3.66v None Data Retention Time 301.2 ms 457.9 ms 3030 sec 300 ms min I

...... 0 ll1 CHAPTER 5

CONCLUSION

The objective of this paper is to demonstrate the se­ quence of steps leading to a successful memory design. The approach presented is not limited to military or aerospace requirements. The approach is equally applica­ ble to commercial memories or other designs, with the ex­ ception of component derating, temperature extremes and other aerospace reliability requirements. This paper is an attempt to avoid the pitfalls based on the following criteria: a) Establish a design based on previous experience or seat-of-the-pants type of approach. b) Establish a design based on minimum cost. c) Design without a rigorous worst case analysis, but based on some vague assumptions or approximations. d) Design based on optimized customer requirements or some ideal conditions. In this design, memory selection is based on customer and other pertinent weighted requirements. Weghting fac­ tors are based on usefullness, future potential and similar factors. As a result the memory selection is based on a scientific approach, evaluating all possible alternatives. The weighting factors are strictly hypothetical, but are somewhat based on marketing research and customer require-

106 107 ments on several memory designs (1). The figures of merit stem from typical data sheets of various manufacturers. The design analysis is based on component derating to military standards (2) and applicable manufacturer's data sheets. The purpose of such a rigorous analysis is to prove that all phases of the design are meeting the requirements and that no overstressed components exist. The design analysis is complete, with the exception of stray capacitors, inductors and resistors; the effects of these were considered negligible and byond the scope of a typical analysis. Thermal analysis was not included, simply because it is not within the scope of electrical design. It is normally performed by machanical engineering in aerospace designs, The analysis in this paper is complete enough to gua­ rantee performance of the memory as a black box. Problems associated with interface connections, noise coupling in interface cables, reflections due to improper cable termi­ nations are considered to be beyond the scope of this ana­ lysis. However, in any real system the above problems must be included in the analysis. BIBLIOGRAPHY AND REFERENCES

(1) Memory performance specifications and requirements, Teledyne Inc. (2) Military standards for Cetaur memory design, Teledyne Inc. and NASA standards. (3) Data sheets of the following manufacturer's: LSTTL circuits - Fairchild Inc. HM6514 memory element - Harris Semiconductor Products Division. 2716 memory element - Intel Corp. (4) "Management Analysis/Concept and Cases", by Haynes and Massie, Prentice- Hall, Inc., 1961. (5) "An Introduction to Management Science, Deterministic Nodels", by Daniel Teichroew, John Wiley & Sons Inc. 1964.

( 6) "Statistical Analysis", by Samuel B. ~~.Richmond, The Ronald Press Company, 1964. (7) "Memory Technologiesn, by Morton Jack, Magnetics Transcript, Sep. 1971. (8) "Magnetic Core Access Switches", by R. C. Minnick and J, L. Haynes, Trans. IRE PGEC, Vol. EC-11, June 1962 p. 352. (9) "Ferrite Memory Systems and Devices", Staff, Electro Technology, Febr. 1963 p. 80. (10) "Advances In Memory Technology", by H. Frederic Koehler, Computer Design, June 1974 p. 71.

108 109

(11) "New Magnetic Materials Help Core Memories Stay Alive", by Rodger D. Thuras, Computer Design, July 1976, p. 100. ( 12) "Memories: Magnetic Hainframes", by Steve Thompson, The Electronic Engineer, Apr. 1971 p. 45. (13) "Centaur Core Memory Analysis", by Leo Zaretsky, Teledyne Inc. (14) "Magnetic Rubble Memories and System Interface Cir­ cuits from Texas Instruments", Texas Instruments Inc. Feb. 1977. ( 15) "Bubbles Rise from the Lab", by Edward A. Torrero, IEEE Spectrum, Sep. 1976 p. 29. (16) "Magnetic Bubble Memory Devices and Applications", by Eric Garen, IEEE Spectrum, Feb, 1978 p. 164. (17) "Memory System Design Seminar", Intel Corp. 1977. (18) "Application of Intel's Sv EPROM and P.OM Family for Microprocessor Systems", Intel Corp. 1978, AP - 30. (19) "Signetics Product Reliability Report R 363", Signetics Corp., June 1975. (20) "Harris Bipolar & CNOS Memory Data Book, Harris Reliability & Quality", Harris Semiconductor Products Division 1978 Volume 1. APPENDIX A

CIRCUIT SCHB-fA TICS

Appendix A contains the following circuit schematics: CMOS RAM Schematic - figure Al CMOS RAM Data Input/Output Buffer Schematic - figure A2 CMOS RAtv! Data Input/Output Buffer Schematic - figure A3 CMOS RAM Data Input/Output Buffer Schematic - figure A4 CMOS RAM Data Input/Output Buffer Schematic - figure A5 CMOS RAM Schematic - figure A6 CMOS RAH Schematic - figure A7 CMOS RAM Schematic - figure A8 CMOS RAM Schematic - figure A9 CMOS RAM Schematic - figure AlO PROM Memory Schematic - figure All PROM Memory Schematic - figure Al2 PROM Memory Schematic - figure Al3 LVE PROM Output Buffer Schematic - figure A14

LVE PROM Decoder Schematic - figure A15 Semiconductor Memory Timing Schematic - figure Al6 Semiconductor Memory Address Latches Schematic - figure A17 Semiconductor Memory Address Decoder Schematic • figure A18 Semiconductor Memory Data Retention Switch Schematic - figure A19

110 111

~7 1?8 ~~~--~--~~~-o_o~~~-o_ok~l_.o_o_X+J_.o_ak~l~.o_o_k+-l.o_o_~~--,_~ABOO~ ,... ~~----~---+--~--~--~--,_--+---+---~ A801

~~------~--~--~--~--~--~--~--~--- A&02 *

~------._--~-4---+--~--~~AB04*

~~~------~--4---+---+---~ASO~*

.II' ~------+---+---4---4-._ABOb

~~------~--~~A808*

~.:...J------..... /1809 * Ground connections Al,A2-8 +Sv connections Al,A2-16

CMOS RAM SCHEMATIC

FIGURE Al 112

Vcc2

Rllt R.IS" 1\17 "1000 DOOO PMEI '* MOOt .... DM e 2. ":>---...J MD02 DM B~ =>-----....1 MD03 W!2. • coe*

DI06

Yoo

0!02

0!0.3 'w'.E I*,. SMI! err.*

Mt:>Olr

Ground - A2,A3,A4-8 +Sv - A2,A3,A4-16 /)104

DIOS'

CMOS RAM DATA INPUT/OUTPUT BUFFER SCHEMATIC

FIGURE A2 113

· Vccz.

R2.4 R2.5 f?2.6 A2.7 RZg R2.'1 MP06*~------~s,~q~oK~5.~9o~k~S.~·~qo~K+~~.9~o~K~5.~.1~0~X~S.~.g~o~~~

MDo7*>------~r--+--~--+-~~-+~

~ MD08 ~------+--4--~--+-~~-+~

Mooq* ~------r--+-~~~--~--~~

DI07

DI O'i ,.. C!f MD I 0-lt- ;>------+------+-----+--+-=~

MD J l '* ::>------+------!---!~-+~

Ground - A4,A5,A6-8 +5v - A4,A5,A6-16 OIIO

/)I I I

CMOS RAM DATA INPUT/OUTPUT BUFFER SCHEMATIC

FIGURE A3 114

Vcc2.

M!> J 2.*' D0/2.

lit MD13 D0/.3

MD141t DOf4

MD IS* {)015"

COE.¥t-

/)I/2..

0113

DI/4

DII5"

~IE IE

MDIG+ DOI6

MD 17* >-----+------t--1----.~.:...... J DO 1 7

Ground - A4,AS,A6-8 +5v - A4,A5,A6-16 Dllb

CMOS RAM DATA INPUT/OUTPUT BUFFER SCHEMATIC

FIGURE A4 115

MDI8

MD 19 >------1----.11__...!..4

;f. C OE >------_.;_---1--~--Cl

(:.L£.-· ->>------~-----l ~ Ground - A8,A9-8 + Sv - A8 , A9 - 16

CMOS RAM DATA INPUT/OUTPUT BUFFER SCHEMATIC

FIGURE AS Vpp Ycc1 Y(.cJ Veer J.. ;It 5 Vee. .4BOO /JO ABOO * R8DO• 1/BOO.lf< b .4801.. A, ftBOI* hBOf~jt .-9BOitt 7 .Ill 17 1:>02.* J:lil. f)BD2.• fl/302. *- 4 1/802. ~~~~ ,t:J8o3'*' A;!. 11803* /}803~ ~B03-ff. /13 3 .;. 17 f>Sitr 11&Dl:> tt- I A, "t 80 6 .. h!!-06 ilt: /180f>lt- 7 ,q Ml 11B07"tt 7 11BD7""' f)£>07 • IJB07 • AB>OB~ J:/g /1BD8f: A8D8~ ~8os• AF:Joq • I~ 1}'1 ABoq* ABO't • A BD't lf. _ 1!!:...:;.. M D 00 J>GlO MDOO oao ~0 MPOO . D~O~MDOO PQI 1"100 I PGU MJ)OI PGI MDOI p~ I J.3 Mt>OI PG2 MDoz. D~l M Do2. DQ2. M l>02. DQ2. Mt>oz. 10 ;t tO WEI * 'W Dti3 MP03 DQ.3 MDO?. w~ Pa~ MDo.3 w• .l>Q3 1 I 1'4 D03 8 8 .SMt: I• E * E.. • ~:• C.ND 6NI> q -- -- ' - ;f- - DMEI WE2. •,._ DME2 DMe:/'

CMOS RAM SCHEMATIC FIGURE A6

1-' 1-' 0\ Ypp Yc.c.t Yc..ct Vc.ct i 5 Vee.. 5" vee. .,. .4800* ,qo. ABOO * RBDO* llo ~Boo 6 .4801"' A, ftBO 1* .480 ,. A, .IJBOiot 7 ,jft 17B02* ~:l. I)B02.1l /J/3D2lt 4;z. 4 11802.. ~~~ .. ..q8o3"* f)~ lleo3* IJB03tt }:J~ IU303 . .93 3 ,. -1 Bo4". 11~,- I} BOlt ~8D4 *" 11+ A.BQ../t • .3 ll.~t 2 .... . ~ 11805+: Its- 11BoS* ~B05 .1J 8OS' !1&0(:; tj A, . ):j806.. lt!>06 ill; ~806*" 7' 1}7 M5' ~ /IB07>tt ~Bo7 Ab07 • IIB07 • Ae.oa* Aa /JB08 it A BD8tlt 1')808 * At!Joq* IS" J}"' A Boq * ABoCJ * li 801 ~ - j)QO MD04 j)Qo ~MD04 J>Qo MP04 . MD04 /.3. DO.o~13 PQI I"ID05 Pat MP05" PGI MD05' Pal MI>05' 12 PQ2. MDoE:a P~2. MD06 DQ2. Ml>06 PQ2. 2.. Mf>06 10 .... lo WElt JO w'* DG.3 ML>o7 w DQ3 I ML>07 10 w+ PC.3 Mbo7 w• PQ~ . 1 1 /'t1 D01 ~ 8 8 8 8 SMf:l E * E*' E• . f: .. GND G Nl) 6ND q 't 'I - - - ;If - - - - DMEI > -·------W'E 2 '*,._ PMe2 DMe3*

C~10S RAM SCHEMATIC FIGURE A7

...... Vpp Yc.c.l Yc..cl Vcct j_ -:It 5 Vee.. lit .A BOO ,qo ABOO * R8DO 1/Boo"' ~ 6 .4801 A, JtBO/If .480 ,. .-9Bo Itt 7 .Ill 17/:J02.* l:l;t })802,. 111!>02."' ,9802 4 lleo!'/lt IJB03'4: ~Bo3"* f)~ -fE ' IU>03 ·~:~lq3 1Jt>o4". 3 IJBO't. J98D4 *" AE>Olt ,._ o3 li4 44- 2 ... . A8t>S"" RBOS* ,qs- 11805* ~BOS 11/!.Df:, ~ I Ab ~eo~/~ ltB>06 it- ,98o6'*" ~ 'lit IJBo7"" 7 IJ7 M'l 11Bo7 lt/:>07'* AB07 A~os" ,q/5 /IB08f- ABD8~ ~808. A8D'I * IS"' .t}9 ABOO~ PQ3. . N D I I 8 E.._ 8 f;.. .SMf: I '* B .f *' E• • GND GNO 6Nl> GND 'j ') 't ,.. -- -- "- - DMEI INEZ •,._ PMf2 DMc3*>

CM.OS RA1'·1 SCHENATIC FIGURE A8

t-' t-' <» VDD Yc.c.J Vc.c1 Vc.ct !JL~ 5 Vee.. It BOO* ,qo ABOO * IJBDO• /1800.. to It BOt * .~~. ft80Jtt ABot* ,qso I~ 7 .Ill ,q~o2.* R.il. fJB02.,. /11!>02. * 4 lit ,t:18D3.;t .1).3 11803 IJB03.., IU!>03IJ8£)2... ar"-'~.!. fJB04 ~. 3 44- IJ.BOit* ;:JB04 *' A&O..It i ..3 /14 2. ... 11805* ,qs- I'JB05* ~80S 19 8 {)Site f)i>Ob tt I A, -"'tlb06.. /tbD6 ill.: /180,+ ~ /IB07;;t 1 .tJ? Ml~ f)BD7 /11:>07 • /1807 * 11.808* )/g fiBD8 f: ABD8'tli:... ~e.os* 1160'1 • IS' ,{}9 A 80'1 * ABO't ABo~/' _ .PGO MD12. oao ~ MD/2. />GlO 1'1()12. • D/l,o MP12. ~13 PQI I"ID 13 PQI MP13 PQI MD1.3 PQ I f\11>13 Pll2 MD14 D~2. MDI+ DG2. M 1>14 PQ2. MP14 10 10 ... 10 Jo 1 1 WEI w* DG3 MPIS w Pa3 MD IS" w+ l)ij3 MDI~ ~,l .l>Qo N DIS" * 8 8 8 8 SMf:l I:* E11r E• . ~:• - G.ND GND GNP GND q ') 'I '1 - - - :if- - - - DMEI W'E2~_. PME2 DMt:3*>-

CMOS RAM SCHEMATIC FIGURE A9

,_. ,_. \0. CMOS RAH SCHEMATIC FIGURE AlO

...... N (!l Vpp1 Vcq VPPl V(CI Ypp3 Ycc1 Vpp.Jt \lc.c.t

8 . . .;;-r IIBOO > Ao \'c, A Boo Jl/300 ABOO 7 ~BOI ~ A, -'lBO I IJBOI .-980' b 1/1302 ; 4z. 1Jt302 A802. IU302 5 ABO~ ;; -9a A80.3 A803 ~80.3 4 ~BO.lt-). I}" JlBD4 AB04 ~804 3 IJ60S ) ~~ .t~Bo5 AB05 111305' 2 IJB06 .,. li{. A BOb 11 B(Jl, /JB06 .-9807 > I R1 !IB07 . .-9 807 Ji/307 23 IJ80B > lia /J/3.013 IU3D8 FJB08 22 ABOCf ) A 'I A BO't IH3D'I .-980'1 ICJ .L:J M21 11~10 > /o )1810 .11810 Af,/ 0 0 !2* > 3J: OE2.* MPOD · MPoo Oo · MPDO o.. MPOO CE2~ ~ CE2• MPOI MPOI o, · MPOi o, MPOI OE.3* > > Of3* MP02 Mfoz.. MP02 0;~. MP02. CE3; ~ CE3: MPo3 1\f Po.3 JV1Po3 03 fYIPo3 OP.'t ~ OE4 MP04 MPo4 MPo4 e~,. MP04 C e..4 it >----? C. E4 1ft l"JPos- MPOS MPOS M.POS" 20 Jo OE.t*' MPo6 MP06 MPo6 17 )!. CEI* ';. /8 MPo7 MPo1 oaz..."* cs2..* -- -- ..- - -- . ~ --

PROM MEMORY SCHEMATIC FIGURE All

1-' N 1-' VPPJ Vcq Vpp2_ Vcc1 Ypp3 Vcct Vpp4 VC.CI J t 4 if' t Vpp ..... 8 2.4 T IIBO 0 / Ao ~C. A Boo Jl/300 11800 7 HBO I ) A, .i]BO I IJL>OI ~SOl G fJBD2 :;- J:lz. }1802 A/302 fli>02 5 A&D2. ' -93 R803 .4803 ~1!>03 ~804 .. 4 -9-\ .4804 AB04 ~8()4 .3 A605 .. lk -4805 AB05 }J/305 2 !~BOb:;- 11" /1806 IJBOh ,1} 80{:. /-J807 > t R1 IJB07 .ltB07 ,iJ807 2.3 IJ806 :;- Aa fJ&0/3 f1.BD8 /j808 22 IIBOCf ) A'I f)Ef;OCJ fJBot:J ,r:J80't 118 I 0 ;;- I CJ ,.q ,:; 2S ~810 ~j810 11bl0 01:2.* ~ OEZ."* MPOS MPOS 0.:. · MPos Oo MPOB CE2>1t ~ CE2.~ M PO'i MPb'f o, · MPD'/ o, MPolJ OE.3*> >DE3* MPIO MPJo MPio oiL MP1o CE3: ~ Cf3: MP11 1'1 PJ I JVI PI/ 03 JVIPII 0./=lt ~ OE4 M P12. MP12 MP12. th. MPil ce.4* ~ GE4* tv}P13 MPI~ MP13. Os MP13 .20 01:1 * .... . 20 MP14 MP14 MPJ4 OE.. o, MP/4 18 17 )!. CEI* ., MPIS' MPt> MPIS' E 01 .... " MPJ> 0£;2.. oe3* O!;+~ CE2...;,. c. £:~.,. -- -- - C E.f-fl .,. --

PROM l'JEMORY SCHEMATIC FIGURE Al2

...... N N Vpp, Vee, Vppa_ Vcc1 Vpp3 Yc.ct Vpp4 Vc::.c1 t t t 2.1 + Vpp .,.,. 2.Jt 24 ffBOO __...... a Ro ~(. A Boo 111300 R0 Yc.c ABOO 7 .1/BOI ' A, .J}BOI IJ/}OJ !i80I G llBD2 :; liz. /18()2 A/302 li/302 5 A803 ) JJa R80.3 .4803 .IJB0-3 4 f}BOJt. ..- ~~. }1804 .4804 JIB04 3 i360S .- Rr ~805 ~Bos }1505" 2 /JBOb :;::. II' .4806 IJBO& ,qe.ot. -9i!J07 .... t 117 ABO? . ,t} 807 IIB07 23 IJ/308 ... Rs fJ&08 11/308 /J/008 22 fJB0'1 ) A'I 11 8>09 f)BOi fJBO'i MZ.'i 11.810 ; JCJ ,q/0 .J}810 /1810 Flf,/0 0!2* ~ OE2.* MPI'- M P u~ 0"' · MPit:. Oo MPI~ C I: 2M- ~ C. Ei'l' M Pl1 MP17 o, · l'f P17 o, MP17 OE.3 * > :> 0 f3* MPIB MfH$ MP18 . 0~ MP18 CE3: :.:> ? C E3: MPir, I~ Pl't fYlPI? 0,3. fVIPICJ OP.It ~ OE4 M PNC- MPNC. MPNc. CJ,. MPNt:- C EU,. * >-----?- C. E 4 ;A IVJPNt... MPNL MPN'- Os MPNc 20 J.o 01:.1,. / MPNC MPNc.- OE• o, MPJ'.(C /8 }!. ,. CEI* ::. MPNC M PNt.. E 07 MPNC- oaz.* ·oe3* CE.2.."11t c:~:~"' ~ ~ - . ., ------

PROM HEMORY SCHEMATIC FIGURE Al3

...... N ~ -.

124

MPoo 0 Dooo MPIO 0 DOlO

MPO/ J)OOI IV/Pii Po II

Poe

MPCJ2 MPt2. 0 DOIZ.

/VI Po::, POo.3 MP13 o Oo/3

/11PC't 0 Doo4- MP14 Pol f.

MPo~ Doos- Mpl~ 0 /0~"II .. I 0 D0/5'

I c8>-l 12 MPO(a DOO(;. MPib 0 ()0 ,,

Nro7 o /)OO] MPJ7 /)0/7

MPOg 1)008 MP18 · Dot8

MfO'j DOOCJ MP!'f /)Oj'J

Ground - A9,Al0,All,Al2-8 +Sv - A9,A10,All,Al2-16

UVE PROM OUTPUT BUFFER SCHEMATIC FIGURE A14 125

oe=1~

PGM P e>----r-r------=-L_.....

ST~-'*"" ?---~~------~

cez"'

CE3*"

OE4*

Ground - Al4,Al5,Al6,Al7-7 +5v - Al4,Al5,Al6,Al7-14

UVE PROM DECODER SCHEMATIC FIGURE Al5 BMHZCLv---~ 8-, Vee I 8 NOTe~: Ci< ,---CK ..3 14- ~ GROVNJ) -.JJI2,. A/3 -8 Vc.c. 14 v,c. ~ 1 .It 4 ~·Q2. a2 -'7181 /)1~ 5" Q.3 Fl F2. a3 s ~ ):}2.01 -922 f 6 Rll:. b C>O-~DI?ERDY .J:}2.3-7 G4 2.0SI< &J; ID J_, 10 t-S"V- -91}. J9J3-JG as- 11 r-!- ,if I II Q6 ,IJ !11'1 2. 2. J8, 1 8 B 12.. G.T ,?} 2tJ1 /12.2 ~ q j Gb 9 * fi23-1Jt MR~ T M~ QB r §:NP 7 ---1- --1. ----a-."""CLI . I I -= I CL2. RERD

VIR. IT/! ) ~erE.*" CI

MEME \8 421 Jlt :){) >CLL L~~ b II .. ~--; n ~.sn~*

oo >PRO& PfWG *

SEMICONDUCTOR tv1Etv10RY TINING SCHEMATIC FIGURE A16

1-' N 0\ 12.7

Yc."' Vu,

5'" Vc.c,... Va,, 2 .2. j(. /.:;00 0 o, Q,, .!.!;?___,. /7 800 RoB 0 p, a, J7BOi a,- I ...3 F,3. !5 ...3 .1101 D~ G )7(30 I ,.lfO~ f!Bo I o 1/ G.J 7 ,qo,3 Dlt Q.; A 80..1. .-9- I I Qlf ~ -'91311 t3 8 g CL Olt- 12.. 12. - -

v'cc.. 1 '/C.C../ s-f s- '.lee Vc.:. 2.. 2 /~ ;1104- o, Ql ,qBolr 412. o, Q, ,q /.3 I 2. I Q, l 1=-4 l Fob~ 3 ,::,- /}OS" '.3 D,. Ch. )1805' 413 I 01... Qz. ~~S/3 4- CL. 14- : 4-; CL. - I'+ G:z. /VIC az /0 n .A06 03 a~ #BCJ 6 MODt: 0 I 6 ! o ~_;~ R.E~D . I 3 I " 1/ (1(/w) .I I Q3. i I a; W-1', , .. 7 NC 7 Q'f. r"l ,.t:)07 04 Glt /9407 D~t 13 8 13 - g - C.L Qq 0 GN/) . ..J 2. ~- -

SEMICONDUCTOR MEMORY ADDRESS LATCHES SCHEMATIC

FIGURE A17 128

.... 2. r--- . / .. "]2-.t,. WEI v'-'-' ,2.... ""'' ,J ,.£ V'-c. olt- I G II Zit ~ A81o ' ~0 a-: ~--4Yo'0 .ft. 2. .q. lit ·'- A811 I Q, Dl\1~1 ...3 13 11812. ~2. Oz. DJVI~ z'* /Z. Q_;- DM £3 F7 _ > * 6 II ' IE3 Q4 1r - C.z. Q>" /0 5" 9 E, Q~:,- l Q7-17 G"f,:> I

.I ,;i'lz3~! ,010 ~ I II .· q ,q Zit- ;> -

Yc.:.. 1 v~'-' If\ ~~.r v.,_.::.. I ~~- A& II ' '70 q""; I~ .4812 ' z.. 4, ~ ..3 13 A-G 1.3 "12. a; PMI*" ' I 12. IG Q!. PM2. ~ 1=8 S"k .__.§_ - II .... t:3 ~'r p fV13 :.r­ /0 ,-±. cz. Q> p fvtlt- ~ q ~..L E:,- Q(.- f ~ - 7 10 Q7 1'2:. A20 g~ POE. 13 * C,.NI) '------·

- L.- :L - Ground - A23,A24,A25-7 +5v - A23,A24,A25-14

SEMICONDUCTOR MEMORY ADDRESS DECODER SCHEMATIC

FIGURE Al8 129

2.N.3 762.

~ 4-1 it.81 J<..

R~ 1-.~Jk C/ ~V~'--+-----~ .I uri

R-4-.3 1(4-4- !)I 187 383 1!<14~ 7 f /1 l K3'8 C2. Ti3fc~:r c5Ic~J 22 u < 22 I"" /.2.1 i"* "l_, .lUi

SEMICONDUCTOR MEMORY DATA RETENTION SWITCH SCHEMATIC

FIGURE A19 APPENDIX B

SUPPORTING TABLES

Appendix B contains the following tables: Input/Output Loading - table Bl Standby Mode Power Computation - table B2

C"t-lQS RA~f Cycling Power Computation - table B3 UVE PROM Cycling Power Computation - table B4 Programming Mode Power Calculation - table BS Component Power Dissipation - table B6

130 INPUT/OUTPUT LOADING TABLE Bl SOURCE LOAD Item Ref. Des./ Part Nurn. Min @V CC = 4 • Sv Ref. Des./ Part Num. Max @ VCC = 5 • Sv Num. Signal Name Outp. Cap. in rna Signal Name Loading in rna 1oH 1oL 1IH 1IL 1 A1 - 3 54LS368 -1.0 12.0 R1 1.00K (M1-M20)-S HM6514 -2.23 -4.87 2 Al - 5 54LS368 -1.0 12.0 R2 l.OOK (M1-M20)-6 HM6514 -2.23 -4.87 3 Al - 7 54LS368 -1.0 12.0 R3 l.OOK (Ml-t-120)- 7 HM6514 -2.23 -4.87 4 Al - 9 54LS368 -1.0 12.0 R4 1,00K (Ml-M20)-4 Ht-'16514 -2.23 -4.87 5 Al - .. 11 54LS368 -1.0 12.0 RS l.OOK (Ml-M20)-3 HM6514 -2.23 -4.87 6 Al - 13 54LS368 -1.0 12.0 R6 l.OOK (Ml-M20)-2 HH6514 -2.23 -4.87 7 A2 - 3 54LS368 -1.0 12.0 R7 l.OOK (Ml-H20)-l HM6514 -2.23 -4.87 8 A2 - 5 54LS368 -1.0 12.0 R8 l.OOK (Ml-M20)-17 HH6514 -2.23 -4.87 9 A2 - 7 54LS368 -1.0 12.0 R9 l.OOK (Ml-t-120)-16 HM6514 -2.23 -4.87 10 A2 - 9 54LS368 -1.0 12.0 RlO l.OOK (Ml-M20)-15 HM6514 -2.23 -4.87 11 A2 - 11 54LS368 -1.0 12.0 D004 .04 -.80

..- w 1-' INPUT/OUTPUT LOADING TABLE Bl CONT. SOURCE LOAD Item Ref. Des./ Part Num. Min @V CC = 4. Sv Ref. Des./ Part Num. Max@ VCC = 5 • 5v Num. Signal Name Outp. Cap. in rna Signal Name Loading in rna IOH IOL 1IH 1IL 12 A2 - 13 54LS368 -1.0 12.0 D005 .04 -.80 13 A3 - 3 54LS368 -1.0 12.0 R18 5 .9K (M1-N4 )-14 HM6514 A4-2 -. 30 -1.25 14 A.3 - 5 54LS368 -1.0 12.0 R19 5.9K (M1-M4)-13 HM6514 A4-4 -.30 -1.25 15 A3 - 7 54LS368 -1.0 12.0 R20 5.9K (M1-N4)-12 HN6514 A4-6 54LS368 -.30 -1.25 16 A3 - 9 54LS368 -1.0 12.0 R21 5.9K (M1-M4)-11 HM6514 A4-10 -.30 -1.25 17 A3 - 11 54LS368 -1.0 12.0 R22 5.9K (N5-M8)-14 HM6514 A2-12 54LS368 -. 30 -1.25 18 A3 - 13 54LS368 -1.0 12.0 R23 5.9K (M5-M8)-13 HM6514 A2-14 -.30 -1.25 19 A4- - 3 54LS368 -1.0 12.0 0000 .04 -.80 20 A4 - 5 54LS368 -1.0 12.0 0001 .04 -.80 21 A4 - 7 54LS368 -1.0 12.0 D002 .04 -.80

...... w. N.,, INPUT/OUTPUT LOADING TABLE B1 CONT. SOURCE LOAD Item Ref. Des./ Part Num. Min @ VCC = 4 • Sv Ref, Des./ Part Num. Max @ VCC = 5 • Sv Num. Signal Name Outp. Cap, in rna Signal Name Loading in rna 1oH 1oL 1IH 1IL 22 A4 - 9 54LS368 -1.0 12.0 D003 .04 -.80 23 A4 - 11 54LS368 -1.0 12.0 R28 5.9K (M9-Ml2)-12 HM6514 AS-12 54LS368 -.30 -1.25 24 A4 - 13 54LS368 -1.0 12.0 R29 5,9K (M9-Ml2)-11 HM6Sl4 AS-14 54LS368 -.30 -1. 2S 2S AS - 3 54LS368 -1.0 12.0 D006 .04 -.80 26 AS - S S4LS368 -1.0 12.0 D007 .04 -.80 27 AS - 7 S4LS368 -1.0 12.0 D008 .04 -.80 28 AS - 9 54LS368 -1.0 12.0 D009 ,04 -- .80 29 AS - 11 S4LS368 -1.0 12.0 DOlO .04 -.80 30 AS -:13 S4LS368 -1.0 12.0 DOll • 04 -.80 31 A6 - 3 S4LS368 -1.0 12.0 R24 S.9K (MS-M8)-12 HM6Sl4 AS-2 54LS368 -.30 -1.25 32 A6 - 5 54LS368 -1.0 12.0 R25 S.9K (M5-M8)-ll HM6Sl4 AS-4 54LS368 -.30 -1.2S

..... ·w w INPUT/OUTPUT LOADING TABLE Bl CONT. SOURCE LOAD Item Ref. Des./ Part Num. Hin@Vcc = 4.5v Ref. Des./ Part Num. Max@Vcc = 5.5v Num. Signal Name Outp. Cap. in rna Signal Name Loading in rna 1 1 1 1 oH 01 IH IL 33 A6 - 7 54LS368 -1.0 12.0 R26 S.9K (H9-M12)-14 HM6514 A5-6 -. 30 -1.25 34 A6 - 9 54LS368 -1.0 12.0 R27 S.9K (N9-M12)-13 HH6514 AS-10 54LS368 -. 30 -1.25 35 A6 - 11 54LS368 -1.0 12.0 R34 5.9K (M17-M20)-14 HM6514 A7-12 -.30 -1.25 36 A6 - 13 54LS368 -1.0 12.0 R35 5.9K (M17-M20)-13 HM6514 A7-14 -.30 -1.25 37 A7 - 3 54LS368 -1.0 12.0 D012 .04 -.80 38 A7 - 5 54LS368 -1.0 12.0 D013 .04 -.80 39 A7 - 7 54LS368 -1.0 12.0 D014 .04 -.80 40 A7 - 9 54LS368 -1.0 12.0 D015 .04 -.80 41 A7 - 11 54LS368 -1.0 12.0 D016 .04 -.80 42 A7 - 13 54LS368 -1.0 12,0 D017 • 04 -.80 43 A8 - 3 54LS368 -1.0 12.0 R30 5.9K (M13-M16)-14 HM6514 A7-2 54LS368 -.30 -1.25

...... w.p. INPUT/OUTPUT LOADING TABLE B1 CONT. SOURCE LOAD Item Ref. Des./ Part Num. !-Jin @ VCC = 4 • Sv Ref. Des./ Part Num. Max@Vcc = s.sv Num. Signal Name Outp. Cap. in rna Signal Name Loading in rna 1oH 1oL 1IH 1IL 44 A8 - 5 54LS368 -1.0 12.0 R31 5.9K (Ml3-Nl6)-13 HM6514 A7-4 -.30 -1.25 45 A8 - 7 54LS368 -1.0 12.0 R32 5.9K (M13-M16)-12 HN6514 A7-6 -.30 -1.25 46 A8 - 9 54LS368 -1.0 12.0 R33 S.9K (Ml3-Nl6)-11 HH6514 A7-10 -.30 -1.25 47 A8 - 11 54LS368 -1.0 12.0 D018 .04 - .80 48 A8 - 13 54LS368 -1.0 12.0 D019 .04 -.80 49 A9 - 3 54LS368 -1.0 12.0 D006 .04 -.80 so A9 - 5 54LS368 -1.0 12.0 D007 .04 -.80 51 A9 - 7 54LS368 -1.0 12.0 D008 .04 -.80 52 A9 - 9 54LS368 -1.0 12.0 D009 .04 -.80 53 A9 - 11 54LS368 -1.0 12.0 R36 5.9K (M17-M20)-12 HM6514 A8-12 -.30 -1.25 54 A9 - 13 54LS368 -1.0 12.0 R37 5.9K (M17-M20)-11 HM6514 A8-14 -.30 -1.25

...... w ll1 INPUT/OUTPUT LOADING TABLE Bl CONT. SOURCE LOAD Item Ref. Des./ Part Num. Min@Vcc = 4.5v Ref. Des./ Part Num. Max @ VCC = 5 • 5 v Num. Signal Name Outp. Cap. in rna · Signal Name Loading in rna 1 1 1oH IOL IH IL 55 AlO - 3 54LS368 -1.0 12.0 D002 .04 -.80 56 AlO - 5 54LS368 -1.0 12.0 D003 .04 -.80 57 AlO - 7 54LS368 -1.0 12.0 D004 .04 -.80 SR AlO - 9 54LS368 -1.0 12.0 DOOS .04 -.80 59 AlO - 11 54LS368 -1.0 12.0 DODO .04 -.80 60 AlO - 13 54LS368 -1.0 12.0 DOOl .04 -.80 61 All - 3 54LS368 -1.0 12.0 D012 .04 -.80 62 All - 5 54LS368 -1.0 12.0 D013 .04 -.80 63 All - 7 54LS368 -1.0 12.0 D014 .04 -.80 64 All - 9 54LS368 -1.0 12.0 D015 .04 -.80 65 All - 11 54LS368 -1.0 12.0 DOlO .04 -.80 66 All - 13 54LS368 -1.0 12.0 DOll .04 -.80 67 A12. - 3 54LS368 -1.0 12.0 D016 .04 -.80 68 A12 - 5 54LS368 -1.0 12.0 D017 -. 04 -.80 69 Al2 - 7 54LS368 -1.0 12.0 D018 .04 -.80 70 Al2 - 9 54LS368 -1.0 12.0 D019 .04 -.80 71 Al2 - 11 54LS368 -1.0 12.0 DREADY7'' .04 -.80 72 Al2 - 13 54LS368 -1.0 12.0 tv1BUSY7'• .04 -.80

I-' w 0'1 INPUT/OUTPUT LOADING TABLE Bl CONT. SOURCE LOAD Item Ref. Des,/ Part Num. Min@ VCC = 4. 5v Ref. Des./ Part Num. Max @V CC = 5 . 5v Nurn. Signal Name Outp, Cap. in rna Signal Name Loading in rna IOH 1oL 1IH 1IL 73 A13 - 3 54LS368 -1.0 12.0 A14-2,5,10, 54LS86 13 .16 -2.40 74 Al3 - 5 54LS368 -1.0 12.0 (F3-F6)-4,13 54LS75 .32 -4.80 75 A13 - 7 54LS368 -1.0 12.0 Open 76 Al3 - 9 54LS368 -1.0 12.0 Open 77 Al3 - 11 5L~LS368 -1.0 12.0 Op~m 78 A13 - 13 54LS368 -1.0 12.0 Open 79 A14 - 3 54LS86 -.40 4.0 A15-2 54LS32 A17-l 54LS08 .04 -.80 80 A14 - 6 54LS86 -.40 4.0 Al5-5 54LS32 A17-4 54LS08· .04 -.80 81 Al4 - 8 54LS86 -.40 4.0 Al5-10 54LS32 A17-9 54LS08 .04 -.80 82 Al4 - 11 54LS86 -,40 4.0 Al5-13 54LS32 Al7-12 54LS08 .04 -,80 83 A15 - 3 54LS32 -.40 4.0 1'-121 ,M25,H29 2716 -20 .03 -,03 84 A15 - 6 54LS32. -.40 4.0 H22,M26,M29 2716 -20 ,03 -.03 85 A15 - 8 54LS32 -.40 4.0 M23,H27 ,1'-131 2716 -20 .03 -.03

f-0 w '-.! INPUT/OUTPUT LOADING TABLE B1 CONT. SOURCE LOAD Item Ref. Des./ Part Nurn. Min@ VCC = 4. Sv Ref. Des./ Part Num. Max @V CC == 5 , Sv Num. Signal Name Outp. Cap. in rna Signal Name Loading in rna IOH IOL IIH IlL 86 A15 - 11 54LS32 .- .40 4.0 M24,M28,M32 2716 -20 .03 -.03 87 A16 - 3 54LS32 -.40 4.0 N21 ,M25,M29 2716 -18 .03 -.03 88 Al6 - 6 54LS32 -.40 4.0 M22,M26,M30 2716 -18 .03 -.03 89 A16 - 8 54LS32 _. t~o 4.0 M23,M27 ,M31 2716 -18 .03 -.03 90 Al6 - 11 SL~LS 32 -.40 4.0 M24,M28,M32 2716 -18 .03 -.03 91 Al7 - 3 5LtLS08 -.40 4.0 A16-1 54LS32 .02 -.40 92 A17 - 6 54LS08 -,40 4.0 A16-4 54LS32 .02 -.40 93 A17 - 8 54LS08 -.40 4.0 A16-9 54LS32 .02 -.40 94 A17 - 11 54LS08 -.40 4.0 Al6-12 54LS32 .02 -.40 95 A18 - 3 54LS08 -.40 4.0 A20-5 54LS20 .02 -.40 96 A18 - 6 54LS08 -.40 4.0 Al6-2,5,10, 54LS32 13 .08 -1.60 97 A18 - 8 54tS08 -.40 4.0 Open 98 A18 - 11 54LS08 -.40 4.0 Open 99 Al9 - 2 54LS04 -.40 4.0 F2-8 54LS164 .02 -.40

...... w ())_ INPUT/OUTPUT LOADING TABLE Bl CONT. SOURCE LOAD Item Ref. Des./ Part Num. Min @Vee= 4.Sv Ref. Des./ Part Num. Max @V CC = 5 • Sv Nurn. Signal Name Outp. Cap. in rna Signal Name Loading in rna IOH 1ot 1IH IlL 100 A19 - 4 54LS04 -.40 4.0 A21-2 54LS00 .02 -.40 101 A19 - 6 54LS04 -.40 4.0 A21-5 54LS00 A23-1 54LS00 .04 -.80 102 A19 - 8 54LS04 -.40 4.0 A18-2 54LS08 A21-13 54LS00 A22-5 54LS00 A23-5 54LS10 .08 -1.60 103 A19 - 10 54LS04 -.40 4.0 A24-3,5,6 54LS00 .06 -.80 104 Al9 - 12 54LS04 -.40 4.0 Open 105 A20 - 6 54LS20 -.40 4.0 A21-9 54LS00 .02 -.40 106 A20 - 8 54LS20 -.40 4.0 Al0-1,15 54LS368 A9-l 54LS368 A11-1,15 54LS368 A12-1 54LS368 .12 -2.40 107 A21 - 3 54LS00 -.40 4.0 A22-l 54LS00 .02 -.40 108 A21 - 6 54LS00 -.40 4.0 A22-2 54LS00 .02 -.40 109 A21 - 8 54LS00 -.40 4.0 Fl-9,F2-9 54LS164 Al2-14 54LS368 Al3-4 54LS368 A21-12 54LS00 A22-4 54LS00 .12 -2.40

...... w \0. INPUT/OUTPUT LOADING TABLE Bl CONT. SOURCE LOAD Item Ref. Des./ Part Num. Min @ VCC = 4. 5v Ref. Des./ Part Num. Max @ VCC = 5 • 5v Num. Signal Name Outp. Cap. in rna Signal Name Loading in rna IOH IOL IIH IIL 110 A21 - 11 54LS00 -.40 4.0 A18-1 54LS08 A21-10 54LS00 .04 -.80 111 A22 - 3 54LS00 - .40 4.0 Al2-12 54LS368 .02 -.40 112 A22 - 6 54LS00 -,40 4.0 A18-4 54-LS08 .02 -.40 113 A22 - 8 54LS00 -.40 4.0 Open 114 A22 - 11 SL•LSOO -.40 4.0 Open 115 A23 - 6 54LS10 -.40 4.0 A3-1,15 54LS368 A4-15 54LS368 A6-1,15 54LS368 A8-1 54LS368 A9-15 54LS368 .14 -2.80 116 A23 - 8 54LS10 -.40 l~. 0 A24-8 54LS01 .02 -.40 117 A23 - 12 54LS10 -.40 4.0 A2-5,A4-1 54LS368 AS-1,15 54LS368 A7-1,15 54LS368 A8-15 54LS368 .14 -2.40 118 A24 - 1 54LS01 ,00 4.0 Rll 2,05K M1 , MS , H9., 10 HN6514 -.95 -2.43 119 A24 - 4 54LS01 .oo 4.0 Rl2 2.05K Ml,MS,H9-8 HH6514 -.95 -2.43

...... ·.P. 0. INPUT/OUTPUT LOADING TABLE Bl CONT. SOURCE LOAD Item Ref. Des./ Part Num. Min@ VCC == 4. 5v Ref. Des./ Part Num. Max @ VCC = 5 • 5v Num. Signal Name Outp. Cap. in rna Signal Name Loading in rna 1oH IOL IIH 1IL 120 A24 - 10 54LS01 .oo 4.0 R17 1.54K (M2-M4)-10 HN6514 (M6-M12)-10 HM6514 -2.54 -3.69 . 121 A24 - 13 54LS01 .oo 4.0 Open 122 Fl - 3 54LS164 -.40 4.0 Open 123 Fl - 4 54LS164 -.40 4.0 Open 124 Fl - 5 54LS164 -.40 4.0 Open 125 Fl - 6 54LS164 -.40 4.0 Open 126 Fl - 9 54LS164 -.40 4.0 A19-9 54LS04. .02 -.40 127 F1 - 10 54LS164 -.40 4.0 Open 128 F1 - 11 54LS164 -.40 4.0 Open 129 Fl - 12 54LS16l~ -.40 4.0 Open 130 F2 - 3 54LS164 -.40 4.0 Fl-1 54LS164 F7-6 54LS138 A23-3 54LS10 .06 -1.20 131 F2 - 4 54LS164 -.40 4.0 Open 132 F2 - 5 54LS164 -.40 4.0 Open 133 F2 - 6 54LS164 - ,lt-0 4.0 Open 134 F2 - 10 54LS164 -.40 4.0 A23-2 54LS10 .02 -.40

...... +-- 1-'-t INPUT/OUTPUT LOADING TABLE B1 CONT. SOURCE LOAD Item Ref. Des./ Part Num. Nin @V CC = 4. 5v Ref. Des./ Part Num. Max @ VCC = 5 • 5v Num. Signal Name Outp. Cap. in rna Signal Name Loading in rna IOH IOL 1IH 1IL 135 F2 - 11 54LS164 -.40 4.0 A21-l 54LS00 .02 -.40 136 F2 - 12 54LS 16l~ -.40 4.0 Al9-3 54LS04 A21-4 54LS00 .04 -.80 137 F2 - 9 54.LS164 -.40 4.0 A19-5 54LS04 F7-4 54LS138 .04 -.80 138 F3 - 16 54LS75 -.40 4.0 A1-2 54LS368 (M21-H32)-8 2716 .14 -.52 139 F3 - 1 54LS75 -.40 4.0 Open 1L~O F3 - 15 54LS75 -.40 4.0 A1-4 54LS368 (lv121-M32)- 7 2716 • 14 -.52 141 F3 - 14 54LS75 -.40 4.0 Open 142 F3 - 10 54LS75 -.40 4.0 A1-6 54LS368 (H21-M32)-6 2716 .14 -.52 143 F3 - 11 54LS75 -.40 4.0 Open 144 F3 - 9 54LS75 -.40 4.0 A1-10 54LS368 (M21-M32)-5 2716 • 14 -.52 145 F3 - 8 54LS75 -.40 4.0 Open 1L~6 F4· - 16 54LS75 -.40 4.0 Al-12 54LS368 (M21-M32)-4 2716 .14 -.52 14 7 F4 - 1 54LS75 -.40 4.0 Open

...... p- N. INPUT/OUTPUT LOADING TABLE B1 CONT. SOURCE LOAD Item Ref. Des,/ Part Num. Min @ VCC = 4. Sv Ref. Des./ Part Num. Max@Vcc = s.sv Num. Signal Name Outp. Cap. in rna Signal Name Loading in rna 1oH 1oL 1IH IlL 148 F4 - 15 54LS75 -.40 4.0 A1-14 54LS368 0·121-t-132)- 3 2716 .14 -.52 149 F4 - 14 54LS75 ... 40 4.0 Open 150 F4 - 10 54LS75 -.40 '~. 0 A2-2 54LS368 ( M21-H32 )- 2 2716 .14 -.52 151 F4 - 11 54LS75 -.40 4.0 Open 152 Fl~ - 9 54LS75 -.40 4.0 A2-4 54LS368 (H21-M32) -1 2716 .14 -.52 153 F4 - 8 54LS75 -.40 4.0 Open 15lf FS - 16 54LS75 -.40 4.0 A2-6 54LS368 (M21-M32)-23 2716 .14 -.52 155 FS - 1 54LS75 -.40 4.0 Open 156 FS - 15 54LS75 -.40 4.0 A2-10 54LS368 (M21-H32)-22 2716 .14 -.52 157 FS - 14 54LS75 -.40 4.0 Open 158 FS - 10 54LS75 -.40 4.0 F7-1 54LS 138 .02 -.40 159 F5 - 11 54LS75 -.40 4.0 Open 160 F5 - 9 54LS75 _.t.o 4.0 F7-2,F8-1 54LS138 .04 -.80 161 FS - 8 54LS75 -.40 4.0 Open 162 F6 - 16 54LS75 -.40 4.0 F7-3,F8-2 54LS138 .04 -.80 ...... +'- UJ INPUT/OUTPUT LOADING B1 CONT. SOURCE LOAD Item Ref. Des./ Part Num. Min @V CC = 4. Sv Ref. Des./ Part Nurn. Hax@Vcc = 5.5v Num. Signal Name Outp. Cap. in rna Signal Name Loading in rna 1oH 1oL 1IH 1IL 163 F6 - 1 54-LS75 -.40 4.0 Open 164 F6 - 15 54LS75 -.40 4.0 F7-5,F8-3 54LS138 .04 -.40 165 F6 - 14 54LS75 -.40 4.0 Open 166 F6 - 10 54LS75 -.40 4.0 A23-13 54LS10 .02 -.40 167 F6 - 11 54LS75 -.40 4.0 A23-4 54LS10 A24-2,9 54LS01 .06 -1.20 168 F6 - 9 54LS75 -.40 4.0 Open 169 F6 - 8 5LILS75 -.40 4.0 Open 170 F7 - 15 54LS138 -.40 4.0 A19-11 54LS04 .02 - .40 171 F7 - 14 54LS138 -.40 4.0 A23-11 54LS10 R13 2.05K (M2, M6, MJO, HH6514 M14,M18)-8 -1.25 -3. 10 172 F7 - 13 54LS 138 -.40 4.0 R14 2.05K A23-10 54LS10 OO,N7,Nll, HN6514 Ml5,Ml9)-8 -1.25 -3.10 173 F7 - 12 54LS138 -.40 4.0 R15 2.05K A23-9 54LS10 (H4,M8,H12, HM6514 H16,H20)-8 -1.25 -3. 10

;g:...... INPUT/OUTPUT LOADING B1 CONT. SOURCE LOAD Item Ref. Des./ Part Num. Min @ Vcc = 4 • 5v Ref. Des./ Part Num. Max @V CC = 5 • 5v Num. Signal Name Outp. Cap. in rna Signal Name Loading in rna 1 1 1oH 101 IH IL 174 F7 - 11 54LS138 -.40 4.0 Open 175 F7 - 10 54LS 138 -.40 4.0 Open 176 F7 - 9 54LS138 .,. .40 4.0 Open 177 F7 - 7 54LS138 -.40 4.0 Open l7R F8 - 15 54LS138 -.40 4.0 Open 179 F8 - 14 54LS138 -.40 4.0 Open 180 F8 - 13 54LS138 -.40 4.0 A14-l 54LS86 A15-1 54LS32 A20-13 54LS20 .06 -1.20 181 F8 - 12 54LS138 -.40 4.0 A14-4 54LS86 A15-4 54LS32 A20-12 54LS20 .06 -1.20 182 F8 - 11 54LS138 -.40 4.0 A14-9 54LS86 A15-9 54LS32 A20-10 54LS20 .06 -1.20 183 F8 - 10 54LS138 -.40 4.0 A14-12 54LS86 A.15-12 54LS32 A20-9 54LS20 .06 -1.20 184 F8 - 9 54LS 138 -.40 4.0 Open 185 F8 - 8 54LS138 -.40 4.0 Open

...... p.. lJl 146

STANDBY MODE POWER COMPUTATION TABLE B2 Devices Type Current in rna Power in mw Typical Maximum Typical Haximum 1on1Icc M1 - ~15 HM6514 o.oo 0.25 o.oo 1. 31 R11, R12 2.05K o.oo 0.21 o.oo 1.10 Subtotal o.oo 0.46 o.oo 2.41 1cc21Icc Rl - RlO LOOK 23.75 52.82 118. 75 277.31 R13 - R15 2.05K 0.03 0.32 0. 15 1.68 R17 1.54K 0.01 0.10 0.05 0.53 R18 - R37 5.90K 0.50 1.24 2.50 6.51 Subtotal 24.29 54.48 121.45 286.03 1cc Al - A13 54LS368 260.00 338.00 1300.00 1774.50 A14 54LS86 6.10 10.00 30.50 52.50 A15, A16 54LS32 6.60 13.30 33.00 69.83 A17, A18 54LS08 4.80 9.60 24.00 50.40 A19 54LS04 3.00 5.55 15.00 29.14 A20 54LS20 0.40 0.80 2.00 4.20 A21, A22 54LS00 2.40 4.60 12.00 24. 15 A23 54LS10 0.60 1. 20 3.00 6.30 A24 54LS01 0.80 1.60 4.00 8.40 F1, F2 54LS 164 32.00 54.00 160.00 283.50 F3 - F6 54LS75 25.20 48.00 126.00 252.00 F7, F8 54LS138 12.60 20.00 63.00 105.00 M6 - M20 HM6514 0.10 1.00 0.50 5.25 M21 - M32 2716 156.00 360.00 780.00 1890.00 R16 2.05K 0.01 0.12 0.05 0.63 Volt. Sw. 35.40 45.20 177.0 237.30 Subtotal 546.01 912.97 2730.05 4793.10 Total 570.30 967.91 2851.50 5081.54 147

CMOS RAH CYCLING POWER COMPUTATION TABLE B3 Devices Type Current in rna Power in mw Typical Maximum Typical ~'!aximum IDD/ICC M1 - M5 HM6514 20.83 29.17 104. 15 153. 14 R11, R12 2.05K 4.63 5.15 23.15 27.04 Subtotal 25.46 34.32 127.30 180. 18 Icc21Icc R1 - RlO l.OOK 23.75 52.82 118.7S 277.31 R13 - RlS 2.0SK .03 .32 .1S 1.68 R17 l.S4K .01 .10 .OS .53 Rl8 - R37 S.90K 12.20 14.92 61.00 78.33 Subtotal 35.99 68.16 179.9S 3S7. 85 Icc A1 - A13 54LS368 260.00 338.00 1300.00 1774.SO A14 54LS86 6. 10 10.00 30.SO S2.SO AlS, A16 54LS32 6.20 13.30 31.00 69.83 A17, A18 54LS08 5.80 11.60 29.00 60.90 A19 54LS04 3.00 s.ss 1S.OO 29.14 A20 54LS20 0,40 0.80 2.00 4.20 A21, A22 54LS00 2.80 5.30 14.00 27.83 A23 S4LS10 1.40 2.60 7.00 13.6S A24 54LS01 1.60 3.60 8.00 18.90 F1, F2 54LS164 32.00 54.00 .. 160.00 283. so F3 - F6 54LS75 25.20 48.00 126.00 252.00 F7, F8 54LS138 12.60 20.00 63.00 105.00 M6 - M20 HM6S14 0.10 1.00 0.50 5.25 M2l - M32 2716 156. 00 360.00 780.00 1890.00 R16 2.0SK 0.01 0.12 0.05 0.63 Volt. Sw. 35.40 45.20 177.0 237.30 Subtotal 548.61 919.07 2745.05 4825.13 Total 610.06 1021.SS 30S2.30 5363.16 L'VE PROM CYCLING POWER CONFUTATION TABLE B4 Devices Type Current in rna Power in mw Typical Naxirnum Typical Maximum Inn/Icc M1 - MS HM6514 o.oo 0.25 o.oo 1. 31 R11, R12 2.05K 0.00 0.21 o.oo 1.10 Subtotal o.oo 0.46 o.oo 2.41 Icc21Icc R1 - R10 1.00K 23.75 52.82 118.75 277.31 R13 - RlS 2.05K 0.03 0.32 0.15 1.68 R17 1.54K 0.01 0.10 o.os 0.53 R18 - R37 5.90K o.so 1. 24 2.50 6.51 Subtotal 24.29 54.48 121.45 286.03 Icc A1 - A13 54LS368 260.00 338.00 1300.00 1774.50 A14 54LS86 6. 10 10.00 30.50 52.50 A15, A16 54LS32 7.10 14.20 35.50 74.55 A17, A18 54LS08 6.30 12.60 31.50 66.15 A19 54LS04 3.00 5.55 15.00 29.14 A20 54LS20 0.40 0.80 2.00 4.20 A21, A22 54LS00 2.80 5.30 14.00 27.83 A23 54LS10 1.00 1.90 5.00 9.98 A24 54LS01 0.80 1.60 4.00 8.40 F1, F2 54LS164 32.00 54.00 160.00 283.50 F3 - F6 54LS75 25.20 48.00 126.00 252.00 F7, F8 54LS 138 12.60 20.00 63.00 105.00 M6 - M20 :ffi.-16 5 14 0.10 1.00 0.50 5.25 M21 - M32 2716 273.50 537.50 136 7. so 2821.88 R16 2.05K 0.01 0.12 o.os 0.63 Volt. Sw. 35.40 45.20 177.00 237.30 Subtotal 666.31 1095.77 3331.55 5752.81 Total 716.59 1150.71 3453.00 6041.25 149

PROGRAMMING MODE POWER CALCULATION TABLE BS Devices Type Current in rna Power in mw Typical Maximum Typical Maximum IDD/ICC M1 - MS HM6514 o.oo 0.25 0.00 1. 31 R11, Rl2 2.05K o.oo 0.21 o.oo 1.10 Subtotal o.oo 0.46 o.oo 2.41 Icc21Icc Rl - R10 LOOK 23.75 52.82 118.75 277.31 Rl3 - R15 2.05K 0.03 0.32 0.15 1.68 R17 1.54K 0.01 0.10 0.05 0.53 Rl8 - R37 5.90K 0.50 1.24 2.50 6.51 Subtotal 24.29 54.48 121.45 286.03 Icc Al - A13 54LS368 260.00 338.00 1300.00 1774.50 A14 54LS86 6.10 10.00 30.50 52~50 A15, A16 54LS32 7.10 14.20 35.50 74.55 Al7, A18 54LS08 6.30 12.60 31.50 66.15 A19 54LS04 3.00 5.55 15.00 29.14 A20 54LS20 0.40 0.80 2.00 4. 20 A21, A22 54LS00 2.80 5.30 14.00 27.83 A23 54LS10 1.00 1.90 5.00 9.98 A24 54LS01 0.80 1.60 4.00 8.40 F1, F2 54LS164 32.00 54.00 160.00 283. so F3 - F6 54LS138 12.60 20.00 63.00 105.00 M6 - M20 HM6514 0. 10 1.00 o.so 5.25 M21 - M32 2716 684.00 1200.00 3420.00 6300.00 R16 2.05K 0.01 0.12. 0.05 0.63 Volt. Sw. 35.40 45.20 177.00 237.30 Subtotal 1051.61 1710.27 5258.05 8978.93 Ipp 'M21 - M32 2716 102.00 135.00 2550.00 3510.00 Total 1177.90 1900.21 7929. so 12777.37 150

COMPONENT POWER DISSIPATION TABLE B6 Schematic Nominal Power Dissipation in mw Designation Value/Type Typical Maximum R1 - RlO l.OOK ohms 23.8 27.7 Rll - R15 2.05K ohms 11.6 13.5 R16 2.05K ohms 0.0 0.7 R17 1. 54K ohms 15.0 19.4 R18 - R37 5.90K ohms 3.0 3.9 R38 121 ohms 43.7 68.3 R39 715 ohms 3.2 7.4 R40 909 ohms 18.9 25 .o R41, R45 4.87K ohms 0.1 0.2 R42 33 ohms 498.2 703.7 R43 187 ohms 129.8 148.6 R44 383 ohms 44.8 59.4 R46 5.6 ohms 3.7 4.5 Ql 2N3762A 5.2 8.3 Q2 2N2369A 2.1 3.7 Q3 2N3762A o.o 145.6 Q4 2N3762A 10.0 18.4 A1 - Al3 54LS368 100.0 136.5 A14 54LS86 30.5 52.5 A15, A16 54LS32 16.5 37.3 A17, Al8 54LS08 14.5 33.1 A19 54LS04 15.0 29.1 A20 54LS20 2.0 4.2 A21, A22 54LS00 7.0 13.9 A23 54LS10 7.0 13.6 A24 54LS01 8.0 15.8 F1, F2 54LS164 80.0 141.8 F3 - F6 54LS75 31.5 42.0 F7, F8 54LS138 31.5 52.5 M1 - M20 HM6514-2 o.o 30.6 M21 - M32 2716 1135.0 1695.0 Dl 1N4371A 57.1 . 65.9