4K TV Development Made Easy with the Zynq Soc
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XCELLENCE IN VIDEO PROCESSING 4K TV Development Made Easy with the Zynq SoC by Roger Fawcett Managing Director OmniTek [email protected] 26 Xcell Journal Fourth Quarter 2014 XCELLENCE IN VIDEO PROCESSING ltrahigh-definition (UHD) TVs, also called 4K for Xilinx All Programmable their resolution level, are already widely avail- technology can be a boon able and 4K is proving 4K TV Development a much more popular for designers of 4K video technology than 3D TV among consumers. But systems. Associated tools, the standards lag behind the uptake. Society of UMotion Picture & Television Engineers (SMPTE) Made Easy with standards for 6-Gbps and 12-Gbps SDI, support- IP and reference designs ing 4K60 video, are only just being released, while HDMI™ 2.0 and DisplayPort supporting will help those new to the same resolution are in the early stages of adoption. Given the significant consumer de- the Zynq SoC FPGA design.. mand for 4K UHD TVs, many ad hoc standards have rushed in to fill the void. Indeed, so much about 4K UHD TV is in a state of flux that it is essential for systems to be flexible enough to adapt to the devel- oping standards. The way to ensure flexibil- ity is to replace the time-honored chip sets and ASSPs long used for these designs with FPGAs and All Programmable systems-on- chip such as the Xilinx® Zynq®-7000 All Pro- grammable SoC. These solutions offer the flexibility needed while also delivering perfor- mance comparable to that of ASICs. At the same time, the size and perfor- mance of the latest FPGAs and SoCs present considerable design challenges, especially to engineers who are not particularly FPGA- savvy. While there are many similarities in the design of hardware and FPGA imple- mentations, FPGA-based systems typically involve many more components. In addition, the inherent flexibility of firmware designs introduces extra complications. Fortunately, Xilinx offers a lot of help for 4K TV designers—all at a much lower cost in both time and money than designing your system from scratch. But before delving into the details of how to use FPGA technology for 4K applica- tions, let’s first take a look at how 4K systems have managed to become so popular so quickly, and the issues that any 4K system has to address. THE UPSIDES AND DOWNSIDES OF 4K Ever since television was first invented, there has been a constant drive toward making the images it shows closer to real life. This effort typically comes down to providing bigger, bet- ter and faster video by increasing the resolution, Fourth Quarter 2014 Xcell Journal 27 XCELLENCE IN VIDEO PROCESSING the frame rate or the dynamic range of defined for 4K—all involving mul- FIRST LEVEL OF ASSISTANCE: the images (that is, how bright they tiple data streams, some delivered 4K IP CORES can be)—plus, of course, attempting multiplexed on the same cable, some The first step in designing any system is to achieve either a true 3D effect or at on different cables—and the differ- to find ready-made blocks that you can least a more immersive feel. ent technologies emerging to supply usefully include in your design. In the Increasing the resolution allows the them: 4x3G; 6G-SDI and 12G-SDI; FPGA world, the equivalent building images to be more detailed and makes HDMI 1.4 and 2.0; DisplayPort 1.2; blocks to the various chips available for it possible to display them on larger and V-by-One HS. inclusion in a PCB design are intellectu- screens without the pixelation becom- Another issue for designers is the al-property (IP) cores. So your first step ing obvious. Bigger screens give a more need for any system to handle not just is to identify what IP cores are available immersive feel. These are improvements 4K but also many if not all of the video for use in your 4K UHD design. that customers find easy to appreciate standards currently in use, including OmniTek is a good source of IP and hence, are willing to spend money SD. In addition, the system must sup- cores for all types of video system on. The improvements brought about port conversion among these differ- design. The company, which is a cer- by increasing the frame rate (smoother ent standards with all the associated tified member of the Xilinx Alliance motion) or the dynamic range (brighter issues of up/down/cross-conversion, Program, has a depth of experience in lights and darker blacks), while compel- nonmatching color spaces, color cor- video processing, initially as developer ling, have been slower to capture the rection, interlacing and deinterlacing, of its own video test-and-measurement consumer’s imagination so far. and cadence handling. An addition- (T&M) systems. These systems needed The new 4K UHD TV represents a al complication is that upconversion dedicated hardware, which in turn led quadrupling of the number of pixels typically also needs to be followed by to the development of dedicated firm- from the previously sought-after HD the application of so-called “super-res- ware blocks. Those firmware blocks standards. Perhaps most important for olution” enhancement techniques to are now also available as IP cores. The customers, 4K allows them to upgrade counteract the image smoothing that creation of OmniTek’s latest T&M sys- to a much larger TV that offers a much inevitably results. tem, the newly launched Ultra 4K Tool more immersive feel without any obvi- Other processes that may be needed Box, led to the development of a range ous effect on the image quality. include noise reduction, cropping and of 4K-capable IP cores, now available to There are, however, plenty of tech- resizing—all to be done in real time. third-party developers. nical challenges intrinsic to develop- Some systems may also need to handle Two cores in particular are useful ing systems to support 4K video. For High-Bandwidth Digital Copy Protec- to designers of 4K systems: Omni- a start, a frame size of 3,840 x 2,160 tion (HDCP). Tek’s OSVP v2 Scalable Video Proces- pixels delivered at frame rates of up Furthermore, anyone needing to deter- sor and its Multi-Channel Streaming to 60 Hz represents a 600-MHz pixel mine the quality of the broadcast transmis- DMA Controller, both of which are rate. It takes a very high-performance sions will also need to generate appropri- available targeted for Xilinx 7 series system to process this rate in real ate eye and jitter displays, the technology FPGAs and Zynq SoCs. Both cores time. Then there are the different de- for which becomes increasingly difficult adopt the ARM® AMBA® AXI4 system livery configurations that are being to implement at higher bit rates. interconnect standards. AXI4-MM Memory Interface AXI-4 Stream AXI-4 Stream Video Memory Memory Chroma L L Video 1:2 Color-Space Deinterfacer Noise Cropper Resizer Write Read 2:1 Upsampler U Converter U Reduction RGB or YUV T T RGB or YUV 4:2:2 or 4:4:4 4:2:2 or 4:4:4 Progressive, Progressive, Interlaced or PsF Crosspoint Interlaced or PsF up to up to 4096 x 2160@60 4096 x 2160@60 OSVP 2.0 in 2-pixel conguration (suitable for 4K) AXI4-Lite CPU Interface Figure 1 – Input channel architecture of OmniTek’s OSVP v2 Scalable Video Processor core 28 Xcell Journal Fourth Quarter 2014 XCELLENCE IN VIDEO PROCESSING Figure 2 – The RTVE 3.1 video design as laid out within Vivado IP Integrator, together with Configuration window The OSVP v2’s facilities include A single OSVP v2 core can process block that provides a highly efficient six-axis color correction; motion- and multiple video channels. The limiting engine for handling video input/output. edge-adaptive deinterlacing (complete factors are the resources offered by the Capturing and playing out one or with 3:2 and 2:2 film cadence detection FPGA or SoC on which it is implement- more channels of 4K60 over PCI Ex- and processing); the ability to resize ed and the amount of SDRAM band- press®, however, requires a DMA con- and crop with image sharpening and width available. For example, you could troller optimized for handling streaming smoothing; and noise reduction. Figure configure an OSVP core implemented on data across a PCIe® interface. Omni- 1 shows a block diagram of this core. a Kintex®-7 XC7K325T FPGA to support Tek’s Multi-Channel Streaming DMA You configure the selection of process- up to eight inputs handling video at eight Controller has a couple of key features ing facilities that are included at com- different HD video standards, eight color to help here. The first is FIFO-based pile-time, while further details of the spaces and so on. At the same time, you DMA (FDMA), which bypasses the need processing carried out by the OSVP v2 could configure the output block for up to transfer the data in and out of mem- core can either be set at run-time or to 16 progressive HD outputs. Alterna- ory. The second is a series of design driven from software. tively, you could set up the output block optimizations that allow the controller The OSVP v2 core comes as part of a to offer either a single 4K channel or a to make highly efficient use of the PCIe suite that also includes a combiner for set of four channels that together offer bandwidth, such as by prefetching of combining multiple video streams; an Square Division (“quad”) or 2-Pixel Sam- scatter-gather-mode descriptors and interlacer for producing output in inter- ple Interleave 4K.