Service Manual
Service Manual U8550 Model : U8550
Date: November, 2005 / Issue 1.0 Table of Contents
1. INTRODUCTION ...... 6 3.2.2 Block Description ...... 44 3.2.3 Camera & Camera FPC Interface... 46 1.1 Purpose...... 6 3.2.4 Camera Regulator ...... 49 1.2 Regulatory Information...... 6 3.2.5 Display & LCD FPC Interface ...... 50 1.3 Abbreviations ...... 8 3.2.6 Main&Sub LCD Backlight Illumination...52 2. PERFORMANCE...... 10 3.2.7 Camera Flash LED Illumination ...... 52 3.2.8 Keypad Illumination ...... 53 2.1 System Overview...... 10 3.3 LCD Module...... 54 2.2 Usable environment...... 11 3.4 Analog Baseband (ABB) Processor...... 55 2.3 Radio Performance...... 11 3.4.1 Overview of Audio path...... 55 2.4 Current Consumption...... 19 3.4.2 Audio Signal Processing 2.5 RSSI...... 19 & Interface...... 56 2.6 Battery Bar...... 19 3.4.3 Audio Mode...... 58 2.7 Sound Pressure Level...... 20 3.4.4 Voice Call...... 59 2.8 Charging ...... 21 3.4.5 MIDI (Ring Tone Play) ...... 62 3.4.6 MP3 (Audio Player)...... 63 3. Technical Brief ...... 22 3.4.7 Video Telephony...... 64
3.1 Digital Baseband(DBB) & Multimedia 3.4.8 Audio Part Main Components...... 65 Processor ...... 22 3.4.9 GPADC(General Purpose ADC) and 3.1.1 General Description ...... 22 AUTOADC2 ...... 67 3.1.2 Hardware Architecture ...... 23 3.4.10 Charger control ...... 68 3.1.3 External memory interface...... 27 3.4.11 Fuel Gauge ...... 69 3.1.4 RF Interface ...... 28 3.4.12 Battery Temperature 3.1.5 SIM Interface ...... 30 Measurement...... 70 3.1.6 UART Interface ...... 31 3.4.13 Charging Part...... 71 3.1.7 GPIO (General Purpose Input/Output) 3.5 Voltage Regulation...... 74 map...... 32 3.5.1 Internal Regulation...... 74 3.1.8 USB ...... 33 3.5.2 External Regulation ...... 74 3.1.9 Folder ON/OFF Detection...... 35 3.6 General Description of RF Part...... 76 3.1.10 Bluetooth Interface...... 36 3.7 GSM Mode...... 78 3.1.11 TransFlash Interface...... 39 3.7.1 Receiver...... 78 3.1.12 Power On Sequence...... 40 3.7.2 Transmitter...... 83 3.1.13 Keypad...... 41 3.8 WCDMA Mode...... 85 3.2 GAM Hardware Subsystem ...... 43 3.8.1 Receiver...... 85 3.2.1 General Description ...... 43 3.8.2 Transmitter...... 88
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3.8.3 Frequency Generation ...... 92 4.20.1 Checking VCXO Block...... 154 4.20.2 Checking Ant. SW module...... 154 4. TROUBLE SHOOTING ...... 94 4.20.3 Checking Control Signal ...... 154 4.1 Power ON Trouble ...... 94 4.20.4 Checking RF TX Level...... 156 4.2 USB Trouble ...... 96 4.20.5 Checking PAM Block ...... 159 4.3 SIM Detect Trouble...... 97 4.20.6 Checking RX I,Q ...... 162 4.4 TransFlash Trouble...... 98 4.21 Checking GSM Block...... 164 4.21.1 Checking Regulator Circuit ...... 165 4.5 Keypad Trouble...... 99 4.21.2 Checking VCXO Block...... 165 4.6 1.3M Camera Trouble...... 101 4.21.3 Checking Ant. SW Module...... 165 4.7 VGA Camera Trouble ...... 103 4.21.4 Checking Control Signal ...... 166 4.8 Main LCD Trouble...... 105 4.21.5 Checking RF Tx Path...... 168 4.9 Sub LCD Trouble ...... 107 4.22 Checking Bluetooth Block...... 181 4.10 Keypad Backlight Trouble...... 109 4.11 Camera Flash Trouble ...... 111 5. BLOCK DIAGRAM ...... 185
4.12 Audio Trouble...... 113 5.1 GSM & WCDMA RF Block...... 185 4.12.1 Receiver...... 113 4.12.2 Speaker ...... 117 6. DOWNLOAD ...... 187 4.12.3 Microphone ...... 121 6.1 The Purpose of Downloading 4.12.4 Headset - Receiver ...... 125 Software ...... 187 4.12.5 Headset - MIC...... 126 6.2 Download Environment Setup ...... 187 4.12.6 Headset ...... 127 6.3 U8XXX Download ...... 188 4.13 Charger Trouble...... 128 4.14 RF Component...... 130 7. CALIBRATION ...... 200 4.15 Procedure to check...... 132 7.1 General Description ...... 200 4.16 Checking Common Power 7.2 XCALMON Environment...... 200 Source Block...... 133 7.2.1 H/W Environment...... 200 4.17 Checking VCXO Block...... 140 7.2.2 S/W Environment...... 200 4.18 Checking Ant. SW Module Block ...... 145 7.2.3 Configuration Diagram of 4.19 Checking Antenna Switch Block input Calibration Environment...... 200 logic...... 146 7.3 Calibration Explanation...... 201 4.19.1 Mode Logic by TP Command ...... 146 7.3.1 Overview...... 201 4.19.2 Checking Switch Block 7.3.2 Calibration Items...... 201 power source ...... 148 7.3.3 EGSM 900 Calibration Items ...... 202 4.20 Checking WCDMA Block ...... 153 7.3.4 DCS 1800 Calibration Items ...... 207
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7.3.5 WCDMA Calibration Items...... 210 7.3.6 Baseband Calibration Item ...... 218 7.4 Program Operation ...... 219 7.4.1 XCALMON Program Overview ..... 219 7.4.2 XCALMON Icon Description ...... 220 7.4.3 Calibration Procedure ...... 223 7.4.4 Calibration Result Message...... 225
8. Circuit Diagram ...... 229
9. pcb layout ...... 239
10. EXPLODED VIEW & REPLACEMENT PART LIST ..... 248
10.1 EXPLODED VIEW ...... 248 10.2 Replacement Parts
- 5 - 1. INTRODUCTION
1. INTRODUCTION
1.1 Purpose
This manual provides the information necessary to repair, calibration, description and download the features of this model.
1.2 Regulatory Information
A. Security
Toll fraud, the unauthorized use of telecommunications system by an unauthorized part (for example, persons other than your company’s employees, agents, subcontractors, or person working on your company’s behalf) can result in substantial additional charges for your telecommunications services. System users are responsible for the security of own system. There are may be risks of toll fraud associated with your telecommunications system. System users are responsible for programming and configuring the equipment to prevent unauthorized use. The manufacturer does not warrant that this product is immune from the above case but will prevent unauthorized use of common-carrier telecommunication service of facilities accessed through or connected to it. The manufacturer will not be responsible for any charges that result from such unauthorized use.
B. Incidence of Harm
If a telephone company determines that the equipment provided to customer is faulty and possibly causing harm or interruption in service to the telephone network, it should disconnect telephone service until repair can be done. A telephone company may temporarily disconnect service as long as repair is not done.
C. Changes in Service
A local telephone company may make changes in its communications facilities or procedure. If these changes could reasonably be expected to affect the use of the phones or compatibility with the network, the telephone company is required to give advanced written notice to the user, allowing the user to take appropriate steps to maintain telephone service.
D. Maintenance Limitations
Maintenance limitations on the phones must be performed only by the manufacturer or its authorized agent. The user may not make any changes and/or repairs expect as specifically noted in this manual. Therefore, note that unauthorized alternations or repair may affect the regulatory status of the system and may void any remaining warranty.
- 6 - 1. INTRODUCTION
E. Notice of Radiated Emissions
This model complies with rules regarding radiation and radio frequency emission as defined by local regulatory agencies. In accordance with these agencies, you may be required to provide information such as the following to the end user.
F. Pictures
The pictures in this manual are for illustrative purposes only; your actual hardware may look slightly different.
G. Interference and Attenuation
A phone may interfere with sensitive laboratory equipment, medical equipment, etc. Interference from unsuppressed engines or electric motors may cause problems.
H. Electrostatic Sensitive Devices
ATTENTION
Boards, which contain Electrostatic Sensitive Device (ESD), are indicated by the sign. Following information is ESD handling:
• Service personnel should ground themselves by using a wrist strap when exchange system boards. • When repairs are made to a system board, they should spread the floor with anti-static mat which is also grounded. • Use a suitable, grounded soldering iron. • Keep sensitive parts in these protective packages until these are used. • When returning system boards or parts like EEPROM to the factory, use the protective package as described.
- 7 - 1. INTRODUCTION
1.3 Abbreviations
For the purpose of this manual, following abbreviations apply.
APC Automatic Power Control BB Baseband BER Bit Error Ratio CC-CV Constant Current - Constant Voltage CLA Cigar Lighter Adapter DAC Digital to Analog Converter DCS Digital Communication System dBm dB relative to 1 milliwatt DSP Digital Signal Processing DTC DeskTop Charger EEPROM Electrical Erasable Programmable Read-Only Memory EL Electroluminescence ESD Electrostatic Discharge FPCB Flexible Printed Circuit Board GMSK Gaussian Minimum Shift Keying GPIB General Purpose Interface Bus GPRS General Packet Radio Service GSM Global System for Mobile Communications IPUI International Portable User Identity IF Intermediate Frequency LCD Liquid Crystal Display LDO Low Drop Output LED Light Emitting Diode OPLL Offset Phase Locked Loop PAM Power Amplifier Module PCB Printed Circuit Board PGA Programmable Gain Amplifier PLL Phase Locked Loop
- 8 - 1. INTRODUCTION
I. Introduction
1.3 Abbreviations
For the purpose of this manual, following abbreviations apply.
PSTN Public Switched Telephone Network RF Radio Frequency RLR Receiving Loudness Rating RMS Root Mean Square RTC Real Time Clock SAW Surface Acoustic Wave SIM Subscriber Identity Module SLR Sending Loudness Rating SRAM Static Random Access Memory UMTS Universal Mobile Telephony System
- 9 - 2. PERFORMANCE
2. PERFORMANCE
2.1 System Overview
Item Specification Shape GSM900/1800/1900 & WCDMA Folder- Dual Mode Handset Size 90 x 55 x 24.7mm Weight 134g (with Standard Battery) Power 1400mA Li-Polymer Over 180 Min (WCDMA, Tx=12 dBm, Voice) Talk Time Over 220 Min (GSM, Tx=Max, Voice) Over 165 hrs (WCDMA, DRX=1.28) Standby Time Over 223 hrs (GSM, Paging period=9) Antenna Fixed Type (Fixed Screw) Main LCD 220 x 220 TFT LCD 262K Color Sub LCD 128 x 160 TFT LCD 262K Color Main/Sub LCD BL White LED Backlight Vibrator Yes (Cylinder Type) LED Indicator Blue C-MIC Yes Receiver Yes
Earphone Jack Yes SIM Socket Yes (3.0V/1.8V) Volume Key Push Type(+,-) Voice Key Push Type (Memo) External Memory T - Flash Socket I/O Connect 24 Pin
- 10 - 2. PERFORMANCE
2.2 Usable environment
1) Environment
Item Spec. Unit Voltage 4.0 (Typ), 3.4 (Min), (Shut Down: 3.2) V Operating Temp. -20 ~ + 60 °C Storage Temp. -30 ~ + 85 °C Humidity max. 85 %
2) Environment(Accessory)
Item Spec. Min Typ. Max Unit Power Available power 100 220 240 Vac * CLA: 12~24V(DC)
2.3 Radio Performance
1) Transmitter -GSM Mode
No Item GSM DCS/PCS 9k ~ 1GHz -39dBm 100k ~ 1GHz -39dBm MS allocated 1G ~ 1710MHz -33dBm Channel 1710M ~ 1785MHz -39dBm 1G ~ 12.75GHz -33dBm Conducted 1785M ~ 12.75GHz -33dBm 1Spurious 100k ~ 880MHz -60dBm 100k ~ 880MHz -60dBm Emission 880M ~ 915MHz -62dBm 880M ~ 915MHz -62dBm 915M ~ 1000Mz -60dBm 915M ~ 1000MHz -60dBm Idle Mode 1G ~ 1.71GHz -50dBm 1G ~ 1.71GHz -50dBm 1.71G ~ 1.785GHz -56dBm 1.71G ~ 1.785GHz -56dBm 1.785G ~ 12.75GHz -50dBm 1.785G ~ 12.75GHz -50dBm
- 11 - 2. PERFORMANCE
No Item GSM DCS/PCS 30M ~ 1GHz -36dBm 30M ~ 1GHz -36dBm MS allocated 1G ~ 1710MHz -30dBm Channel 1710M ~ 1785MHz -36dBm 1G ~ 4GHz -30dBm Radiated 1785M ~ 4GHz -30dBm 1 Spurious 30M ~ 880MHz -57dBm 30M ~ 880MHz -57dBm Emission 880M ~ 915MHz -59dBm 880M ~ 915MHz -59dBm 915M ~ 1000Mz -57dBm 915M ~ 1000MHz -57dBm Idle Mode 1G ~ 1.71GHz -47dBm 1G ~ 1.71GHz -47dBm 1.71G ~ 1.785GHz -53dBm 1.71G ~ 1.785GHz -53dBm 1.785G ~ 4GHz -47dBm 1.785G ~ 4GHz -47dBm 2 Frequency Error ±0.1ppm ±0.1ppm ±5(RMS) ±5(RMS) 3 Phase Error ±20(PEAK) ±20(PEAK) 3dB below reference sensitivity 3dB below reference sensitivity Frequency Error Under RA250: ±200Hz RA250: ±250Hz 4 Multipath and Interference HT100: ±100Hz HT100: ±250Hz Condition TU50: ±100Hz TU50: ±150Hz TU3: ±150Hz TU1.5: ±200Hz 0 ~ 100kHz +0.5dB 0 ~ 100kHz +0.5dB
200kHz -30dB 200kHz -30dB 250kHz -33dB 250kHz -31dB Due to 400kHz -60dB 400kHz -33dB modulation 600 ~ 1800kHz -66dB 600 ~ 1800kHz -60dB Output RF 5 1800 ~ 3000kHz -69dB 1800 ~ 6000kHz -60dB Spectrum 3000 ~ 6000kHz -71dB ≥6000kHz -73dB ≥6000kHz -77dB 400kHz -19dB 400kHz -22dB Due to 600kHz -21dB 600kHz -24dB Switching 1200kHz -21dB 1200kHz -24dB transient 1800kHz -24dB 1800kHz -27dB
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No Item GSM DCS/PCS Frequency offset 800kHz Intermodulation product should 7 Intermodulation attenuation – be Less than 55dB below the level of Wanted signal Power control Power Tolerance Power control Power Tolerance Level (dBm) (dB) Level (dBm) (dB) 533±3030±3 631±3128±3 729±3226±3 827±3324±3 925±3422±3 10 23 ±3 5 20 ±3 8 Transmitter Output Power 11 21 ±3 6 18 ±3 12 19 ±3 7 16 ±3 13 17 ±3 8 14 ±3 14 15 ±3 9 12 ±4 15 13 ±3 10 10 ±4 16 11 ±5 11 8 ±4 17 9 ±5 12 6 ±4
18 7 ±5 13 4 ±4 19 5 ±5 14 2 ±5 15 0 ±5 9 Burst timing Mask IN Mask IN
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2) Transmitter-WCDMA Mode
No Item Specification Class3: +24dBm(+1/-3dB) 1 Maximum Output Power Class4: +21dBm(±2dB) 2 Frequency Error ±0.1ppm 3 Open Loop Power control in uplink ±9dB@normal, ±12dB@extreme Adjust output(TPC command) cmd 1dB 2dB 3dB +1 +0.5/1.5 +1/3 +1.5/4.5 4 Inner Loop Power control in uplink 0 -0.5/+0.5 -0.5/+0.5 -0.5/+0.5 -1 -0.5/-1.5 -1/-3 -1.5/-4.5 group(10equal command group)
+1 +8/+12 +16/+24 5 Minimum Output Power -50dBm(3.84MHz) Qin/Qout:DPCCH quality levels 6 Out-of-synchronization handling of output power Toff@DPCCH/lor:-22->-28dB Ton@DPCCH/lor:-24->-18dB 7 Transmit OFF Power -56dBm(3.84M) ±25us 8 Transmit ON/OFF Time Mask PRACH, CPCH, uplink compressed mode ±25us power varies according to the data rate 9 Change of TFC DTX: DPCH off (minimize interference between UE) 10 Power setting in uplink compressed ±3dB(after 14slots transmission gap) 11 Occupied Bandwidth(OBW) 5MHz(99%) -35-15*(∆f-2.5)dBc@∆f=2.5~3.5MHz, 30k -35-1*(∆f-3.5)dBc@∆f=3.5~7.5MHz, 1M 12 Spectrum emission Mask -39-10*(∆f-7.5)dBc@∆f=7.5~8.5MHz, 1M -49 dBc@∆f=8.5~12.5MHz, 1M
- 14 - 2. PERFORMANCE
No Item Specification 33dB@5MHz, ACP>-50dBm 13 Adjacent Channel Leakage Ratio(ACLR) 43dB@10MHz, ACP>-50dBm -36dBm@f=9~150KHz, 1k BW -36dBm@f=150KHz~30MHz, 10k -36dBm@f=30~1000MHz, 100k Spurious Emissions -30dBm@f=1~12.75GHz, 1M 14 *: additional requirement -41dBm*@1893.5~1919.6MHz, 300k -67dBm*@925~935MHz, 100k -79dBm*@935~960MHz, 100k -71dBm*@1805~1880MHz, 100k -31dBc@5MHz, Interferer -40dBc 15 Transmit Intermodulation -41dBc@10MHz, Interferer -40dBc 17.5% (>-20dBm) 16 Error Vector Magnitude(EVM) (@12.2k, 1DPDCH+1DPCCH) -15dB@SF=4, 768kbps, multi-code 17 Transmit OFF Power transmission
3)Receiver - GSM Mode
No Item GSM DCS/PCS 1 Sensitivity (TCH/FS Class II) -105dBm -105dBm Co-Channel Rejection 2 C/Ic=7dB C/Ic=7dB (TCH/FS Class II, RBER, TUhigh/FH) 3 Adjacent Channel 200kHz C/Ia1=-12dB C/Ia1=-12dB Rejection 400kHz C/Ia2=-44dB C/Ia2=-44dB Wanted Signal: -98dBm Wanted Signal: -96dBm 4 Intermodulation Rejection 1’st interferer: -44dBm 1’st interferer: -44dBm 2’st interferer: -45dBm 2’st interferer: -44dBm Blocking Response Wanted Signal: -101dBm Wanted Signal: -101dBm 5 (TCH/FS Class II, RBER) Unwanted Signal: Depend on freq. Unwanted Signal: Depend on freq.
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4) Receiver - WCDMA Mode
No Item Specification 18 Reference Sensivitivity Level -106.7dBm(3.84M) -25dBm(3.84MHz) 19 Maximum Input Level -44dBm/3.84MHz(DPCH_Ec) UE@+20dBm output power(class3) 33dB 20 Adjacent Channel Selectivity(ACS) UE@+20dBm output power(class3) -56dBm/3.84MHz@10MHz
21 In-band Blocking UE@+20dBm output power(class3) -44dBm/3.84MHz@15MHz UE@+20dBm output power(class3) -44dBm/3.84MHz@f=2050~2095 & 2185~2230MHz, band a) UE@+20dBm output power(class3) -30dBm/3.84MHz@f=2025~2050 & 22 Out-band Blocking 2230~2255MHz, band a) UE@+20dBm output power(class3) -15dBm/3.84MHz@f=1~2025 & 2255~12500MHz, band a) UE@+20dBm output power(class3) -44dBm CW 23 Spurious Response UE@+20dBm output power(class3) -46dBm CW@10MHz & 24 Intermodulation Characteristic -46dBm/3.84MHz@20MHz UE@+20dBm output power(class3) -57dBm@f=9KHz~1GHz, 100k BW 25 Spurious Emissions -47dBm@f=1~12.75GHz, 1M -60dBm@f=1920~1980MHz, 3.84MHz -60dBm@f=2110~2170MHz, 3.84MHz
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5) Bluetooth Mode
5.1) Transmitter
1 Out Power Class 2 : -6~4dBm 2 Power Density Power density < 20dBm per 100kHz EIRP
Option 3 Power Control 2dB ≤ step size ≤ 8dB
TX Output Spectrum fmax & fmin @ below the level of -30dBm(100khz BW) 4 -Frequency range within 2.4GHz~2.4835GHz
TX Output Spectrum 5 ≤ 1MHz -20dB Bandwidth
Tx Output Spectrum ≤ -20dBm @ C/I = 2MHz 6 -Adjacent channel Po ≤ -40dBm @ C/I ≥ 3MHz 140kHz ≤ delta f1 avg ≤175kHz 7 Modulation Characteristics delta f2max ≥115kHz at least 99.9% of all deltaf2max delta f2avg/deata f1avg≥0.8 8 Init. Carrier Freq. Tolerance ≤ ±75KHz 1 slot : ≤ ± 25kHz 3 slot : ≤ ± 40kHz 9 Carrier Frequency Drift 5 slot : ≤ ± 40kHz
Maximum drift rate ≤ 20KHz/50usec Freq.Range Operating Standby
30MHz~1GHz -36dBm -57dBm 10 Out of Band Spurious Emissions Above 1GHz~12.75GHz -30dBm -47dBm 1.8~1.9GHz -47dBm -47dBm 5.15~5.3GHz -47dBm -47dBm
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5.2) Receiver
11 Sensitivity single slot packets BER≤0.1%@-70dBm 12 Sensitivity multi slot packets BER≤0.1%@-70dBm 13 BER ≤ 0.1%@ (Low,Mid,High Frequency) 2405MHz, 2441MHz, 2477MHz Interference Ratio Co-Channel interference, C/I co-channel 11dB C/I performance Adjacent(1MHz)interference, C/I 1MHz 0dB Adjacent(2MHz)interference, C/I 2MHz -30dB Adjacent(≥3MHz)interference, C/I ≥3MHz -40dB Adjacent(≥3MHz)interference to in band -9dB mirror frequency, C/I image ±1MHz -20dB 14 BER ≤ 0.1%@wanted signal -67dBm interfering Signal Frequency Power Level
30MHz~2000MHz -10dBm Blocking Characteristic 2000MHz~2400MHz -27dBm
2500MHz~3000MHz -27dBm 3000MHz~12.75GHz -10dBm 15 BER ≤ 0.1%@wanted signal -64dBm Intermodluation Performance static sinwave signal at f1=-39dBm
a BT modulated signal f2=-39dBm(payload PRBS15) 16 Maximum Input Level BER ≤ 0.1%@-20dBm
- 18 - 2. PERFORMANCE
2.4 Current Consumption
(VT test : Speaker off, LCD backlight On)
Stand by Voice Call VT WCDMA 165Hours=8.48mA 180Min=467mA 130Min=646mA (DRX=1.28) (Tx=12dBm) (Tx=12dBm) GSM 223Hours=6.28mA 220Min=380mA (paging=9period) (Tx=Max)
2.5 RSSI
TBD
GSM WCDMA(TBD) BAR 4 → 3 -91 ±2dBm -87 ±2dBm BAR 3 → 2 -96 ±2dBm -97 ±2dBm BAR 2 → 1 -101 ±2dBm -107 ±2dBm BAR 1 → 0 -106 ±2dBm -112 ±2dBm
2.6 Battery Bar
Indication Voltage BAR 4 → 3 (65%) 3.87 ± 0.05V BAR 3 → 2 (43%) 3.77 ± 0.05V BAR 2 → 1 (24%) 3.72 ±0.05V BAR 1 → Icon Blinking (3%) 3.54 ±0.05V 3.54 ±0.03V(Talk: 1min. interval) -3% Low voltage, warning message 3.50 ±0.03V(Standby: 3min. Inverval) -2% 3.15 ±0.03V ↓ (WCDMA Talk) Power OFF 3.23 ±0.03V ↓ (else)
- 19 - 2. PERFORMANCE
2.7 Sound Pressure Level
No Test Item Specification NOM 1 Sending Loudness Rating (SLR) 8±3dB MAX NOM -1±3dB 2 Receiving Loudness Rating (RLR) MAX -15±3dB NOM 3 Side Tone Masking Rating (STMR) 17dB over MAX NOM 4 Echo Loss (EL) MS 40dB over MAX 5 Sending Distortion (SD) refer to TABLE 30.3 6 Receiving Distortion (RD) refer to TABLE 30.4 NOM 7 Idle Noise-Sending (INS) -64dBm0p under MAX NOM -47dBPA under 8 Idle Noise-Receiving (INR) MAX -36dBPA under A NOM 9 Sending Loudness Rating (SLR) 8±3dB C MAX O NOM -1±3dB 10 Receiving Loudness Rating (RLR) U MAX -12±3dB S NOM 11 Side Tone Masking Rating (STMR) 25dB over T MAX I HEAD NOM 12 Echo Loss (EL) 40dB over C SET MAX 13 Sending Distortion (SD) refer to TABLE 30.3 14 Receiving Distortion (RD) refer to TABLE 30.4 NOM 15 Idle Noise-Sending (INS) -55dBm0p under MAX NOM -45dBPA under 16 Idle Noise-Receiving (INR) MAX -40dBPA under TDMA NOISE SEND GSM –.GSM: Power Level: 5 REV. MS DCS: Power Level: 0 SEND DCS (Cell Power: -90 ~ -105dBm) REV. 17 -62dBm under –.Acoustic(Max Vol.) SEND GSM MS/HEADSET SLR: 8±3dB REV. Headset MS/HEADSET RLR: -13±1dB/-15dB SEND DCS (SLR/RLR: mid-Value Setting) REV.
- 20 - 2. PERFORMANCE
2.8 Charging
• Normal mode: Complete Voltage: 4.2V Charging Current: 800mA
• Await mode: In case of During a Call, should be kept 3.9V (GSM: It should be kept 3.9V in all power level WCDMA: It will not be kept 3.9V in some power level)
• Extend await mode: At Charging prohibited temperature(-20C under or 60C over) (GSM: It should be kept 3.7V in all power level WCDMA: It will not be kept 3.7V in some power level)
- 21 - 3. Technical Brief
3. Technical Brief
3.1 Digital Baseband(DBB) & Multimedia Processor
3.1.1 General Description A. Features • CPU ARM946 running at 104 MHz - 32 kB Instruction Cache, 16 kB Data Cache, 128 kB Instruction TCM and 128 kB Data TCM - 8 channel DMAC • DSP C55x (LEAD3) Megastar (MGS3_2.0B) running at 170 MHz - 144 kWord ROM, 32 kWord DARAM, 32 kWord SARAM - 7 channel DMAC - Dedicated API channel to DSP memory (not locked up to other DMA channels) • UMTS Access - Support for WCDMA/GSM Dual Mode - GSM/GPRS network signaling (from Layer 1 to 3) - WCDMA Ciphering and Integrity - High Speed Serial Link (HSSL) to the WCDMA Modem (at Layer 1) - GSM AMR - Multislot Class 8 - HSCSD 14.4 kb/s • MMI - Keypad Interface - Tone Generator Interface - Camera Data and Programmable Display Interfaces - Enhanced graphics support for QCIF display • Operation and Services - I2 CTM‚ Interface - SIM Interfaces - General Purpose I/O (GPIO) Interface - External Memory Interface that supports FLASH, SRAM and PSRAM - JTAG - RTC • Data Communication - IrDA ® (SIR) - UARTs (ACB, EDB (RS232), Bluetooth® HCI) - Slave USB • Package - 12 by 12 mm 289 pin FPBGA Production Package
- 22 - 3. Technical Brief
3.1.2 Hardware Architecture The hardware structure is delivered as five separate hardware macros to the top-level design, also depicted in Figure.
GAM Subsystem CPU Subsystem
Peripheral Subsystem
GSM Core Subsystem
DPS Subsystem SYSCON
Figure 3-1-1 Simplified Block Diagram of Ericsson DB 2000
- 23 - 3. Technical Brief
A. Block Diagram
59 CPU Sub-Chip GAM Sub-System 23 946 CPU Sub-System ETM PDID [7:0] AHB data data Slave GRAPHCON PDI Instruction ETM IF Data Boot ROM PDIC [4:0]
SRAM RAM 16k bytes PAR/ SSI PDIRES_N
128kB 128kB (4K x 32bit) Display Module RAM Control System GRAM cpu BRAM 160k byte CID [7:0]
AHB 16k bytes CIPCLK IPU DPU Slave AHB (4K x 32bit) CIVSYNC 8 JTAG ARM9E GAMCON CDI Slave JTAG CIHSYNC I Cache D Cache AHB CIRES_N Control Control AHB AHB Module Camera Slave DMA Default CP15 Slave Slave (16Rq 8Ch) Slave 26 I Cache D Cache key ADD [24] 32kB 16kB unused 2 Write Buffer & AHB IF AHB AHB DAT [16] Master Slave AHB Master CS [4]
EMIFS Conceptual Diagram of bus MUX MUX MUX MUX
MUX AHB-Lite
External Memory we/oe [2] AHB1 (CPU) AHB-Lite AHB2 (DMA) MEME[5] MUX MUX Interconnect Matrix MUX MUX
16 AHB Bridge AHB APB Bridge AHB APB Bridge AHB APB Bridge AHB APB Bridge AHB AHB Slave Asynchronous Slave (Slow) Slave (Data) Slave (1) Slave (2) Slave Slave
32 4 16 4 3 UL 5 7kB RAM HSSL TS USB 3 43x16 bit RAM 16 43x16 bit RAM RTC UL 13MHz 13MHz RXIF 32 16 11 Integrity KEYPAD 3 16 2 16 360x38bit RAM I2C MMC
RAM 32 32 1 I Ciphering INTCON 3 FCHDET 16 16 MEM 13MHz, 26MHz 13MHz, 13MHz TONGEN STICK 144 bit 32 4 16 GAM CRYPTO UL MPPCM UART5 4 16 kB dual port SRAM dual port 16 kB 16 3 16 UART1 (Internal radio radio (Internal data RAM) SIMIF_0 EDB Control DL 32 16 4 Control CPU I/O interface DL DSP_INT UART4 4 EQU 16 3 16 UART3 UL SIMIF_1 BT 8 4 Peripheral Sub-System Peripheral 6.5 Mbps 16 UART2 GAM 16 UL GPIO 40 GPS UART6
DL 16 (16)
NODI RHEA MUX 16 UART0 4 API 32 3 UL ACB IRDA 4 x CHD DL 32 GPIO MUX DMA Channels
MEMSYS (DMA bus) (DMA MEMSYS TIMER 28 GPRS UL 89 DL CRYPTO 32 6 eight bit wide multiplexedbus, JOGDIAL GPRS DL 0 RHEA CRC24 32 ETX MGS3_2.0B DL MGS3 UL 53 CHE API RHEA peripherals DARAM SARAM DL 16 GPIO MUX 4 32 kWords 32 kWords DL SYSCON DMA (8 x 4kW) (8 x 4kW) UART7 DIRMOD BRE BRE DSP debug 16 SYSCLK [3] 13 208 16 APLL DPLL DGPIO RESOUT [5] 16 CLKCON GSM Sub-System Timer1 MCLK BPW 26 CLK HPRTD ROM 16 7 CLKREQ APLL SQR C55x CPU 16 DPLL SERCON 144 kWords Timer2 PWRREQ_N TRACE (18 x 8 kW) BX 11 SERVICE 48 JTAG TIMGEN APLL RESPOW_N DSP Sub-System 25 13
Figure 3-1-2 Detailed Block Diagram of Ericsson DB 2000
- 24 - 3. Technical Brief
B. CPU Hardware Subsystem
The CPU subsystem incorporates: • CPU Sub chip • Backplane • JTAG • DMA Controller • System Buffer RAM • Boot ROM • External Memory Interface (EMIF) for connection to external SRAM and Flash memories. The bus architecture is built on the ARM AMBA standard with multi-layer AHB (Advanced High-speed Bus) and APB (Advanced Peripheral Bus) for the peripheral buses. There are two AHB busses, the CPU AHB and the DMA AHB. Clocks to the CPU subsystem are distributed from the system control (SYSCON) backplane clocking. The reset lines are all asynchronously asserted low and synchronously negated high. The CPU subsystem has separate clocking and reset for the ARM946, AHB system, EMIF and DMAC.
C. Peripheral Hardware Subsystem
There are 29 peripherals within the peripheral hardware subsystem. With the exception of the USB, all hardware peripheral blocks are APB slave peripherals. From an architecturehierarchy perspective, the SYSCON block is an APB slave on the slow APB bridge, but resides at the top level of the ASIC. The APB provides a simple interface to support low-performance peripherals. Within the peripheral subsystem, there are four separate APB busses with AHB to APB (AHB2APB) bridges to the multi- layer AHB.
D. DSP Hardware Subsystem
The DSP subsystem provides support for processor intensive activity, such as voice coding and multimedia application support. The DSP subsystem includes the standard C55xTM Core (LEAD3) from Texas Instruments with associated memory system and peripherals.
E. GAM Hardware Subsystem
The Graphics Accelerator Module (GAM) subsystem provides hardware support in the creation of visual imagery and the transfer of this data to the display. GAM also provides support for the camera module. The visual data could be graphics, still images or video. The GAM subsystem consists of five modules: • GRAM - graphics memory (160 kB). • GAMCON - GAM controller. • GRAPHCON - graphics controller. • PDI/SSI - programmable display interface for parallel/serial displays. • CDI - camera data interface.
- 25 - 3. Technical Brief
F. GSM Hardware Subsystem
The GSM subsystem is a stand-alone sub-chip incorporating GSM modem and interface to GSM radio together with memory control (MEMSYS) and internal RAM (IRAM). The hardware peripheral blocks are RXIF, FCHDET, CRYPTO, EQU, NODI, 4 x CHD, GPRS CRYPTO, GPRS CRC24, CHE, DIRMOD, CLKCON, SERCON, TIMGEN, MEMSYS and IRAM. The peripherals are accessible to the AHB (CPU-only) by an asynchronous I/O bridge. The dual port IRAM is accessible to the AHB (CPU and DMA) by a synchronous AHB slave interface.
G. System Control Subsystem
The system controller subsystem (SYSCON) is primarily responsible for generating clock signals and distributing the clock and reset signals within the ASIC and certain external devices. The GSM core, GAM and DSP subsystems include their own system controllers that are sourced from SYSCON. SYSCON consists of analog and digital PLL clocks and a clock squarer. The block is a slave peripheral on the slow APB bus under control of the CPU. The programming of SYSCON controls the fundamental modes of operation within the ASIC. Individual blocks can also be reset and their clocks held inactive by accessing the appropriate control registers. SYSCON also controls the requesting protocol through which different subblocks in Ericsson DB 20000 can request clocks derived from the system clock. The system controller also stores the chip-ID number in a read only register.
- 26 - 3. Technical Brief
3.1.3 External memory interface There are four independent chip selects (CS0, CS1, CS2, CS3) provided for external memories and each has an address range of 256 Mb. RF calibration data, Audio parameters and battery calibration data etc are stored in flash memory area.
A. U8550 • 1-MCP used (512Mb flash memory + 128Mb PSRAM) • 4-CS (Chip Select) are used
Interface Spec. Read Access Time Write Device Part Name Maker Access Async Page Burst Time 14 ns Flash 85 ns 25 ns 90 ns at 54MHz RD38F4455LLYBQ1 Intel 10 ns PSRAM 85 ns 25 ns 85 ns at 66MHz
Table 3-1-1. External Memory Interface Spec. of U8550
Flash CS0 256 Mb (Top boot)
Flash CS1 256 Mb (Bottom boot)
PSRAM CS2 64 Mb
CS3 PSRAM 64 Mb
MARITA Intel MCP
Figure 3-1-3. External Memory Configuration of U8550
- 27 - 3. Technical Brief
3.1.4 RF Interface
A. MARITA Interface Marita controls GSM RF part using these signals through GSM RF chip-Ingela. • RFCLK, RFDAT, RFSTR : Control signals for Ingela • TXON, RXON : Control signals for TX and RX part of Ingela • PCTL : Control signal for GSM TX PAM • BANDSEL0 : Band selection signal for GSM or DCS • ANTSW[0:3] : Control signals for antenna switch • DCLK, IDATA, QDATA : GSM/DCS RX Data • DIRMOD[A:D] : GSM/DCS TX Data
RF I/F MODA MODB MODC MODD TXON RXON RADCLK RADSTR RADDAT BSEL0 GPRFCTRL ANTSW0 ANTSW1 ANTSW2 ANTSW3 PCTL DCLK IDATA QDATA 0 R632 NA R631 100 R627 E2 J7 F3 F2 K4 H4 H3 K7 J2 J4 J3 J1 K3 G3 L7 G2 K8 G1 L8 PCTL DCLK TXON RXON IDATA RFSTR RFCLK RFDAT QDATA ANTSW0 ANTSW1 ANTSW2 ANTSW3 DIRMOD0 DIRMOD1 DIRMOD2 DIRMOD3 BANDSEL0 BANDSEL1
Figure 3-1-4. Schematic of MARITA RF Interface
- 28 - 3. Technical Brief
B. WANDA Interface Wanda controls WCDMA RF part using these signals through W-CDMA RF chip-Wopy & Wivi. • WCLK, WDAT, WSTR : Control signals for Wivi & Wopy • RXIA, RXIB, RXQA, RXQB : WCDMA RX Data • TXIA, TXIB, TXQA, TXQB : WCDMA TX Data • HSSLRX_D, HSSLRX_CLK : Marita & Wanda Communication Signal • HSSLTX_D, HSSLTX_CLK : Marita & Wanda Communication Signal
VDIG VCORE 47p C726 2.7K 3.3K R745 R744
Q702 PMST3904 2
WSTR 3 1 R746
NA G16 JTAG_TRSTN G17 JTAG_TCK VCORE G15 JTAG_TMS F16 JTAG_TDI G13 JTAG_TDO E15 EMU1 F13 EMU0
R749R748 100K 100K R17 RADIO_CLK WCLK P15 RADIO_DAT WDAT M13 RADIO_STR R10 ADC_I_IN RXIA N10 ADC_I_IN_INV RXIB R9 ADC_Q_IN RXQA T9 ADC_Q_IN_INV RXQB T10 ADC_RXEXTREF_P N9 ADC_RXEXTREF_N C730 0.1uM16 ADCSTR AD_STR N8 DAC_I_OUT TXIA U8 DAC_I_OUT_INV TXIB U7 DAC_Q_OUT TXQA R7 DAC_Q_OUT_INV TXQB T7 DAC_TXEXTRES B16 HSSLRX_D HSSLTX A16 HSSLTX_CLK HSSLRXCLK A15 HSSLTX_D HSSLRX C14 HSSLTXCLK HSSLRX_CLK D4 ID_BALL A13 IS_SYNC_N ISSYNCn B12 IS_EVENT_N ISEVENTn U12 APLL_ATEST1
Figure 3-1-5. Schematic of WANDA RF Interface
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3.1.5 SIM Interface SIM interface scheme is shown in Figure 3-1-6 SIMDAT0, SIMCLK0, SIMRST0 ports are used to communicate DBB(MARITA) with ABB(VINCENNE) and filter.
SIM (Interface between DBB and ABB) SIMDATO SIM card bidirectional data line SIMCLKO SIM card reference clock SIMRSTO SIM card async/sync reset
Table 3-1-2. SIM Interface
MARITA SIMVCC VDIG VINCENNE 15K 10K VDD SIMDAT0 SDAT SIMDAT DAT SIMCLK0 SCLK SIMCLK CLK CARD SIMRST0 SRST SIMRST RST
Figure 3-1-6. SIM Interface Scheme
- 30 - 3. Technical Brief
3.1.6 UART Interface UART signals are connected to MARITA GPIO through IO connector and Bluetooth interface.
UART0 Resource Name Note GPIO10 UARTRX0 Receive Data GPIO11 UARTTX0 Transmit Data UART3 for the bluetooth GPIO24 UARTRX3 Receive Data GPIO25 UARTTX3 Transmit Data GPIO26 UARTCTS3 Clear To Send GPIO27 UARTRTS3 Request To Send
Table 3-1-3. UART Interface
- 31 - 3. Technical Brief
3.1.7 GPIO (General Purpose Input/Output) map In total 40 allowable resources. This model is using 22 resources. GPIO Map, describing application, I/O state, and enable level are shown in below table 3-1-4.
IO # Application IO Resource Inactive State Active State GPIO00 VGA_IO_OFF O GPIO Low High GPIO01 I2C_VGA_EN O GPIO Low High GPIO02 CAM28_VGA_EN O GPIO Low High GPIO03 PULSESKIP (Not used) - - - - GPIO04 Not used - - - - GPIO05 CIRES_N_MEGA O GPIO High Low GPIO06 HS_AMP_EN O GPIO Low High GPIO07 Not used - - - - GPIO10 UARTRX0 I UART0 High Low GPIO11 UARTTX0 O UART0 High Low GPIO12 AUDIO_AMP_EN O GPIO Low High GPIO13 HS_SPK_SEL O GPIO Low(Headest) High(Speaker) GPIO14 Not used - - - - GPIO15 Not used - - - - GPIO16 Not used - - - - GPIO17 I2C_MEGA_EN O GPIO Low High GPIO20 CAM28_EN O GPIO Low High GPIO21 Not used - - - - GPIO22 3D_OFF O GPIO Low High GPIO23 Not used - - - - GPIO24 UARTRX3 I UART3 High Low GPIO25 UARTTX3 O UART3 High Low GPIO26 UARTCTS3 I UART3 - - GPIO27 UARTRTS3 O UART3 - - GPIO30 Not used - - - - GPIO31 CAM18_EN O GPIO Low High GPIO32 KEY_LED_ONOFF O GPIO Low High GPIO33 Not used - - - - GPIO34 BTF_REG_EN O GPIO Low High GPIO35 Not used - - - - GPIO36 3D_CTRL2 O GPIO Low High GPIO37 TF_DETECT I GPIO Low High GPIO40 USBSENSE I GPIO Low High GPIO41 3D_CTRL1 O GPIO Low High GPIO42 Not used - - - - GPIO43 FOLDER_DET I GPIO Low(Closed) High(Open) GPIO44 Not used - - - - GPIO45 TP601(Not used) - - - - GPIO46 BL_SLEEP_EN O GPIO Low High GPIO47 Not used - - - -
Table 3-1-4. MARITA GPIO Map Table
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3.1.8 USB The USB block supports the implementation of a "full-speed" device fully compliant to USB 2.0 standard. It provides an interface between the CPU (embedded local host) and the USB wire, and handles USB transactions with minimal CPU intervention. The USB specification allows up to 15 pairs of endpoints. Data for each endpoint is buffered in RAM within the USB block and is read/written from the endpoint FIFO using DMA transfers or FIFO register access. High-speed (high throughput) endpoints can use DMA while slower endpoints can use FIFO register access. The USB block can request up to six DMA channels, three for IN endpoints and three for OUT endpoints.
USB Function Note USBDP USB differential (+) line USBDM USB differential (-) line USBSENSE (GPIO40) USB detection (input) USBPUEN USB Pull-up control VDDUSB Power supply for MARITA USB block
Table 3-1-5. USB Signal Interface of MARITA
USB regulator input voltage is 5V and uses external USB device power through IO Connector. Output voltage is 3.3V and supplies to MARITA USB block. USB is detected by MARITA GPIO40(USBSENES). • VUSB / (10K + 51K) = VUSBSENSE / 51K
N501 C509 100p VUSB ON_OFF BYPASS PWRRSTn 3 4 GND 2 VBUS VIN VOUT 15R514 LP2985IM5X-3.3 10K C510 C508 USBSENSE R513 2.2u 4.7u 1608 1608 51K
3.3V USB Regulator
Figure 3-1-7. Schematic of USB Regulator
- 33 - 3. Technical Brief
J15 USBDP USBDP J20 USBDM USBDM USB H19 USBPUEN USBPUEN
Figure 3-1-8. Schematic of MARITA USB block
VBUS
USBPUEN NUF2221W1T2 USBDM D2 D3 34 GND 3_3V 2 5 USBDP D1 D4 1 6 L701 USB FILTER
Figure 3-1-9. Schematic of USB filter
- 34 - 3. Technical Brief
3.1.9 Folder ON/OFF Detection There is a magnet to detect the folder status, opened or closed. If a magnet is close to the hall-effect switch(U1 on Keypad), the voltage at Pin 1 of U1 goes to 0V. Otherwise 2.8V. This folder signal is delivered to MARITA GPIO43(FOLDER_DET).
VDIG
R1 100K FOLDER_DET
A3212EEH-T U1 6 1 VDD OUTPUT 5 2 NC2 NC1 4 C2 GND2 C1 7 3 0.1u PGND GND1 10p
Folder Detect
Figure 3-1-10. Folder ON/OFF Detector
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3.1.10 Bluetooth Interface U8550 supports Bluetooth operation using Philips’ BGB202/S2 Bluetooth module. A. General Description The Bluetooth interface utilizes the UART interface for control signals going to and from the Bluetooth module. The UART is also used for data transmissions. It uses the PCM interface for transmitting audio to and from the Bluetooth module. The Bluetooth module uses both the 13 MHz master clock signal and the 32,768 kHz low-frequency clock signal for internal timing within the Bluetooth module. The intention is to use the low-frequency clock as a low-power timing provider and to use the 13 MHz as a high precision timing reference used mainly by the Bluetooth radio during operation. The clock request mechanism is used to minimize current consumption for the total system. The intention is to use the CLKREQ signal to ask for the master clock when needed, for example, when the Bluetooth radio is operating. B. UART Interface The UART interface is a standard interface and it includes the handshake signals RTS and CTS. The following speeds can be achieved: 9600, 19200, 38400, 57600, 115200, 230400, 460800, 921600, and 1843200 bauds/s. C. PCM Interface The PCM interface is used to send audio to and from the Bluetooth module. The interface is a synchronous interface using a PCM clock and a PCM sync signal for synchronization. Two data signals are used for data, one in each direction. The PCM clock signal operates at frequencies as high as 1 MHz. The word length of the audio data can be 8 or 16 bits. Furthermore, the PCM interface has a function known as MP-PCM, which is an addressing scheme, used to have more than two devices talking on the bus. To add this function, the data pins have to be bi-directional. Additionally, the position of the audio data relative to the frame sync pulse must be selectable. During the periods within a frame that a device is not transmitting audio data, it must put both PCM data signals in a high- impedance state to allow other devices access.
D. Master Clock and Clock Request Interface The master clock (MCLK) is a 13 MHz signal used as the high precision clock signal for the Bluetooth module. The signal can be switched on and off by the platform. The master clock request (CLKREQ) is used by the Bluetooth module to ask for the master clock. If the Bluetooth module asserts the signal high, it gets the master clock. The other alternative for the Bluetooth module is to set the clock request output to high impedance state, indicating that it does not need the master clock. The Bluetooth module receives the master clock, if other parts of the chipset request it. E. Low Frequency Clock Interface The low-frequency clock signal (RTCCLK) is used by the Bluetooth module as a low-power clock. The clock is used in different Bluetooth modes, like sniff and park, to have a correct timing on the Bluetooth air interface without having the master clock running. The low-frequency clock is always present, in some applications even when the chipset is powered down.
- 36 - 3. Technical Brief
F. BGB202/S2 • General - Full module (BB+RF) : Only need to external antenna and reference clock - Bluetooth Specification version 1.1 - Dimensions : 7 x 8 x 1.3 mm - Power class 2 : 10m • Radio Part - Fully integrated near-zero-IF receiver with high sensitivity (typical -82dBm) - Advanced DC offset compensation for improved reception quality - RSSI with high dynamic range - Programmable output pre-amplifier - Fully integrated low phase noise VCO operating in the 5 GHz frequency range - Internal shielding for better EMI (Electro Magnetic Interference) immunity. • Baseband Part - Embedded ARM7TDMI microprocessor - 224 kBytes embedded ROM, 32 kBytes SRAM and 8 kBytes internal RAM (iRAM) for BB controller - Watchdog timer and Two 32-bit system timers - Bluetooth controller including scrambling, CRC generation/checking, FEC encoding/decoding and ciphering according the Specification of the Bluetooth System, Version 1.1 - Bluetooth connections supporting : Maximum 3 active connections (ACL) One voice connection (SCO) - CVSD transcoder - RF interface - RSSI measurement - On-chip 1.8 V voltage regulator - 8-bit D/A and A/D conversion for various purposes, e.g. PA control - Power-on reset - System clock crystal oscillator - Low-power crystal oscillator for a low-frequency clock input - System clock request signal for control of external clock source - Microprocessor interfaces including UART, I2C-bus, combined PCM/IOM® and general purpose I/O-pins - PATCH mechanism for code updates and corrections • Firmware - Interface drivers - Bluetooth controller driver - Link Controller (LC) - Link Manager (LM) - Host Controller Interface (HCI)
- 37 - 3. Technical Brief
G. U8550 Bluetooth Schematic
U604 BGB202_S2 R650 22K 25 15 CLKREQ GPIO10 GP_CLK 30 REF_CLK
R651 0 45 50 RESOUT2n RESET_N TCK_JTAG 47 TMS_JTAG 49 TDI_JTAG 44 48 UARTRTS3 GPIO2_CTS_UART TDO_JTAG 41 UARTCTS3 GPIO3_RTS_UART 43 21 UARTRX3 GPIO4_TXD_UART GPIO0 42 20 UARTTX3 GPIO5_RXD_UART GPIO1 4 6 35 PCMDATB GPIO6_DA_IP C647 22p 2 33 2 1 GND2 GND4 R656 33p L602 33p
PCMSYN GPIO7_FSC_IP ANT IN FEED NC2 36 17 OUT PCMCLK GPIO8_DCLK_IP VANLI NC1
34 22 GND1 GND3 PCMDATA GPIO9_DB_IP VANLO 16 3 5 CN601 L601 27nH ANT601 VBAT C643 100p 29 MCLK XTAL1_SYS MM8430-2600B R652 120K 28 1 XTAL2_SYS GND1 120K 3 GND2 C642 100p 19 4 RTCCLK XTAL1_LPO GND3 18 5 XTAL2_LPO GND4 6 GND5 24 7 GPIO11 GND6 31 8 GPIO12 GND7 23 9 GPIO13 GND8 Bluetooth (BGB202/S2) VBT 32 10 GPIO14 GND9 11 GND10 39 12 VDDIORF GND11 38 13 VDD_IOV GND12 14 GND13 R648 1 27 51 POR_DISABLE GND14 2012 40 52 VREG18 GND15 37 53 VDD18 PGND R649 NA
C646 C640 1_8V_DECOUP1 1_8V_DECOUP2 0.1u 10u 2012 26 46
C641 C645 0.1u 0.1u
Figure 3-1-11. Schematic of Bluetooth module (BGB202/S2)
• Clock - Clock request → Connected to CLKREQ of MARITA and VINCENNE, input to WOPY - Fast clock : 13MHz → Supplied MCLK from WOPY → Frequency deviation : ±10ppm → If level of MCLK is less than 400mVpp, connect to 1.8V through R652(120K) - Slow clock : 32.768kHz → Supplied RTCCLK from MARITA • Power - Supplied 2.85V from external regulator (U510, controlled by GPIO34 of MARITA) → NRESET, UART, PCM, GPIO[2-9] - 1.8V is generated by internal regulator of BGB202/S2 → Baseband core, GPIO[10-14], SysClkReq, JTAG • Reset - RESOUT2n signal of MARITA controls BGB202/S2 reset. • UART - Connected to UART3 of MARITA - HCI interface between MARITA and BGB202/S2 • PCM - Audio signal interface between MARITA/VINCENNE and BGB202/S2 • ANT - 2.4GHz, 50 ohm matching - Antenna switch(CN601) is used for Bluetooth calibration
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3.1.11 TransFlash Interface U8550 supports the TransFlash interface as external memory card. TransFlash has 4-data line, but U8550 uses only 1-data line. All control and data line is connected to MARITA
TransFlash Interface TF_DETECT Card detection, connected to GPIO37 of MARITA TF_CMD Command/Response TF_CLK Clock TF_DAT Data line VTF Supply voltage from 2.85V external regulator(U510)
Table 3-1-6. TransFlash Interface
• Card detection - When there are no card in TransFlash socket, TF_DETECT pin is Low. - If card is inserted in socket, because TransFlash has internal pull-up, TF_DETECT pin changes High. - VTF is always supply power. - If card is removed, TF_DETECT pin changes Low.
VTF 100K 100K S601 500873-0802 GND DAT2_RSV R655 R654 CD_DAT3_CS TF_DETECT CMD_DI TF_CMD VDD CLK_SCLK TF_CLK VSS DAT0_DO TF_DAT DAT1_RSV 1u R653 0.1u GND 470K 1608 C644 C636
Trans-Flash
Figure 3-1-12. TransFlash and Schematic of TransFlash Interface
- 39 - 3. Technical Brief
3.1.12 Power On Sequence ➀ User presses END key and then ONSWAn signal is changed to Low. ➁ VINCENNE initiates the internal oscillator and powers on the regulators. ➂ VINCENNE generates a power for MARITA. ➃ VINCENNE releases the power reset signal(PWRRSTn) and generates an interrupt(IRQ0n) to MARITA.
VIN CENNE MARITA Power for MARITA
Press END key PWRRSTn PWRRST RESPOW_N IRQ0n IRQ IRQ0_N ONSWAn ONSWA
Figure 3-1-13. Power On Sequence
- 40 - 3. Technical Brief
3.1.13 Keypad There are 26 buttons, 3 side keys and 3 MOD keys. ‘END’ key is connected to ONSWAn for Vincenne.
KEYIN0 KEYIN1 KEYIN2 KEYIN3 KEYIN4 KEYOUT0 SIDE1 SIDE2 SIDE3 KEYOUT1 MENU SEARCH MULTI CAM OK KEYOUT2 1 4 7 * UP KEYOUT3 2 5 8 0 DOWN KEYOUT4 3 6 9 # RIGHT KEYOUT5 SEND CLEAR BACK GAME LEFT
Table 3-1-7. Key Matrix Mapping Table
ONSWAn KEYIN0 KEYIN1 KEYIN2 KEYIN3 KEYIN4 SIDE KEY Keypad
SIDE1 CN2 R24 1 2 470 SIDE2 3 R25 4 R27 470 KEYOUT0 SIDE3 470 R28 VA2
END1 470 TVS3 D1 C6 C5 C4
NA NA NA INSTPAR END 1SS388 1*4 7 UP UCLAMP0501H EVL14K02200 VA3 EVL14K02200 EVL14K02200 VA1 1 4 5 STAR1 UP1
KEYOUT2
2 5 8 0 DOWN 2 6 9 10 DOWN1
KEYOUT3
3 6 9 # RIGHT 3 8 7 SHARP1 RIGHT1
KEYOUT4
SEND CLEAR BACK GAME LEFT SEND1 CLEAR1 BACK1 GAME1 LEFT1
KEYOUT5
MENU SEARCH MULTI CAM OK MENU1 SEARCH1 MULTI1 CAM1 OK1
KEYOUT1
Figure 3-1-14. Schematic of Keypad
- 41 - 3. Technical Brief
KEYIN1 KEYIN2 KEYIN3
GND RIGHT CENTER LEFT
Table 3-1-8. MOD Key Matrix Mapping Table
DCIN_3 KEYIN1 KEYIN2 KEYIN3 CPO_LTC_LCDBL
LEFT
CENTER
RIGHT
Figure 3-1-15. Schematic of MOD Keypad
- 42 - 3. Technical Brief
3.2 GAM Hardware Subsystem
GAM
PDID [7:0] Display GRAPHCON PDI/SSI Module PDIC [4:0] control
PDIRES_N
CIRES_N GRAM GAMCON 160k byte CID [7:0] Camera CDI CIPCLK Module CIVSYNC AHB Slave AHB Slave CIHSYNC MUX MUX
AHB2 (DMA)
AHB1 (CPU)
Figure 3-2-1. GAM Subsystem Functional Block Diagram
3.2.1 General Description The Graphics Accelerator Module (GAM) subsystem provides hardware support in the creation of visual imagery and the transfer of this data to the display. GAM also provides support for the camera module. The visual data could be graphics, still images or video. The GAM subsystem consists of five modules: • GRAM : graphics memory (160 kB). • GAMCON : GAM controller. • GRAPHCON : graphics controller. • PDI/SSI : programmable display interface for parallel/serial displays. • CDI : camera data interface.
- 43 - 3. Technical Brief
3.2.2 Block Description
A. GAM Controller(GAMCON) The GAM Controller (GAMCON) is responsible for clock gating and distribution within the GAM module. GAMCON receives the HCLK from SYSCON and distributes to GRAPHCON, GRAM, PDI and CDI. GAMCON also distributes the GAM reset signal to GRAPHCON, GRAM, PDI and CDI. The reset signals CIRES_N and PDIRES_N are distributed from GAMCON to the camera and display module respectively, see Figure 2.28. The CIPCLK is used to clock the received data into the camera data interface. The CIPCLK can be in the range of 100 kHz to 16 MHz.
B. Graphics RAM (GRAM) Block GAM includes 160 kB of graphics memory (GRAM) in order to support display screen sizes of QCIF + alfa display size and three frame buffers when decoding QCIF video. The GRAM can be accessed in 8, 16 or 32-bit mode. Write access takes a single AHB clock cycle. Non-sequential read and the first access of a sequential read access takes two AHB clock cycles. Subsequent sequential read access take a single AHB clock cycle. The GRAM contains both frame buffer and temporary data. There are three image areas with one used for normal MMI graphics and the other two areas used for still images, video frames or camera frames. The three image areas can be combined into one frame buffer. GRAM is required to transfer a VGA (640 by 480 pixels) image from the camera data interface (CDI) over DMA at 100 MBit/s, within a 50 ms timeframe. The GRAM is used as a buffer, but the average transfer bandwidth required is approximately 3 Mword/s (32-bit word), that is 12 MByte/s.
C. Graphics Controller (GRAPHCON) Block GRAPHCON is controlled by the application CPU and can perform operations on pixels and image areas. Images can be moved and merged with other images and text. The GRAPHCON block receives graphical objects from GRAM and performers the appropriate graphical manipulation. The resulting data is transfers to the display interface (PDI). GRAPHCON can receive images from the camera data interface (CDI) and send them to the PDI automatically. GRAPHCON performs conversion from YUV to RGB and can scale (zoom) still or video images.
D. Programmable Display Interface (PDI) Block The programmable display interface (PDI) is designed to interface both parallel and serial display modules. The display data is transferred from the 32 word FIFO on GAMCON to the display module via the PDI block. The PDI block is built around a micro controller and executes 16-bit instruction words to individually control the I/O ports. It has a 128 byte program memory, programmable by the CPU, which can store up to 64 instructions. The CPU transfers all set-up and control data to the display. Data is transferred to PDI as 32-bit words, which in turn writes 8-bit data to the display. The programmable PDI block is configured at the software build stage, to support either parallel interface such as PPI or serial interface such as SSI or I2C.
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E. Camera Data Interface (CDI) Block The camera data interface (CDI) block is designed to support a range of still image camera modules. An 8-bit parallel bus supports data transfer from the camera module to the CDI. The pixel clock is an output clock from the camera module to the CDI and qualifies the data on the parallel bus. One byte of data is captured on each rising edge of the pixel clock. CDI allows the pixel clock to be in the range of 100 kHz to 16 MHz. The horizontal synchronization line is an input from the camera module and defines one scanline of image data. The horizontal synchronization line can be programmed to be active high or low. The vertical synchronization line is an input from the camera module and defines one image frame (image height) of data. The vertical synchronization line can be programmed to be active high or low. The frame rate can be adjusted by skipping frames and various interrupts are used to inform the application CPU regarding the progress of incoming images and potential errors. The normal data format on the data bus is YUV 4:2:2 (raw binary image data) according to the CCIR-656 standard. A function within the CDI can be programmed to reorder the YUV parameters as they pass through the CDI. In addition, the CDI is able to detect the end of an image and perform some truncation as well as overflow conditions. There is nothing preventing the use of other data types such as JPEG or RGB (as long as the timing is followed), but only YUV data can be sent to the display. Camera images can also be sent to a DMA channel to store the image in external memory. The I2C interface and GPIO are part of the interface to the camera module, but they are not part of the CDI block. The I2C is used to set-up and control the camera module. The camera module I2C lines must go high impedance when the supply is removed from the camera. The I2C commands needed to control the camera, as well as the functional behavior of the module, are also different for each implementation. The ON-signal (GPIO) is used to power-on the camera from Standby or Off mode (implementation dependent). This signal must be held low when the mobile equipment is powered down and during the mobile equipment reset period. The GPIO pin can also be an input or high impedance during mobile equipment reset and start. In this case, it must have pull-down to ground. The camera module reset signal is an output to the camera module.
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3.2.3 Camera & Camera FPC Interface
D19 PDIRES_N LCDRESX C19 VCORE VDIG PDIC0 LCDCSX_SUB D18 PDIC1 LCDWRX C20 PDIC2 LCDRS LCD I/F C21 PDIC3 LCDCSX_MAIN E18 R609 PDIC4 LCDRDX R601 B18 2 PDID0 PDID0 D17 VDIG VDIG 4.7K 3.3K PDID1 PDID1 C18 PDID2 PDID2
B19 1 3 PDID3 PDID3 I2CCLK A20 PDID4 PDID4 Q601 H13 R630 R610 PMST3904 PDID5 PDID5 G14 PDID6 PDID6 3.3K 1.2K B20 R611 NA PDID7 PDID7 Y2 I2CSCL I2CCLK_DRIVER W3 I2CSDA I2CDAT H18 CIPCLK CIPCLK H15 CIVSYNC CIVSYNC G21 CIHSYNC CIHSYNC I2C_MEGA_EN E19 CIRES_N CIRES_N_VGA E20 VDIG R602 CID0 CID0 E21 U601 A2 C2 CID1 CID1 A3 C3 100K H14 CID2 CID2 F19 IN2 IN1 VDIG
CID3 CID3 COM2 COM1 F20 B1 B4 CID4 CID4 GND DG3516DB-T5-E1V+ G18 CID5 CID5 G19 NC2 NC1 CID6 CID6 NO2 NO1 C616 G20
VSSA0 VSSA1 VSSA2 CID7 CID7 0.1u A1 C1 A4 C4 R2244 R2245 V14
W13 CAMERA I/F NA NA
I2CDAT_MEGA
I2CCLK_MEGA
I2C_VGA_EN
VDIG R618 U602 A3 C3 A2 C2 100K
IN2 IN1 VDIG COM2 COM1 B1 B4 GND DG3516DB-T5-E1V+
R2242 R2243
NC2 NC1 NO2 NO1 C617 NA NA 0.1u A1 C1 A4 C4 R2246 R2247
NA NA
I2CDAT_VGA
I2CCLK_VGA
Figure 3-2-2. Camera Interface (in Marita) VCAM_2.8V VCAM_1.8V VCAM_2.8V VCAM_2.8V
R715 0 FLASH3 R714 0 FLASH2 R732 0 R729 R728 FLASH1 R731 0 CPO_LTC_FLASH NA CN702 R799 NA G1 G2 10 FB702 1 26 2 25 FL704 10 5 3 24 R726 0 10 5 CIRES_N_MEGA 4 23 G2 G1 G2 G1 5 22 CID0 OUT4 IN4 INOUT_B4 INOUT_A4 I2CCLK_MEGA 6 4 6 21 6 4 CID1 OUT3 IN3 INOUT_B3 INOUT_A3 I2CDAT_MEGA 7 3 7 20 7 3 CID2 OUT2 IN2 INOUT_B2 INOUT_A2 SYSCLK1 8 2 8 19 8 2 CID3 OUT1 IN1 INOUT_B1 INOUT_A1 CIVSYNC 9 1 9 18 9 1 CIHSYNC NFA21SL207X1A45L FL706 10 17 R725 0 ICVE21184E150R101FR 11 16 12 15 13 14 R718 51 CIPCLK
10 5 R713 NA R730 G3 G4 R724 R709 NA G2 G1 C706 C1920 R711 NA CID4 OUT4 IN4 20p NA 6 4 10K R710 NA CID5 OUT3 IN3 10K NA NA 7 3 NA CID6 OUT2 IN2 8 2 CID7 OUT1 IN1 9 1 NFA21SL207X1A45L FL705 C701 NA C704 C702 C703 1.3M CAMERA CONNECTOR VCAM_VGA_2.8V VDIG 0 NA
CN701 R723 R721 51 52 1 50 ICVE21184E150R101FR 2 49 1 9 3 48 SYSCLK1 INOUT_A1 INOUT_B1 2 8 4 47 I2CDAT_VGA INOUT_A2 INOUT_B2 3 7 5 46 I2CCLK_VGA INOUT_A3 INOUT_B3 4 6 6 45 CIVSYNC INOUT_A4 INOUT_B4 7 44
G1 G2 8 43
FL703 5 10 9 42 10 41 IND_SINK 11 40 R702 0 12 39 CIRES_N_VGA 13 38 R722 NA 14 37 R720 NA 15 36 R719 NA 16 35 R712 NA R717 0 17 34 CIHSYNC R716 51 18 33 CIPCLK 19 32 20 31 DCIN_3 21 30 KEYIN1 22 29 KEYIN2 23 28 KEYIN3 R701 0 24 27 CPO_LTC_LCDBL 25 26 53 54
C705 C1919 C707 20p NA NA
LCD, VGA CAMERA CONNECTOR
Figure 3-2-3. Main Board to FPCB Connector(50pin,26pin - Main Board)
- 46 - 3. Technical Brief
EDLM0005801 VCAM_1.8V VCAM_2.8_DVDD VCAM_2.8_AVDD
LD1 CN1
G1 R1 51 26 1 FLASH3 25 2 FLASH2 24 3 CIRES_1.3M FLASH1 23 4 I2C_CLK CPO_LTC_FLASH 22 5 I2C_DAT CID0 21 6 CID1 20 7 SYSCLK CID2 19 8 CIVSYNC CID3 18 9 CIHSYNC CID4 17 10 CID5 16 11 CID6 15 12 CID7 14 13 CIPCLK G2
MAIN-to-FPCB Connector VCAM_1.8V VCAM_2.8_DVDD VCAM_2.8_AVDD
CN2 1 24 2 23 I2C_CLK CID7 3 22 I2C_DAT CID6 4 21 CID5 5 20 CIVSYNC CID4 6 19 CIHSYNC CID3 7 18 SYSCLK CID2 8 17 CID1 9 16 CID0 10 15 CIPCLK 11 14 CIRES_1.3M 12 13
FPCB-to-1.3M Connector
Figure 3-2-4. Main Board to camera FPCB Connector(26pin - FPCB) FPCB to 1.3M camera Connector(24pin - FPCB)
LD2 R3
LEBB-S14H 0 LD1 R4 VCAM_VGA_2.8V VDIG LEBB-S14H 0
CN2 51 52 1 50 2 49 CID0 3 48 CID1 4 47 CID2 5 46 CID3 6 45 CID4 7 44 CID5 8 43 CID6 9 42 CID7 10 41 IND_SINK 11 40 12 39 CIRES_N 13 38 SYSCLK1 14 37 I2C_DAT 15 36 I2C_CLK 16 35 CIVSYNC 17 34 CIHSYNC 18 33 CIPCLK 19 32 20 31 DCIN_3 21 30 KEYIN1 22 29 KEYIN2 23 28 KEYIN3 24 27 CPO_LTC_LCDBL 25 26 53 54
R11 0 AXK8L50125BG LEFT CN3 HEADER 1 20 R12 10 2 19 R10 0 3 18 C4 CENTER 4 17 5 16 6 15 1u 7 14 C5 RIGHT 8 13 9 12 10 11 1u
AXK720145G
VGA Camera Connector
Figure 3-2-5. Main Board to LCD FPCB Connector(50pin - FPCB) FPCB to VGA camera Connector(20pin - FPCB)
- 47 - The 1.3M Camera module is connected to main board(AXK7L26227) with Camera FPCB (AXK8L26125). The VGA Camera module is connected to main board(AXK7L50227) with Camera & LCD FPCB(AXK8L50125). 1.3M Camera module is connected to FPCB with 24-pin Board to Board connector(14-5602-024-000-829 - 1.3M Camera). VGA Camera module is connected to FPCB with 20-pin Board to Board connector(AXK720145 - VGA Camera). Its interface is dedicated camera interface port in Marita. The camera port supply 13MHz master clock to camera module and receive 17MHz pixel clock(15fps), vertical sync signal, horizontal sync signal, reset signal and 8bits YUV data from camera module. The camera module is controlled by I2C port.
NO Pin Name I/O Description 1 GND O Analog Ground 2D7ODigital video data bit[7] 3D6ODigital video data bit[6] 4D5ODigital video data bit[5] 5D4ODigital video data bit[4] 6D3ODigital video data bit[3] 7D2ODigital video data bit[2] 8D1ODigital video data bit[1] 9D0ODigital video data bit[0] 10 PCLK O Clock for output data 11 RESET I Reset 12 STANDBY P Digital Ground 13 DGND P Digital Ground 14 DVDD P Digital Core Voltage(1.8V) 15 DVDD P Digital interface Voltage(2.8V) 16 AVDD P Analog Voltage(2.8V) 17 GND P Interface Ground 18 MCLK I System Clock 19 HREF O Horizental sync signal 20 VSYNC O Vertical sync signal 21 GND P Interface Ground 22 SDA I/O Serial data I/O for 12C bus 23 SCK I/O Clock for output data 24 GND P Analog Ground
Table 3-2-1. Interface between 1.3M Camera Module and FPCB (in FPCB)
NO Pin Name I/O Description 1STANDBY In Stanby mode 2 MCLK In System Clock Input 3 GND Gnd Frame Synchronous Signal 4 PCLK Out Pixel Clock 5D0Out Image data output 6D1Out Image data output 7D2Out Image data output 8D3Out Image data output 9D4Out Image data output 10 D5 Out Image data output 11 D6 Out Image data output 12 D7 Out Image data output 13 VSYNC Out Vertical Synchronization Reference 14 HSYNC Out Horizontal Synchronization Reference 15 GND Gnd Ground 16 SDA In/Out Serial Bus Data 17 SCL In/Out Serial Bus Clock 18 RESET In Reset 19 DVDD 2.8V Power 2.8V Digital Power 20 AVDD 2.8V Power 2.8V Analog Power
Table 3-2-2. Interface between VGA Camera Module and FPCB (in FPCB)
- 48 - 3.2.4 Camera Regulator GPIO_31 enables the 1.8V Camera Regulator for the 1.3M Camera Digital Core. GPIO_20 enables the MEGA_2.8V Camera and GPIO_02 enables the VGA_2.8V Camera Regulator.
VBATI VCAM_1.8V VBATI VCAM_2.8V
R501
U503 U502 R526 0 1 5 0 1 5 VDD VOUT VDD VOUT 2 2 GND R508 GND R527 0 3 4 3 4 CAM28_EN CE NC CAM18_EN CE NC 0 R1114N281D-TR-F C501 R1114N181D-TR-F C504 R528 C522 C523 R507 1u 1u 2.2u 0.47u 100K 1608 100K 1608 1608 1608
MEGA_2.8V Camera Analog Power 1.8V Camera power
Figure 3-2-6. 1.3M 2.8V and 1.8V Camera Regulator
VBATI VCAM_VGA_2.8V
U501 R503 0 1 5 VDD VOUT 2 GND R505 0 3 4 CAM28_VGA_EN CE NC R1114N281D-TR-F R504 C502 C503 1u 0.47u 100K 1608 1608
VGA_2.8V Camera Analog Power
Figure 3-2-7. VGA 2.8V Camera Regulator
- 49 - 3. Technical Brief
3.2.5 Display & LCD FPC Interface LCD module include device in table 3-2-3
Device Type Main LCD 220 X RGB X 220 262K Color TFT LCD Sub LCD 128 X RGB X 160 262K Color TFT LCD Main/Sub LCD Backlight 5 White LEDs (simultaneously)
Table 3-2-3. Devices in LCD Module
The LCD Module is connected to FPCB with the 40-pin Board to Board Connector(AXK8L40125) and Receiver, 2 blue Indicator/backlight LEDs are connected by soldering in the Camera & LCD FPCB. The Main&Sub LCD are controlled by 8-bit PDI(Parallel Data Interface) in Marita. In case of power off mode, if TA is inserted, 2 blue Indicator LEDs are turned-on.
NO Pin Name Pin Type Description Indicator LEDs 20 DCIN_3 O Indicator LEDs Power 10 IND_SINK I Indicator LEDs Ground Receiver Terminal 48 EARM O Receiver Minus 49 EARP O Receiver Plus
Table 3-2-4. Interface between Camera&LCD FPCB and Receiver, Vibrator, Indicator LEDs and Camera Flash LEDs
- 50 - 3. Technical Brief
NO Pin Name Pin Type Description Unused Pin 1 VCC - The Logic Power Supply for LDI and LCM - 2 VCI - The Analogue Power Supply for LDI and LCM - 3 S_RESET I Sub Reset Pin. Initialize the LSI at the low level - 4 M_RESET I Main Reset Pin. Initialize the LSI at the low level - 5 SUB_CS I Sub Chip Select, Active low - 6 D0 I/O Bi-Direction Data Bus GND 7 L D1 I/O Bi-Direction Data Bus GND 8 D2 I/O Bi-Direction Data Bus GND 9 D3 I/O Bi-Direction Data Bus GND 10 D4 I/O Bi-Direction Data Bus GND 11 D5 I/O Bi-Direction Data Bus GND 12 D6 I/O Bi-Direction Data Bus GND 13 D7 I/O Bi-Direction Data Bus GND 14 MLED I Anode of LEDS - 15 MLE1 O Cathode of LED1 - 16 MLE2 O Cathode of LED2 - 17 MLE3 O Cathode of LED3 - 18 MLE4 O Cathode of LED4 - 19 GND - Ground - 20 GND - Ground - 21 MLED5 O Cathode of LED5 - 22 MAIN_IF2 I Main Mode Select2 (See Table 7.1) - 23 SUB_IF2 I Sub Mode Select2 (See Table 7.2) - 24 GND - Ground - 25 BST O Indicate the start of Vertical Blank. OPEN 26 D15 I/O Bi-Direction Data Bus GND 27 D14 I/O Bi-Direction Data Bus GND 28 D13 I/O Bi-Direction Data Bus GND 29 D12 I/O Bi-Direction Data Bus GND 30 D11 I/O Bi-Direction Data Bus GND 31 D10 I/O Bi-Direction Data Bus GND 32 D9 I/O Bi-Direction Data Bus GND 33 D8 I/O Bi-Direction Data Bus GND 34 _WR I Write-Strobe Signal. Active low - 35 MAIN_CS I Main Chip Select, Active low VCC 36 RS I Select Register. High: Control, Low: Index/Status VCC 37 MAIN_IF1 I Main Mode Select1(See Table 7.1) - 38 ID_MAKER - Connected to Ground OPEN 39 SUB_IF1 I Sub Mode Select1(See Table 7.2) - 40 _RD I Read-Strobe Signal. Active low VCC
Table 3-2-5. Interface between LCD module and FPCB(in FPCB)
- 51 - 3. Technical Brief
3.2.6 Main&Sub LCD Backlight Illumination There are 5 white LEDs for the Main LCD and the Sub LCD Backlight circuit which are driven by the Charge Pump(LTC3206EUF). I2C is used for the backlight brightness control. GPIO_46 enables the Charge Pump IC.
VBATI
R739 0 CPO_LTC_FLASH C711 2.2u C708 2.2u R740 0 R738 CPO_LTC_LCDBL 1u 5 4 6 3 1u 1u 1u 1u 0 14 C1- C2- C1+ C2+ CPO C710 C716 15 C715 C714 C713 VIN 22 MAIN1 LCDBL1 21 MAIN2 LCDBL2 7 20 DVCC MAIN3 LCDBL3 19 U701 MAIN4 LCDBL4 23 LTC3206EUF AUX1 LCDBL5 1 SUB1 10 2 BL_SLEEP_EN ENRGB SUB2 24 AUX2 R733 0 8 16 I2CDAT SDA RED FLASH1 9 17 I2CCLK_DRIVER SCL GREEN FLASH2 R737 0 18 I2CCLK BLUE FLASH3 R734 NA PGND SGND IMS IRGB 25 13 11 12
C712 C709
2.2u 2.2u R736 3K R735 12K
LCD BL and Cam Flash Driver LTC3206
Figure 3-2-8. Charge Pump Circuit for Main&Sub LCD Backlight
3.2.7 Camera Flash LED Illumination Camera Flash is composed of one White LED module(LEWW-S35LA with 3 LEDs). The Charge Pump(LTC3206EUF) control similarly the flash LED current respectively.
R739 0 CPO_LTC_FLASH C708 2.2u R740 0 CPO_LTC_LCDBL EDLM0005801 1u 4 6 3 1u 1u 1u 1u
14 C1- C2- C2+ CPO C710 C715 C713 C716 C714
22 MAIN1 LCDBL1 21 LD1 MAIN2 LCDBL2 20 CN1
MAIN3 LCDBL3 R1 51 19 1 U701 MAIN4 LCDBL4 FLASH3 23 2 LTC3206EUF AUX1 LCDBL5 FLASH2 1 3 SUB1 FLASH1 2 4 SUB2 CPO_LTC_FLASH 24 AUX2 16 RED FLASH1 17 GREEN FLASH2 18 BLUE FLASH3
Figure 3-2-9. Camera Flash Figure 3-2-10. Camera Flash Charge Pump Circuit LEDs Circuit (in FPCB)
- 52 - 3. Technical Brief
3.2.8 Keypad Illumination There are 19 blue LEDs in key board backlight circuit, which are driven by GPIO32 (KEY_LED_ONOFF) line form Marita.
R741 2.7K KEY_LED_ONOFF R742
1 2 3 12 Q701 EMX18 R727
12
6 5 4 KEY_LED-
Keypad Backlight Control
Figure 3-2-11. Keypad Backlight Blue LED Interface
VBATI
R32 100K PG05DBTFC LEBB-S14H LEBB-S14H LEBB-S14H LEBB-S14H LEBB-S14H LEBB-S14H LEBB-S14H LEBB-S14H LEBB-S14H LEBB-S14H LEBB-S14H LD5 LD2 LD9 LD8 LD3 LD1 LD6 LD7 LD4 LEBB-S14H LD11 LD12 LD10 LD13
LEBB-S14H R33 100K C3 PG05DBTFC 0.1u R3 R4 R6 R2 R5 150 150 150 150 150 150 150 150 150 150 150 150 150 R30 R26 R14 R23 R15 R29 R31 R34 100K R10
PG05DBTFC KEY_LED-
Figure 3-2-12. Keypad Backlight Circuit
- 53 - 3. Technical Brief
3.3 LCD Module
Ear Piece
40pin BtoB 50pin BtoB Camera&LCD FPCB Main Board LCD Module Connector Connector
20pin BtoB Connector
VGA Camera
Figure 3-3-1. LCD Module Block Diagram
Figure 3-3-2. LCD Module (Main & Sub LCD)
- 54 - 3. Technical Brief
3.4 Analog Baseband (ABB) Processor
3.4.1 Overview of Audio path
MARITA Digital Baseband ASIC
Voice Call RX
Videp Telephony RX VINCENNE MP3 Audio and Power Management ASIC Receiver Tone Generator Audio Mixer
MIDI or WAVE TJATTE2 C-MIC Filter HEADSET AMP Voice Call TX CODEC 3D IC HEADSET Videp Telephony TX Analog S/W Speaker
AUDIO AMP Speaker
Figure 3-4-1. Audio Path Block Diagram
- 55 - 3. Technical Brief
3.4.2 Audio Signal Processing & Interface Audio signal processing is divided Uplink path and downlink path. The uplink path amplifies the audio signal from MIC and converts this analog signal to digital signal and then transmit it to DBB Chip (MARITA). This transmitted signal is reformed to fit in GSM & WCDMA Frame format and delivered to RF Chip. The downlink path amplifies the signal from DBB chip (MARITA) and outputs it to Receiver (or Speaker). The audio interface consists of PCM encoding and decoding circuitry, microphone amplifiers and earphone drivers. The PCM encoder and decoder blocks are two-channel, 16-bit circuits with programmable gain amplifiers (PGA). The decoder has a receive volume control. The audio inputs and outputs can be switched to normal or auxiliary ports.
32 AUXO2 PCM AUXILIARY OUTPUT 1
VOL RX- DAC RX- 16 DECODER BEARP FILTER 2 PGA2 8 /16 kHz 16 BEARN PCMSYN ONE CH. RX- DAC RX- 44/48 kHz EARPHONE PCMI FILTER 1 PGA1 TWO CH. PCMO 32 AUXO1 SIDE TONE AUXILIARY OUTPUT 2 PCMCLK
MIC MIC1P ENCODER TxGC TX- ADC TX- AMP MIC1N 8 /16 kHz FILT 1 PGA1 TWO CH. AUXI1 TX- ADC TX- AUXILIARY INPUT 1 FILT 2 PGA2 MIC MIC2P AMP MIC2N
AUXI2 AUXILIARY INPUT 2
Figure 3-4-2. Audio Interface Detailed Diagram (VINCENNE)
- 56 - 3. Technical Brief
VDIG
B5 DACO1 G11 WDCDCREF L501 BLM15BB750SN1J R510 0 CN502 DACO2 H11 WPAREF EARP 13 DACO3 VCXOCONT L502 R511 0 15 A8 EARM R569 0 17 R571 R2252 TXON C507 G10 TXON C552 470p BLM15BB750SN1J 1 EXPOUT F10 C598 470p C554 1u R566 0 2 NA 10K FF_IN 47p R579 0 3 M4 4 BEARP C555 C566 1 X503 5 L3 10p 6 R2253 BEARN C569 22p 7 JACK_DET C537 47p N504 IP4025CX20-LF U8360-MIC 10K L4 R577 0 2 NA 8 AUXO1 A2 VDIG VBATI 9 MICP C565 C558 C559 L9 R574 620 C585 100u D4 10 CCO AFMS_R_INT 47p R572 620 2527 C1 A1 NA 47p 11 CCO MICN 68 12 M8 C568 0.068u D2 A3 R591 120K MIC1P MICP_INT ATMS 0 R559 0 14 R2131 R2130 R567 L8 22K C567 0.068u D1 A4 C583 NA 16 MIC1N MICN_INT ATMS_CAP 3 4 5 6 1
R2248R2249 68 18 100K C575 D2 D3 D4 D5 M6 R581 0 D3 B4 R584 0 D1 AUXI1 ATMS_INT AFMS_R U508 M7 1u R596 120K C-1827541 MIC2P NLAS4684FCT1 L7 MIC2P C2 A5 GND
C590 SMF05C-TCT
MIC2N ATMS_AD AFMS_L D702 MIC2N R582 0 C586 NA L6 2 AUXI2 B4 10u HOOK C584 100u D5 B5
AFMS_L_INT VDD V+ 2012 K12 R561 0 2527 C2 C4 GPA5 D501 C571 C570 IN1 NO1 C561
J4 C562 B1 C3 AUXO2 68p GND1 GND4 68p U509 LM4809LD
R575 0 B2 C4 A2 A4 7 8 C592 100u C540 GND2 GND5 IN2 NO2 VDD VOUT1
1u 2527 E4 RB521S-30 B3 C5 22p C543 VSSTH31 C581 22p C541 GND3 GND6 F4 NA 0.1u C3 C1 R580 33n R592 120K 1
NA COM1 NC1
VSSTH30 47p 1u C542 VIN1 G4 6 C593 100u VSSTH29 TJATTE2 R587 VOUT2 H4 A3 A1 R583 33n R597 120K 5 2527 VSSTH28 COM2 NC2 VIN2 C1930 J5
VSSTH27 GND 10p C1931 J6 2 3 VSSTH26 C564 BYPASS GND 10p J7 B1 R588 4 9 VSSTH25 _SHDN BGND VBATI J8 C573 1u R585 0 R586 100K 2012 10u VSSTH24 0 C580 H9 1608 C587 3300p HS_SPK_SEL VSSTH23 1u G9 R589 VSSTH22 1608 C1932 F9 C572 1u C589 4700p 100K R564 0 VSSTH21 C1933 10p E9 1608 1608 VSSTH20 10p R576 D8 VBATI VSSTH19 D7 0 R558 0 3 1 VSSTH18 2 4 HS_AMP_EN U505 TPA2005D1ZQYR D6 R539 C528 R537 D1 B4 VSSTH17 R598 R594 IN- VDD1 F7 R578 33n C4 LIN VSSTH1 RIN 0 18K VDD2 C563 LOUT
G7 0 ROUT 4.7K 4.7K B1 VSSTH2 C529 NC 10u G6 16 5 R534 C1 VSSTH3 VREF NFSPR 68p IN+ 2012 E5 15 6 A4 VSSTH4 GND NFHPR 18K VO- SPK_LEFT_M GUIDE HOLE E6 14 7 C526
VSSTH5 V+ U507 NFSPL E7 13 8 A1 D4 VSSTH6 1u STBY NFHPL 33n _SD VO+ SPK_LEFT_P OJ500 OJ501 OJ503 OJ504 OJ505
E8 NJM2705PC1 VSSTH7 C574 C577 F8
VSSTH8 1u GND1 GND2 GND3 GND4 GND5 GND6 GND7 G8 1608 R595 LMON VSSTH9 SW1 SW2 PS R590
H8 A2 A3 B3 C2 C3 D2 D3
VSSTH10 9 8.2K
H7 12 11 10 10K VSSTH11 H6 VSSTH12 H5 R573 0 C582 VSSTH13 3D_OFF G5 R524 1K VSSTH14 3D_CTRL1 4700p F5 R525 1K VSSTH15 3D_CTRL2 U504 TPA2005D1ZQYR D5 R533 C524 R532 D1 B4 VSSTH16 C579 3300p IN- VDD1 33n C4 C517 C519 C578 0 18K VDD2 B1 1u 1u 2700p C525 NC R531 C1 68p IN+ A4 18K VO- SPK_RIGHT_M C560 A1 D4 33n _SD VO+ SPK_RIGHT_P GND1 GND2 GND3 GND4 GND5 GND6 GND7
Engineer: A2 A3 B3 C2 C3 D2 D3 R530 Jeongseok Lee LG ELECTRONICS INC. AUDIO_AMP_EN Drawn by: Mobile Handsets R&D Center 0 HW Group, Development Lab 6. R529 Jeongseok Lee R&D CHK: TITLE: Size: 100K DOC CTRL CHK: U8550-spfy0106301-1.1 12 1 8 A Vincenne, Regulators MFG ENGR CHK: Page 5 of 7(Baseband 1 of 3)
Figure 3-4-3. Schematic of Audio Path
- 57 - 3. Technical Brief
3.4.3 Audio Mode Audio Mode includes three states(Voice call, Midi, MP3) Each states is sorted by the total 7 Modes according to external Devices. (Receiver,Loud Speaker,Headset) Video Telephony Mode Operate on state of the WCDMA Call.
VINCENNE In / Out Port Mode IN OUT Receiver Mode MIC1P/MIC1N BEARP/BEARN Loud Speaker Mode MIC2P/MIC2N AUXO1/AUXO2 Voice call Headset Mode AUXI1 AUXO1/AUXO2 Video Telephony Mode MIC2P/MIC2N AUXO1/AUXO2 MIDI Only Loud Speaker AUXO1/AUXO2 Loud Speaker Mode AUXO1/AUXO2 MP3 Headset Mode AUXO1/AUXO2
Table 3-4-1. Audio Mode
- 58 - 3. Technical Brief
3.4.4 Voice Call
A. Voice call Downlink Mode(Receiver, Speaker, Headset) This section provides a detailed description of the Voice Call RX functions.
Voice Call RX Audio Mixer
FR Speech 65d Decoder
HR Speech SHF Decoder Compressor C D B Speech Coded 65c Acoustic Data from Host Compensation A 4 AMR Speech 64 29 OHF 5 Decoder Compressor 65a
EFR Speech AHF To Linear Echo Canceller in Decoder Compressor Voice Call TX 65b F
Bluetooth Module Tone Generator G E
1
Audio Codec (RX-path)
A 17 AUXO2 30 Auxiliary Output 2 Decoder Volume DAC2 RX PGA2 PCM 44/48 PCM 44/48 27 52 44 45 58 14 BEARN 49 27 Earphone Driver BEARP
22 30 Decoder Volume AUXO1 RX1 HP RX1 LP DAC1 RX PGA1 PCM 8/16 PCM 8/16 Auxiliary Output 1 50 A 36 44 45 58 14 51 16
Sidetone Analog Loop Analog Loop MIC1 to Loop from TX2 from TX1 AUXO1 Loop
Figure 3-4-4. Voice Call Downlink Scheme
- 59 - 3. Technical Brief
The voice decoder accepts a serial input stream of linear PCM coded speech. The receive band-pass filter is the next step in the CODEC receive path. Following the filter is the DAC, followed by a PGA enabling to adjust or trim the circuit in the product for different sensitivity of the earphone and spread in the RX path. The final step in the receive path is the earphone amplifier and the auxiliary output. The auxiliary audio amplifier is intended to drive low impedance headphones. The earphone amplifier and the auxiliary audio outputs can be powered down (muted) via I2C. Both the earphone driver and one of the auxiliary drivers can simultaneously provide an output signal during voice decoding. • Receiver Mode : Earphone amplifier → BEARP/N Port → Receiver(32Ω)
• Loud Speaker / Video Telephony Mode : Auxiliary audio amplifier → AUXO1/2 → SURROUND AUDIO PROCESSOR(NJM2705) → TJATTE2 → Analog S/W(NLAS4684) → AUDIO AMP(TPA2005D1) → Speaker(8Ω)
• Headset Mode : Auxiliary audio amplifier → AUXO1/2 → SURROUND AUDIO PROCESSOR (NJM2705) → TJATTE2 → Analog S/W(NLAS4684) → HEADSET AMP(LM4809LD) → Head Phone Loud Speaker Mode has four GPIO switching control ports. It is 3D_CTRL1/2, HS_SPK_SEL and Audio_AMP_EN. HS_SPK_SEL controls analog switch(NLAS4684) and Audio_AMP_EN controls shutdown of AUDIOAMP(LM4809LD). Video Telephony Mode has same paths with Loud Speaker Mode.
3D IC Mode HS_SPK_SEL AUDIO_AMP_EN 3D_CTRL1 3D_CTRL2
Receiver ------
Headset (amr) Low Low Low Low
Headset (mp3) High Low Low Low
Loud Speaker, VT Low Low High High
3D Speaker (mp3) Low High High High
Table 3-4-2. Speaker Phone Mode GPIO Control State
- 60 - 3. Technical Brief
B. Voice call Uplink Mode(Receiver, Speaker, Headset) This section provides a detailed description of the Voice Call TX functions.
Audio Codec (TX-path) Audio Mixer
53 MIC1 to Analog Sidetone AUXO1 Loop Loop Loop 54 Bluetooth 55 Module MIC1N Microphone Input 1 A C MIC1P 34 Encoder 35 ADC1 TX1 LP TX1 HP TX PGA1 TX GC PCM 8/16 AUXI1 59 1 Auxiliary Input 1 62 44 45 58 B 18 19
MIC2N Microphone Input 2 MIC2P 37 Encoder 38 ADC2 TX2 LP TX2 HP TX PGA2 PCM 8/16 AUXI2 60 63 Auxiliary Input 2 44 45 58 20 21
Voice Call TX
Loudspeaker FR Speech Signal from Encoder Voice Call RX Hard Limiter TX HR Speech Encoder Residual Linear Echo Noise Acoustic Band Pass Soft Limiter Speech Coded Echo Canceller Reduction Compensation Filter TX Controller Data to Host 28 33 40 41 2 3 28 48 D E 56 57 F AMR Speech Encoder
Interdependency EFR Speech Encoder
Figure 3-4-5. Voice Call Uplink Scheme
The Uplink supports two microphones and two auxiliary inputs to the speech encoder blocks. Both microphone inputs are compatible with an electric microphone. The VINCENNE internal voltage source (CCO) provides the necessary drive current for the electric microphone. The voltage source is via I2C programmable to supply 2.2V or 2.4V. But the voltage source of our Model is to supply 2.4V. The auxiliary audio inputs can be used as an alternative source of speech, a source from an external microphone or as an analog loop connection. Figure 3.4.4.2 shows that the audio inputs are fed to the transmit PGAs, which enables to adjust the total gain in the product for different sensitivities of the microphones and spread in the transmit paths. The ADCs are followed by the transmit band pass filters, which accept the maximum output swing that the microphone preamplifiers can deliver without clipping, and maintain a good signal-to-noise ratio. The high pass filter in the TX-paths can be disabled via I2C; still removing the DC offset from the signal. For one of the two transmit paths, a transmit gain control amplifier precedes the final encoding of the PCM output.
- 61 - 3. Technical Brief
3.4.5 MIDI (Ring Tone Play) This section provides a detailed description of the MIDI and WAV-file functions.
Digital Baseband ASIC
VINCENNE MIDI or WAVE Audio Mixer Audio and Power Management ASIC TJATTE2 Filter HEADSET AMP 3D IC HEADSET CODEC
Analog S/W Speaker
AUDIO AMP Speaker
Figure 3-4-6. MIDI Scheme
In Figure 3-4-6, External MIDI path is the same as Voice Loudspeaker downlink Mode, except source in MARITA (DSP and Audio Mixer).
• MIDI : MARITA PCM Decoder → Auxiliary audio amplifier → AUXO1/2 Port → SURROUND AUDIO PROCESSOR(NJM2705) → TJATTE2 → Analog S/W (NLAS4684) → 2 Mono AUDIO AMP(TPA2005D1) → 2 Speaker(8Ω)
- 62 - 3. Technical Brief
3.4.6 MP3 (Audio Player) This section provides a detailed description of the MP3 file functions.
MARITA Digital Baseband ASIC
MP3 VINCENNE TJATTE2 Audio Mixer Audio and Power Management ASIC Filter HEADSET AMP 3D IC HEADSET
CODEC 3D effect Analog S/W Speaker
SPEAKER AMP Speaker
Figure 3-4-7. MP3 Scheme
MP3 function supports PCM 44/48KHz sampling rate.The PCM44/48 RX-path is intended to be used as a 3D surround music headphones and two speakers. Analog switch(NLAS4684) controls the audio path to the headset or two speakers.
- 63 - 3. Technical Brief
3.4.7 Video Telephony This section provides a description of the Video Telephony functions.
MARITA Digital Baseband ASIC
Videp Telephony RX
VINCENNE Audio Mixer Audio and Power Management ASIC
TJATTE2 C-MIC Filter HEADSET AMP 3D IC CODEC HEADSET
Videp Telephony TX By pass Analog S/W Speaker
AUDIO AMP Speaker
Figure 3-4-8. Video Telephony Scheme
Video Telephony Mode has same paths with Loud Speaker Mode.
- 64 - 3. Technical Brief
3.4.8 Audio Part Main Components There are 8 components in U8550 schematic Diagram. Part Number marked on U8550 Schematic Diagram.
N0 ITEM Part Name Part Number 1 Speaker EMS1514TLW1P 2 C-MIC OBG-415S44 X503 3 3D IC NJM2705 U507 4 Audio AMP TPA2005D1 U504, U505 5 Headset AMP LM4809LD U509 6 TJATTE2 IP4025CS20 N504 7 Ear-JACK C-1827541 CN502 8 Analog Switch NLAS4684 U508
Table 3-4-5 Audio Component List
A. TJATTE2 Description The TJATTE2 is a 6-channel RC low pass filter array that is designed to provide filtering of undesired RF signals in the 800-2700 MHz frequency band. In addition, the TJATTE2 incorporates diodes to provide protection to downstream components from Electrostatic Discharge (ESD) voltages as high as 8 kV.
PIN DESCRIPTION PIN DESCRIPTION PIN DESCRIPTION PIN DESCRIPTION A1 MICN B1 GND C1 CCO D1 MICN-int A2 MICP B2 GND C2 ATMS_AD D2 MICP-int A3 ATMS B3 GND C3 GND D3 ATMS-int A4 ATMS-cap B4 AFMS_R C4 GND D4 AFMS_R-int A5 AFMS_L B5 VDD C5 GND D5 AFMS_L-int
Table 3-4-4. TJATTE2 Pin Description
- 65 - 3. Technical Brief
Ω ATMS 47K ATMS_AD A3 C2 2.7K Ω R1 R2 CCO C1 ATMS-cap 1450 Ω 1450 Ω ATMS-int
A4 R3 R4 D3 13.4K Ω 20 pF R5 1K Ω R6 MICP 50 Ω 50 Ω MICP-int
A2 R7 R8 D2 50 pF
50 Ω Ω MICN 50 MICN-int
A1 R9 R10 D1 50 pF 1K Ω R11
AFMS_R 10 Ω AFMS_R-int
B4 R12 D4 200 pF R13 VDD 60K Ω B5 60K Ω 10 Ω R14 AFMS_L AFMS_L-int A5 R15 D5 200 pF GROUND
B1, B2, B3, C3, C4, C5
Figure 3-4-9. TJATTE2 Block Diagram
- 66 - 3. Technical Brief
3.4.9 GPADC(General Purpose ADC) and AUTOADC2 The GPADC consists of a 14 input MUX and an 8-bit ADC. The analog input signal is selected with the MUX and converted in the ADC. The GPADC has a built in controller, AUTOADC2, which is able to operate in the background without software intervention. The AUTOADC2 periodically measures the battery voltage or current. (Fig.2) shows the schematic of GPADC part. The GPADC channel spec is as following (Table 2). 100K R2127 B4 MOD1 2012 2012 2012 C7 ADSTR M10 GPA0 ADCSTR L10 RTEMP GPA1 K10 GPA2 VLOOP L11 GPA3 WPOWERSENSE K11 GPA4 WRFLOOP J11 GPA6 JACK_DET J10 GPA7 VBACKUP J9 GPA12 D9 GPA13
Figure 3-4-10. Schematic of GPADC and AUTOADC2
M U A D X
AUTOADC2 Controller ADSTROBE
Figure 3-4-11. GPADC and AUTOADC2 Block diagram
ADC 6 channels Resource Name Description GPA0 RTEMP Radio temperature sense GPA2 VLOOP Loop voltage sense GPA3 WPOWERSENSE Reference voltage for PAM GPA4 WRFLOOP Lock inform GPA6 GPA6 Headset detect GPA7 VBACKUP Backup battery
Table 3-4-5. GPADC channel spec
- 67 - 3. Technical Brief
3.4.10 Charger control A programmable charger in AB2000 is used for battery charging. It is possible to set limits for the output voltage at CHSENSE- and the output current from DCIO via the sense resistor to CHSENSE-. The voltage at CHSENSE- and the current feed to CHSENSE- cannot be measured directly by the GPADC. Instead, the two measuring amplifiers translate these inputs to a voltage proportional to the input and within the range of the GPADC. Figure 3-4-12 shows the schematic of charging control part. This section provides a detailed description of the Voice Call RX functions.
J9 GPA12 C532 1u D9 GPA13 E2 DCIO DCIN_3 D1 CHREG D3 CHSENSE+ D2 CHSENSE- D1 0 Q501 0 G D2 R2191 R2126 R2236 F11 FGSENSE+ D3 S1 0 DCIN_2 D4 S2 0.05 0.05 R847 R899 R875 D5 S3 R2205 F12 FGSENSE-
D6 0 SI7411DN-T1-E3 0.1 D7 H10 VSS_A G3 C599 C548 VSS_B C6 10p 10p VSS_C VBATI VBAT E3 VSS_D D10 SUB B1 VSSBUCK
D4 TEST
Figure 3-4-12. Schematic of charging control part
ASIC
PA Control DCIO
CHREG Charger Control
CHSENSE+ To GPADC
VBAT CHSENSE-
To GPADC
Figure 3-4-13. Battery charging block diagram
Name Type Unused Description CHSENSE+ Analog VBAT Current sensing input positive CHSENSE- Analog VBAT Current sensing input negative
Table 3-4-6. Charger Control channel spec
- 68 - 3. Technical Brief
3.4.11 Fuel Gauge AB2000(VINCENNE) supports the measurement of the current consumption/charging current in the U8550 with a fuel gauge block. By constantly integrating the current flowing into and out of the battery, the fuel gauge block is used to determine the remaining battery capacity. The function of the fuel gauge block is schematically described in Figure 3-4-15. A sense resistor R_FGSENSE is connected in series with the battery. The voltage across the resistor, equivalent to the current entering/leaving the battery, is integrated using an ADC block.
ASIC
LOAD 16 bit Accumulated charge FGSENSE+
RFGSENSE ADC Accumulators FGSENSE- Sign bit
Figure 3-4-14. The analog front-end of the fuel gauge block
R2236 F11 FGSENSE+ 0 0.05 0.05 R875 R847 R2205 F12 FGSENSE- 0 H10 VSS_A G3 C599 C548 VSS_B C6 10p 10p VSS_C VBAT E3 VSS_D D10 SUB B1 VSSBUCK
Figure 3-4-15. Schematic of the fuel gauge block
Name Type Unused Description FGSENSE+ Analog VBAT Fuel gauge current sensing input positive FGSENSE- Analog VBAT Fuel gauge current sensing input negative
Table 3-4-7. Fuel Gauge channel spec
- 69 - 3. Technical Brief
3.4.12 Battery Temperature Measurement The BDATA node, the constant current source, feed the battery data output while monitoring the voltage at the battery data node with GPADC. This battery data is converted to the battery temperature. Figure 3-4-16 shows the schematic of battery temperature measurement part.
R2194 0 BDATA R548 4.7 B3 MOTOR_BATT VIBR C9 DACDAT DACDAT B10 DACSTR DACSTR A10 R565 R2135 DACCLK 8.2K 180K DACCLK R878 1% 1% 100K R2138 100K R843 VDIG PT501 100K VBATI E10 47K VSSPA G12 1% VDDPA_DAC C12
Figure 3-4-16. Battery Temperature Measurement
Name Type Unused Description
BDATA Digital Input/Output Unconnected current output
Table 3-4-7. BDATA channel spec
- 70 - 3. Technical Brief
3.4.13 Charging Part
The charging block in AB2000 processes the charging operation by using VBAT voltage. It is enabled or disabled by the assertion/negation of the external signal DCIO. Part of the charging block are activated and deactivated depending on the level of VBAT. Figure 3-4-17 shows the schematic of charging part.
C532 1u
E2 DCIO DCIN_3 D1 CHREG D3 CHSENSE+ D2 CHSENSE- D1 0 Q501 0 G D2 R2191 R2126 R2236 F11 FGSENSE+ D3 S1 0 DCIN_2 D4 S2 0.05 0.05 R847 R899 R875 D5 S3 R2205 F12 FGSENSE-
D6 0 SI7411DN-T1-E3 0.1 D7 H10 VSS_A G3 C599 C548 VSS_B C6 10p 10p VSS_C VBATI VBAT E3 VSS_D D10 SUB B1 VSSBUCK
D4 TEST R2194 0 B11 BDATA R548 4.7 B3 MOTOR_BATT VIBR C9 DACDAT DACDAT B10 DACSTR DACSTR A10 R565 R2135 DACCLK 8.2K 180K DACCLK R878 1% 1% 100K R2138 100K R843 VDIG PT501 100K VBATI E10 47K VSSPA G12 1% VDDPA_DAC C12 VDDBUF E12 PASENSE+ PASENSE+ E11 PASENSE- PASENSE- D11 PAREG PAREG D12 IOUT IOUT
Figure 3-4-17. Schematic of Charging Part
When VBAT is below a certain value, 3.2V, a current generator take care of initial charging of the CHSENSE+ node and internal trickle charge signal is active. This part of the charging block is powered on and active when DCIO is asserted. The DCIO signal is asserted when its voltage is above the voltage at VBAT. As soon as generator is turned off and all parts of the charging block are functional and active. Battery block indication as shown in Figure 3-4-18
4.2 ~3.88 (V) 3.87 ~3.78 (V) 3.77 ~3.73 (V) 3.72 ~3.55 (V) 3.54 ~3.23 (V) 100~66 (%) 65~44 (%) 43~25 (%) 24~4 (%) 3~0 (%)
Figure 3-4-18. Battery Block Indication
- 71 - 3. Technical Brief
A. Trickle charging When the VBAT is below a certain value, 3.2V, a current generator take care of internal trickle charge signal is active. The charging current is set to 50mA.
Parameter Min Typ Max Unit
Trickle current 30 50 60 mA
Table 3-4-8. Trickle charging spec
B. Normal charging When the VBAT voltage is within limits or the internal regulators are turned on, the current source for trickle charging is turned off and all parts of the charging block are active. The charging method is ‘CCCV’ (Constant Current Constant Voltage) This charging method is used for Lithium chemistry battery packs. The CCCV method regulates the charge current and the VBAT voltage. This charging method prevents the battery voltage to go above the charge set in the CCCV algorithm. Figure 3-4-19 shows the charging voltage(a) and charging current change(b).
(a) Charging voltage
(b) Charging current
Figure 3-4-19. CCCV charging method
- 72 - 3. Technical Brief
• Charging Method : CCCV (Constant Current Constant Voltage) • Maximum Charging Voltage : 4.2V • Maximum Charging Current : 700mA • Nominal Battery Capacity : 1400 mAh • Charger Voltage : 4.6V • Charging time : Max 3.5h • Full charge indication current (icon stop current) : 80mA • Low battery POP UP : Idle - 3.50V, Dedicated - 3.54V • Low battery alarm interval : Idle - 3 min, Dedicated - 1 min • Cut-off voltage : WCDMA call - 3.15V, ELSE - 3.23V
C. Charging of Extended Temperature When the battery temperature is outside the normal charging specification, the battery voltage, VBAT is maintained at 3.7V. • Under 0°C : Extended temperature • From 0°C to 45°C : Normal charging temperature • Over 45°C : Extended temperature
- 73 - 3. Technical Brief
3.5 Voltage Regulation
3.5.1 Internal Regulation There are LDO (Low Drop Output) regulators and BUCK converter in AB2000 (Vincenne) chip. LDO regulators and BUCK converter generate the following voltages : 1.5V, 1.8V and 2.75V. The output of these LDOs supply VDD-A, VDD-B and VDIG with 2.75V. BUCK converter steps down the VBAT to 1.5V for VCORE and VRTC, and to 1.8V for VMEM voltage. The output of these LDOs and BUCK converter are as following (Table 1). (Fig.1) shows the power supply of each module in U8550.
3.5.2 External Regulation
• 1.5V LDO - supply 1.5V for Wanda core • 1.5V LDO - supply 1.5V for Marita PLL • 2.4V LDO - supply 2.4V for SPK_MIC_BIAS • 2.8V LDO - supply 2.8V for Mega Camera • 2.8V LDO - supply 2.8V for VGA Camera • 2.85V LDO - supply 2.8V for Bluetooth and TransFlash • 3.3V LDO - supply 3.3V for USB • CHARGER PUMP : supply up to 400mA continuous output current for LCD back light and Camera Flash LED
- 74 - 3. Technical Brief
Figure 3-5-1. Power supply scheme
Pin Name Type Output voltage Description B12 VDD_A Power Supply 2.75V Supply output A11 VDD_B Power Supply 2.75V Supply output M11 VDD_D Power Supply 2.75V Supply output L12 VDD_E Power Supply 1.8V Supply output L2 VDDLP Power Supply 1.5V Low Power supply output A2 VDDBUCK Power Supply Unused: VBAT Buck converter switch supply B1 VSSBUCK Power Supply GND Buck converter switch ground
Table 3-5-1. LDO and BUCK
- 75 - 3. Technical Brief
3.6 General Description of RF Part The RF part includes a tri-band GSM/DCS/PCS part (900, 1800 and 1900MHz) and W-CDMA part for IMT-2000 (UL 1900MHz, dl 2100MHz). It also contains Antenna Switch, WCDMA duplexer, WCDMA Power Amplifier and GSM Power Amplifier.
The whole structure of Radio part is shown in Figure 3-6-1.
Figure 3-6-1. Block diagram of RF part
Starting at the antenna end, an antenna switch provides switching capability needed for four frequency bands (900, 1800, 1900 and 2100MHz). For the W-CDMA part, duplexer is included to facilitate the simultaneous transmission and reception required for the FDD mode. The main components in the radio are Wopy (W-CDMA receiver ASIC), Wivi(W-CDMA transmitter ASIC), Ingela(GSM/GPRS transceiver) and two power amplifiers. The mixed-signal circuit ASIC, Vincenne provides power supply for the main RF components. The control flow for the Radio is shown in Figure 3-6-2
- 76 - 3. Technical Brief
WCDMA RF ASIC Ctrl Wopy WANDA WCDMA PA Wivi
Antenna Antenna Switch Ctrl Swit ch Ingela Herta GSM RF ASIC Ctrl Marita
GSM PA
GSM/DCS GSM/DCS Band select PA Ctrl Vincenne Ctrl
WCDMA PA Ctrl DAC Ctrl (Indirect GSM PA Pwr Ctrl) Vincenne VCXO Ctrl DAC Ctrl (Indirect WCDMA PA Pwr Ctrl)
Figure 3-6-2. RF control signal flow diagram
The MARITA(the main processor) controls the overall radio system. In the GSM/GPRS air interface mode, this control is handled via direct interfaces to individual RF components. The MARITA(the main processor) also handles the antenna switch mechanism for selection of mode. In the W-CDMA mode, the RF system is managed via the Wanda (WCDMA digital base-band coprocessor ASIC) and its DSP processor.
- 77 - 3. Technical Brief
3.7 GSM Mode
3.7.1 Receiver The received RF signal on the antenna connector arrives via antenna switch at external band pass filters for band selectivity. One filter is required per supported GSM band. The corresponding LNA amplifies the signal for optimum noise suppression. The LNA output signal is mixed with the on-channel LO generated by the proper VCO and transformed into a Q and an I signal. The I and Q signals are low pass filtered with two parallel high dynamic range filters. Finally, the filtered I and Q signals are converted by a sigma-delta converter into two 13 Mbps digital bit streams by Herta(A/D converter), then fed to the Marita baseband ASIC.
A. Front end RF Front end consists of antenna, antenna switch(FL101), three RF SAWs(FL402, FL403, Z401) and triple band LNAs integrated in transceiver(N405). The Received RF signals (GSM 925MHz ~ 960MHz, DCS 1805MHz ~ 1880MHz, PCS 1930MHz ~ 1990MHz) are fed into the antenna or coaxial connector. An antenna matching circuit is between the antenna and the coaxial connector. The Antenna Switch(FL101) is used to select the signal path, which is one of WCDMA, GSM RX, GSM TX, DCS RX, DCS/PCS TX and PCS Rx. The control signals VC1, VC2 and VCG of antenna switch (FL101) are connected to Marita baseband ASIC(D601) to control the signal path. For example, when the GSM RX path is turned on, the received RF signal, which has passed through the antenna switch, is filtered by GSM RF SAW filter to suppress any unwanted signal except GSM RX band. The filtered RF signal is amplified by an LNA integrated in the transceiver IC(N405) and is passed to a direct conversion demodulator. The process for DCS RX is also the same as GSM RX case. The logic for antenna switch is given below Table 3-7-1.
VC1 VC2 VCG GSM TX 0V 0V 2.8V ~ 3.0V GSM RX 0V 0V 0V DCS/PCS TX 2.8V ~ 3.0V 2.8V ~ 3.0V 0V DCS RX 0V 2.8V ~ 3.0V 0V PCS RX 2.8V ~ 3.0V 0V 0V WCDMA 0V 0V 0V
Table 3-7-1. Antenna Switch logic
- 78 - 3. Technical Brief
B. Receiver Block The circuit contains one frequency down-conversion section for each receive band and a common base band amplifier and filter section. The GSM900 RF part consists of a low noise amplifier followed by high dynamic range mixers. The DCS 1800 and PCS 1900 RF part also have low noise amplifier connected to the other mixers. The amplified RF signal is mixed with the quadrature local oscillator signal to create in-phase (I) and quadrature phase (Q) baseband signals. The I and Q signals are then buffered and low pass filtered. The same baseband circuitry is used for all bands. Balanced signals are used for minimizing cross talk due to package parasitics. An impedance level at RF of 150 ohms for the GSM 900 input and 50 ohms for the DCS 1800/PCS 1900 input is chosen to minimmize current consumption at best noise performance. The low gain mode in GSM 900 is used in high input signal mode. There is no gain switch in DCS 1800/PCS 1900. Figure 3-7-1 shows a block diagram of the receiver block.
MIXHI RF1800p LNA RF1800n 1800 MHz LOHI
LOHQ IRA RF1900p LNA IRB RF1900n 1900 MHz MIXHQ
MIXLI QRA QRB
LOLI RF850/900p LNA RF850/900n LOLQ 850/900 MHz LNAL LNAH1 LNAH2 BB GNDRF BIAS CIRCUITS
MIXLQ
Figure 3-7-1. Block diagram of receiver part
- 79 - 3. Technical Brief
C. LO Block The LO signals from the receive VCO section drive the dividers for GSM 900, DCS 1800 and PCS 1900 respectively to provide quadrature LO signals to the receive mixers. The LO signal is also supplied to the prescaler and transmit output buffer. Figure 3-7-2 shows a block diagram of the LO block.
LOLBUFI . To MIXLI 0 DIVIDER From GSM 850/900 RX VCO / 2 To MIXLQ 90
LOLBUFQ
GNDLO To prescaler VCCLO LOHBUFI
To MIXHI 0 DIVIDER From GSM 1800/1900 RX VCO / 2 To MIXHQ 90
LOHBUFQ
LOL LOH
BIAS CIRCUITS
Figure 3-7-2. Block diagram of the LO part
- 80 - 3. Technical Brief
D. VCO Block The VCOs are fully integrated balanced LC oscillators with on-chip resonators. The receive VCOs run on double frequency. Different frequency ranges can be selected in the VCOs for GSM, DCS and PCS band operation. The VCOs are supplied from a separated external voltage regulator to avoid frequency pushing and up conversion of low frequency noise. A separate ground pin is also used as varactor ground reference to prevent DC voltage drop changes from affecting the VCO frequency. Figure 3-7-3 shows a block diagram of the VCO block.
Figure 3-7-3. Block diagram of the VCO part
- 81 - 3. Technical Brief
E. PLL Block The PLL consists of a programmable prescaler with multiple division ratios and a phase and frequency detector with a charge pump with programmable output current. Channel frequency selection and transmitter modulation is controlled via the prescaler modulus inputs MODA ~ MODD and the prescaler offset value N offset. The MODA ~ MODD signals could be delayed 0, 5, 10 or 15 ns with MD bits to be synchronized with the XO signal. Figure 3-7-4 shows a block diagram of the PLL block.
MD
2 I PHD MODA 6 MODB DELAY PHDOUT CHARGE PUMP MODC MODD
PHASE From XO PRESCALER DETECTOR From VCO
PULSE PS 7 SKIP TBL VCCPRE DETECTOR NPS N offset VCCPHD GNDPRE GNDPHD
DELAY PHD/CP PRE BIAS CIRCUITS
Figure 3-7-4. Block diagram of the PLL part
- 82 - 3. Technical Brief
3.7.2 Transmitter A 4-bit sigma-delta bit stream comes from the Marita ASIC including both channel information and the GMSK phase information. Via the 3-wire control bus also driven from Marita, the selection of transmitter band is made. The 4bits from the bit stream provides the fine-tuning of the division ratio before going to the divider of the used VCO (low band, 900MHz or high band, 1800/1900MHz). The modulated VCO signal is fed to the output buffer. One buffer is available for each of the low and high bands. Trimming capability is included for best match versus the PA used. The GSM/GPRS transceiver, Ingela, output is passed to the dual-band PA that after amplification feeds the signal via a low pass filter to the antenna switch and further to the antenna. The transmit block consists of two differential high power transmit output buffers with controllable output power. The modulated transmit signal from the VCO buffer is amplified to a level suitable to drive the external power amplifier. The buffer outputs are of open collector type and must be terminated into a suitable load. Figure 3-7-5 shows a block diagram of the transmitter block.
MUX To prescaler
TXBUFH TXOHA From GSM 1800/1900 TX VCO TXOHB PCTL TXOLA From GSM 800/900 TX VCO TXOLB TXBUFL VCCBUF
GNDBUF TXBUFL TXBUFH
BIAS CIRCUITS
Figure 3-7-5. Block diagram for the transmitter
- 83 - 3. Technical Brief
A. Power Amplifier The Power Amplifier (N401) is intended for use in EGSM and DCS/PCS mobile equipment. It is a module with two parallel amplifier chains, with one chain for the EGSM transmitter section and one for the DCS/PCS transmitter section. Each chain amplifies the RF signal from the respective transmitter to the antenna. The power amplifier supports class 10.
Band selection and the output power level of the RF amplifier are controlled by discrete signals Vband
and Vapc respectively from the digital baseband controller ASIC(Marita).
Vband GND Vapc
GND 10pF GND DCS/PCS Pin DCS/PCS Pout
GND GND 33pF EGSM Pin EGSM Pout GND GND
100pF 100pF
Vcc GND Vcc
Figure 3-7-6. Block diagram of the Power Amplifier with Two Parallel chains
- 84 - 3. Technical Brief
3.8 WCDMA Mode
3.8.1 Receiver The received RF signal on the antenna connector arrives via the antenna switch to the duplexer. The duplexer directs the signal to the LNA, which resides in Wopy (W-CDMA Receive ASIC) as every other active part of the radio receiver. The LNA has two different gain settings. From the output of the LNA, the signal is fed to the input of a RF SAW filter, and then appears at the differential output of the filter. The differential output of the RF SAW filter is connected to the differential mixer input, and the received signal is down-converted to a 190MHz IF frequency (with the RFLO signal) by the mixer. At 190MHz, the signal is filtered in a differential (input and output) IF SAW filter, with the approximate bandwidth of 4MHz, and then again the signal is fed to Wopy (W-CDMA Receive ASIC), this time to the differential IF input, which also has a LNA. From the 190MHz, the signal is mixed down to base-band I and Q which represented signals (using the IFLO signal). Finally the signals are filtered in low pass filters and amplified in baseband VGAs. The I and Q represented signals appear at the output of Wopy (W-CDMA Receive ASIC) as differential voltages. The large signal gain provided by the processing steps from the antenna down to base-band gives a DC offset at the outputs of Wopy (W-CDMA Receive ASIC). To eliminate this, there are DC-offset compensation loops included, one in the VGA of each of the I and the Q signals.
A. IFLO Section The balanced IFLO signal from an external IFVCO drives the divider to provide qaudrature LO signals to the RxIF mixers. The LO buffers amplifies the signal to a suitable amplitude and DC level to drive the RxIF mixers.
IFLOBUFI
To IFLOI 0 DIVIDER From IFLO 4 To IFLOQ 90
IFLOBUFQ
IFLO BIAS CIRCUITS
Figure 3-8-1. Block diagram of the IFLO section
- 85 - 3. Technical Brief
B. RFLO Section The VCO is a fully integrated balanced LC oscillator with on-chip resonator. An on-chip varactor is used to control the frequency over the desired tuning range. A separate external voltage regulator supplies the VCO with power to avoid frequency pushing and up conversion of low frequency noise. A separate ground pin is also used as varactor ground reference to prevent DC voltage drop changes from affecting the VCO frequency. Via the serial interface, the VTUNE voltage can be set to VCC/2 to check the center frequency of the VCO. The PLL consists of a programmable prescaler with multiple division ratios and a phase and frequency detector with a charge pump with programmable output current. Channel frequency selection is set via the serial interface.
VCCVCO vco
C RFVCO GNDVCO
VTUNE vco RFLOO GNDTUNE
VCCPHD
GNDPHD CHARGE PHDOUT PUMP IPHD
PHASE DET. $ N DIVIDER
Ndiv
R From XO DIVIDER
VCCPLL VCO PLL RFLO Rdiv GNDPLL BIAS CIRCUITS
Figure 3-8-2. Block diagram of the RFLO section
- 86 - 3. Technical Brief
C. Reference Section The reference block consists of a balanced oscillator and a buffer amplifier. The crystal unit and the feedback capacitors are external. The current consumption when only the reference oscillator and the output buffer are activated must be kept to an absolute minimum.
To PLL
XOOON XOIA MCLK XO XOIB
REFON XOOA XOOB
XOOON
XOOON REFON BIAS CIRCUITS
Figure 3-8-3. Block diagram of the Reference section
- 87 - 3. Technical Brief
3.8.2 Transmitter Analogue differential signals (currents), representing I and Q, are sent to the radio ASCI Wivi (W- CDMA Transmitter ASIC) from the D/A converter in Wanda (W-CDMA digital base-band coprocessor ASIC). The signals are filtered in a reconstruction filter and then modulated up to 380MHz (using the IFLO signal). The signal is then amplified in a VGA and filtered in an external filter (an LC filter). After filtering, the signal is mixed to its final frequency (using the RFLO) and amplified in a differential output RF buffer with two different gain settings (high gain or low gain). The differential RF signal is fed into a SAW filter with a single ended output, and is then amplified in a stand-alone RF buffer. After the RF buffer, the signal is filtered again in a SAW filter before it is fed to the PA (Power Amplifier). In the PA the signal is amplified for the last time before leaving the radio. After the PA, the signal is sent through an isolator and through the duplexer, which directs the transmit signal to the antenna connector via the antenna switch. The PA has variable supply voltage, which adapts itself by means of a control loop so that the linearity of the PA is kept constant. The variable supply voltage is provided from the battery through a DC/DC converter and a signal linearity detector sits at the PA output. The detected signal at the PA output is compared with a reference (supplied by the Vincenne, the mixedsignalcircuit ASIC), and the error signal is used in a loop filter, which provides the control signal to the DC/DC converter. A. Reconstruction Filters The reconstruction filters consist of input buffers that provide the correct DC biasing for the preceding DAC in the digital baseband controller, and a low-pass filter for removing the unwanted high frequency components from the baseband input waveform. The filter inputs are adapted for use with a current-source type of input signal. B. IQ-modulator The IQ-modulator receives the incoming I and Q analog baseband signals at baseband frequency and converts them to an intermediate frequency of 380MHz.
- 88 - 3. Technical Brief
C. Variable Gain Amplifier(VGA) Comprising two cascaded variable gain amplifiers, the VGA-together with the RF mixer-controls the power of the transmitter. The first of these two amplifiers, the so-called QVGA, enables fine-tuning of the transmitter by varying the gain in 0.25dB steps, that is 0/0.25/0.5/0.75dB. The second amplifier provides a 54dB gain range in 1 dB steps (54steps = 55 levels). D. IF Band Bass Filter (IFBP) The IF filter suppresses spurious signals and eliminates unwanted frequency components generated in the IQ modulator and subsequently amplified in the VGA. The filter is tuned using an external RLC load as shown in Figure 3-8-4.
External tuned load
Off chip On chip
Vb,casc
Vb
Figure 3-8-4. Principle Schematic of the IFBP
- 89 - 3. Technical Brief
E. RF Mixer and Buffer The RF mixer converts the signal output from the IF BP filter from an intermediate frequency (IF) to the final radio frequency (RF). The mixer can be switched between three different gain levels: high gain (HG), medium gain (MG), and low gain (LG). The LO buffer provides the buffering for either an internal LO signal generated within the internal RFPLL, or an external LO signal applied to the RFLO/RFLOBAR pins. External DC blocking is necessary for the external LO signal. The RF buffer is used to drive an external PA stage. The buffer is of an open-collector design. The gain switching together with the VGA amplifier at IF will enable an output power control in 0.25 dB steps over no less than 80dB. The programmable bias in the high and mid-gain settings is specified as a reduction of bias current from the maximum bias condition. It should achieve a reduction of bias current from the nominal value of 17mA to 3mA (signal ended) in 7 steps. GNDRF VCCRF
RF-mixer & RF buffer IN OUT INBAR OUTBAR
BUFFGAIN & 2 Bias & BUFFGAIN2 Logic LOINTEXT
3 RFLOBAR RFLO GAINMETH RFBIAS ENABLE
Figure 3-8-5. Block Diagram of RF Mixer and Buffer
- 90 - 3. Technical Brief
F. Power Amplifier The N302(RF9266) is a high-power, high-efficiency linear amplifier module targeting W-CDMA transmitter ASIC. The module is fully matched to 50ߟ for easy system integration and utilizes advanced GaAs HBT process technology. The PA features an integrated RF power output detection network and is compatible with DC-DC converter operation in DC power management applications. Additionally, a variable bias-current allows the idle current to be adjusted for optimum performance at a given RF output power.
GND RFin GND
Vctrl 1 22 21 20 Vcc1 19 IMN
Vctrl 2 Vcc1 18
GND 3 GND 17 BIAS
Vcc2 4 Vcc_bias 16
Vcc_bias 5 Vcc2 15
GND 6 Detector 14 GND network OMN
Vccdet 7 GND 13
8 9 10 11 12 Vdet GND GND GND RFout
Figure 3-8-6. Block Diagram of W-CDMA power amplifier
- 91 - 3. Technical Brief
3.8.3 Frequency Generation The Wopy (W-CDMA Receive ASIC) contains the active elements for a 13MHz VCXO, which is designed to be the reference frequency of the UE. There are two synthesizers in the W-CDMA part of the radio, an intermediate frequency (IF) synthesizer and a radio frequency (RF) synthesizer. They generate the Intermediate Frequency Local Oscillator (IFLO) and Radio Frequency Local Oscillator (RFLO) signals. Both synthesizers are used in both the transmitter and the receiver, which gives the radio a fixed duplex distance of 190MHz. The RF synthesizer is in the Wopy (W-CDMA Receive ASIC), except for the loop filter, which is external. The 13MHz clock is used as the reference, and the phase detector frequency is 200kHz. The programmable divider makes the RF synthesizer cover the 2300~2360MHz band. The IF synthesizer is in the Wivi (W-CDMA Transmitter ASIC), except for the loop filter. The 13MHz is used as the reference, and the phase detector frequency is 1MHz. The IF VCO runs at 1520MHz given that the (programmable) reference divider is set to 13. The synthesizers are controlled by Wanda (W-CDMA digital base-band coprocessor ASIC) via the serial bus to Wivi (W-CDMA Transmitter ASIC) and Wopy (W-CDMA Receive ASIC).
- 92 - 3. Technical Brief
A. IF PLL The IF LO frequency synthesis comprises the four following par is:
- Input buffer: A 13MHz input buffer with DC-biasing provided at source. - VCO: Operating on 1.52GHz which is 4times the TX-IF frequency (380MHz) and 8 times the RX-IF (190MHz), this is a fully integrated balanced LC oscillator with on-chip resonator. On-chip varactor are used to tune the VCO frequency. - Prescaler - Phase-detector with charge pump
For maintaining check on the VCO center frequency, the tuning voltage is set to Vcc/2. External DC blocking capacitors must be used on the IFLO/IFLOBAR signals. IF LO IFLOTX T XBAR
VCCIFVCO IF PLL
GNDIFVCO Bias IFPLLON
IFLO
IFLOBAR TBIFVCO TBIFSI Div 2 VTUNEIF TBIFSO
XO / R GNDTUIF XOBAR / R
R PHD
Charge PHDIFOUT Pump X X GNDIFPHD VCCIFPHD VCCIFPHD GNDIFPLL OOB OOA
Figure 3-8-7. Block Diagram of Frequency Synthesizer Part (IF PLL)
- 93 - 4. TROUBLE SHOOTING
4. TROUBLE SHOOTING
4.1 Power ON Trouble
START
The voltage of main battery No Charge or change is higher than 3.2V ? main battery
Yes
Follow the Press END key. No Keypad backlight Keypad LED ON? Trouble shooting guide Yes
END key operates well? No Follow the keypad Trouble ONSWAn(C597) level is low shooting guide when END key pressed.
Yes
Check the voltage. VCORE (R600) 1.5V VDIG (R560) 2.8V VMEM (R563) 1.8V VRTC (R551) 1.5V VEXT15_M (N502 Pin#5) 1.5V VEXT15_W (N702 Pin#5) 1.5V VDD_A (R2250) 2.8V VDD_B (R2251) 2.8V
No
Change main board
- 94 - 4. TROUBLE SHOOTING
N502
N405
D601
R2250
N201
R560
R551 R563 N503
R600
C597 N702
- 95 - 4. TROUBLE SHOOTING
4.2 USB Trouble
START (Measure during the state of USB module running)
No Check host USB port Input power(N501, Pin#1) is 5V? or USB cable Yes No Output power(N501, Pin#5) is 3.3V? Resolder or change N501 Yes No USBSENSE level is 2.8V? Resolder R513or R514 Yes No VUSB(C623) is 3.3V? Resolder C623 Yes
Change main board
N501 R513
R514
D601
C623
- 96 - 4. TROUBLE SHOOTING
4.3 SIM Detect Trouble • SIM control path - MARITA generates SIM interface signals(2.75V level) to VINCENNE. - Vincenne converts SIM interface signals to 3V/5V.
START
Reconnect SIM card
Yes SIM work well? Finish No
Resolder X502 on main PCB and check the contact between X502 and SIM card No
No
Change SIM card X502 No
Yes SIM work well? Finish No
Change main board
- 97 - 4. TROUBLE SHOOTING
4.4 TransFlash Trouble
START
Re-insert TransFlash
Yes TransFlash work well? Finish N o
Check operation of TransFlash using other notebook or PDA
No TransFlash work well? Change the TransFlash
Yes
Re-insert TransFlash
No Check output of U510 VTF(C636) is 2.85V? C636 Resolder C636 Yes S601 R653 No TF_DETECT(R653) is 2.85V? Resolder R653
Yes Yes TransFlash work well? Finish
N o
Change main board
- 98 - 4. TROUBLE SHOOTING
4-5 Keypad Trouble
Keypad singals to MARITA and VINCENNE through board-to-board connector.
START
Press the Keypad
YES Keypad operates well?
NO 1
Check B to B connector short? YES Resolder B to B connector CN703(Main Bíd), CN1(Keypad) CN703(Main Bíd) or CN1(Keypad)
NO YES Keypad operates well?
NO Change Keypad
YES Keypad operates well?
NO
Change Main Board Finish
- 99 - 4. TROUBLE SHOOTING
Keypad signals to MARITA and VINCENNE through board-to-board connector.
13 CN703 12 Pin #16 ~ #21 KEYOUT5 KEYIN0 KEYOUT4 KEYIN1 KEYOUT3 KEYIN2 KEYOUT2 KEYIN3 KEYOUT1 KEYIN4 KEYOUT0 OMSWAn Pin #4 ~ #9
24 1 1
12 CN1 13 KEYOUT5 Pin #16 ~ #21 KEYOUT4 KEYIN0 KEYOUT3 KEYIN1 KEYOUT2 KEYIN2 KEYOUT1 KEYIN3 KEYOUT0 KEYIN4 Pin #4 ~ #9 OMSWAn
1 24
- 100 - 4. TROUBLE SHOOTING
4-6 1.3M Camera Trouble
Camera control signals are generated by Marita
START
Press END Key to turn on the power
NO Follow the Power On Trouble Is the circuit powered? Shooting
YES 1 Reconnect the 26pin B to B connector CN702 and 1.3M Camera Connector
YES 1.3M Camera Operation OK?
NO
NO 2 Pin 5 of U502 or C504 = 1.8V? Change U502 or U503 Pin 5 of U503 or C523 = 2.8V?
NO YES
Change 1.3M Camera
NO 1.3M Camera Operation OK? Change the Camera & LCD FPCB
NO YES
1.3M Camera Works Change the Main Board
- 101 - 4. TROUBLE SHOOTING
1
CN2 CN702
2
C523
5
U503 U502 C504
4
- 102 - 4. TROUBLE SHOOTING
4-7 VGA Camera Trouble
Camera control signals are generated by Marita
START
Press END Key to turn on the power
NO Follow the Power On Trouble Is the circuit powered? Shooting
YES 1 Reconnect the 50pin B to B connector CN701 and VGA Camera Connector
YES VGA Camera Operation OK?
NO
NO 2 Pin 5 of U501 or R721 = 2.8V? Change U501
NO YES
Change VGA Camera
NO VGA Camera Operation OK? Change the Camera&LCD FPCB
NO YES
VGA Camera Works Change the Main Board
- 103 - 4. TROUBLE SHOOTING
2
CN701
4
U501
R721
1
- 104 - 4. TROUBLE SHOOTING
4-8 Main LCD Trouble
LCD control signals are generated by Marita
START
Press END Key to turn on the power
NO Follow the Power On Trouble Is the circuit powered? Shooting
YES 1 Disconnect and Reconnect the 50pin B to B connector (FPCB and Main)
YES LCD Display OK?
NO 2 Disconnect and Reconnect the 40pin B to B connector (LCD and FPCB)
NO LCD Display OK? Change Camera&LCD FPCB
YES Change LCD Module
YES The LCD Works LCD Display OK?
NO
Change the Main Board
- 105 - 4. TROUBLE SHOOTING
CN701 1
CN2
Main Board 50 pin B to B Connector FPCB Board 50 pin B to B Connector
2 CN1
FPCB Board 40 pin BtoB Connector
LCD Module 40 pin BtoB Connector
- 106 - 4. TROUBLE SHOOTING
4-9 Sub LCD Trouble
START
Press END Key to turn on the power
NO Follow the Power On Trouble Is the circuit powered? Shooting
YES 1 Disconnect and Reconnect the 50pin B to B connector (FPCB and Main)
YES Sub LCD Display OK?
NO 2 Disconnect and Reconnect the 40pin B to B connector (LCD and FPCB)
NO Sub LCD Display OK? Change Camera & LCD FPCB
YES Change LCD Module
YES The LCD Works Sub LCD Display OK?
NO
Change the Main Board
- 107 - 4. TROUBLE SHOOTING
CN701 1
CN2
Main Board 50 pin B to B Connector FPCB Board 50 pin B to B Connector
2 CN1
FPCB Board 40 pin BtoB Connector
LCD Module 40 pin BtoB Connector
- 108 - 4. TROUBLE SHOOTING
4-10 Keypad Backlight Trouble
START
Press END Key to turn on the power
YES Keypad Backlight Works?
NO
NO 1 Backlight Control Signal is 2.8V at R741?
YES 2 Resolder or Change Q701
YES Keypad Backlight Works?
NO
Change Keypad
NO Keypad Backlight Works?
YES
Finish Change Main Board
- 109 - 4. TROUBLE SHOOTING
R741 2.7K KEY_LED_ONOFF R742
1 2 3 12 Q701 EMX18 R727
12
6 5 4 KEY_LED-
Keypad Backlight Control
VBATI
R32 100K PG05DBTFC LEBB-S14H LEBB-S14H LEBB-S14H LEBB-S14H LEBB-S14H LEBB-S14H LEBB-S14H LEBB-S14H LEBB-S14H LEBB-S14H LEBB-S14H LD5 LD2 LD9 LD8 LD3 LD1 LD6 LD7 LD4 LEBB-S14H LD11 LD12 LD10 LD13
LEBB-S14H R33 100K C3 PG05DBTFC 0.1u R3 R4 R6 R2 R5 150 150 150 150 150 150 150 150 150 150 150 150 150 R30 R26 R14 R23 R15 R29 R31 R34 100K R10
PG05DBTFC KEY_LED-
Q701 R741
1 2
- 110 - 4. TROUBLE SHOOTING
4-11 Camera Flash Trouble
START
Press END Key to turn on the power
NO Is the circuit powered? Follow the Power On Trouble Shooting
YES 1 Disconnect and Reconnect the 26pin BtoB connector (FPCB and Main)
Change Flash LED YES Camera Flash Works?
NO 3 Check Flash LEDs YES 2 Pin16,Pin17,Pin18 of U701 (4.0V Direct Power Supply) over 3.5V??
NO NO Pin10 of U701 is High? Flash LED Works? NO
YES 4 Change the U701 YES
NO Resolder Flash LEDs or Camera Flash Works? Change Camera&LCD FPCB
NO Change the Main Board Camera Flash Works?
YES
Finish
- 111 - 4. TROUBLE SHOOTING
1
CN2 CN702
2 3
Over 3.5V?
Pin17
Pin18 Pin16
U701
- 112 - 4. TROUBLE SHOOTING
4.12 Audio Trouble
4.12.1 Receiver • Signals to the receiver - Receiver signals are generated at Vincenne • BEARP, BEARM - Receiver path : • Vincenne (BEARP, BEARM) → • CN701 on main board → • LCD Module → • Receiver
♣ Note : It is recommanded that engineer should check the soldering of R, L, C along the corresponding path before every step.
- 113 - 4. TROUBLE SHOOTING
START
Connect the phone to network Equipment and setup call Setup 1KHz tone out
NO Does the sine wave appear Change the main board at L501,L502 ?
YES The sine wave not appear
Does the sine wave appear NO at Number 47, 48 pin Check R510,R511 in the main Bíd CN701?
YES
Does the sine wave appear NO at EAR(+) PAD in LCD Module? Change the LCD module
YES
NO Is the soldering ot the receiver OK? Resolder Receiver
YES
NO Can you hear sine wave out of the receiver ? Change the Receiver
YES
END
- 114 - 4. TROUBLE SHOOTING
Pin 47,48 L501,L502
50 26 CN701
1 25
B SIDE
- 115 - 4. TROUBLE SHOOTING
Measured 1khz Sine Wave Signal
Measured 1khz Sine Wave Signal
- 116 - 4. TROUBLE SHOOTING
4.12.2 Speaker (Voice Loud Speaker,Midi, MP3,Key Tone)
Signals to the speaker • AUXO1/Right, AUXO2/Left - AUXO1/Right, AUXO2/Left • Speaker path : - Vincenne (AUXO1/Right, AUXO2/Left) → - U507(Surround Audio Processor) on the main board → - C584,C585 on the main board → - N504(ADG) on the main board → - U508(Analog Switch) on the main board → - U504,U505(Speaker Amp) on the main board → - CN703 on the main board → - CN3, CN4 on the Key PCB → - Speaker
♣ Note : It is recommanded that engineer should check the soldering of R, L, C along the corresponding path before every step.
- 117 - 4. TROUBLE SHOOTING
START
Connect the phone to network Equipment and setup call Setup 1KHz tone out
NO Does the sine wave appear Change the main board at C572,C573 ?
YES The sine wave not appear
Does the sine wave appear NO Change U507 at C584,C585 ?
YES
N Does the sine wave appear Change the main board at R582,R584 ? O
YES The sine wave not appear
NO Does the sine wave appear Change U508 at R533,R539 ?
YES The sine wave appear
Does the sine wave appear at CN703 num22,23 ? Resolder CN703 num 22,23
The sine wave not appear The sine wave appear YES Change U504,U505 each The sine wave not appear
NO Does the sine wave appear Change the Key PCB at CN3,CN4 ?
YES
Can you hear sine wave NO out of each speakers ? Change each Speaker
YES
END
- 118 - 4. TROUBLE SHOOTING
CN703 #22,23
24 1
R533,R539
R582,R584
C584,C585 C572,C573
CN3, CN4
- 119 - 4. TROUBLE SHOOTING
Measured 1khz Sine Wave Signal
- 120 - 4. TROUBLE SHOOTING
4.12.3 Microphone (Voice call, Voice Recorder, Video Recorder)
• Microphone Signal Flow - MIC is enable by MIC Bias - MICBAS, MICIP, MICIN signals to ABB (Vincenne)
• Check Points - Microphone bias - Audio signal level of the microphone - Soldering of components
• Signal from the MIC : - MIC → - N504(TJATTE2) on main board → - C567,C568 on main board → - Vincenne
- 121 - 4. TROUBLE SHOOTING
START
Check the MIC bias level at the pad of MIC+(X503)
Check the signal level No Is the level of MIC+ AND MIC- at C568 at the putting 2.4Volt ? Audio signal in MIC
Yes Yes Resolder C566,C567, C568 A few hundred of mV No and try again. of the signal measured ? If fail again, change the main Bíd
Yes
Yes Change the main B,d
No Does it work properly ?
YES
END
- 122 - 4. TROUBLE SHOOTING
C566
C567
C568
- 123 - 4. TROUBLE SHOOTING
Measured Some Noise Signal
- 124 - 4. TROUBLE SHOOTING
4.12.4 Headset - Receiver(Voice call, Video Telephony,MP3)
START
Connect the phone to network Equipment and setup call Setup 1KHz tone out
Insert Headset. NO Does the Headset icon display Does the level of R2252 on the main LCD? under 0.5Volt ?
YES YES
NO Does the sine wave appear Change the main B,d at C572,C573 ?
YES
NO Does the sine wave appear Change the U507 If the sine wave doesnít appear at C584,C585 ?
YES
NO Does the sine wave appear Change the U509 at C592,C593 ?
YES
Resolder CN502 Pins or change the Headset
Can you hear sine wave NO Change the main Bíd out of the receiver ?
YES
END
- 125 - 4. TROUBLE SHOOTING
4.12.5 Headset - MIC(Voice call, Video Telephony)
START
Insert Headset. NO Does the Headset icon display Does the level of R2252 on the main LCD? under 0.5Volt ?
YES YES
Check the signal level at R569 at the putting Change the main B,d Audio signal in MIC
Resolder C554, A few hundred of mV NO R569 and try again. of the signal measured If fail again, at C575? Change the main Bíd
YES
Change the main B'd
NO Does it work properly ?? Try again from the start
YES
END
- 126 - 4. TROUBLE SHOOTING
4.12.6 Headset
R2252 C572,C573 C584,C585 C592,C593
CN502
R569 C554 C575
- 127 - 4. TROUBLE SHOOTING
4.13 Charger Trouble
J9 GPA12 C532 1u D9 GPA13 E2 DCIO DCIN_3 D1 CHREG D3 CHSENSE+ D2 CHSENSE- D1 0 Q501 0 G D2 R2191 R2126 R2236 F11 FGSENSE+ S1 D3 0 DCIN_2 S2 D4 0.05 0.05 R847 R899 R875 S3 D5 R2205 F12 FGSENSE-
D6 0 SI7411DN-T1-E3 0.1 D7 H10 VSS_A G3 C599 C548 VSS_B C6 10p 10p VSS_C VBATI VBAT E3 VSS_D D10 SUB B1 VSSBUCK
D4 TEST
Figure 4-13-1. Main Battery Charging Path
• Charging Procedure - Connecting TA and Charger Detection - Control the charging current by AB2000(Vincenne) - Charging current flows into the battery
• Check Point - Connection of TA - Charging current path - Battery
• Trouble shooting setup - Connect TA and battery to the phone
• Trouble Shooting Procedure - Check the charger connecter - Check the Charging current Path - Check the battery
- 128 - 4. TROUBLE SHOOTING
start
Check the pin and battery connect terminals of I/O connector
NO Connection OK? Change I/O connector
YES
NO Is the TA voltage 4.6V? Change TA
YES
Is it charging properly YES END after changing Q501?
NO
Change the board
Q501
L702 IO Connector
- 129 - 4. TROUBLE SHOOTING
4.14 RF Component
N301 N402 N302 N303 B301 FL102
N403 N404 FL402
FL403
Z401 N405
Figure 4-14-1. RF component (Top)
Reference Description Reference Description N301 VOLTAGE_REGULATOR N403 DCS_TX_BALUN
N402 HERTA (GSM ADC) N404 GSM_TX_BALUN N302 WCDMA PAM FL402 DCS_RX_SAW N303 ISOLATOR FL403 PCS_RX_SAW
B301 TEMP_SENSOR Z401 GSM_RX_SAW FL102 DUPLEXER N405 GSM TRANSCEIVER
- 130 - 4. TROUBLE SHOOTING
W101 N401 FL401 FL301
FL101
FL201
N201 N304
N101
B201
V201 Z201
Figure 4-14-2. RF component (Bottom)
Reference Description Reference Description W101 TEST CONNECTOR Z201 WCDMA RX IF SAW N401 GSM PAM V201 DIODE/VARIABLE CAP FL401 EMI FILTER B201 CRYSTAL
FL301 WCDMA TX RF SAW N201 WCDMA RX IC (WOPY) N304 WCDMA TX IC (WIVI) FL201 WCDA RX RF SAW N101 REGULATOR FL101 ANT SW MODULE
- 131 - 4. TROUBLE SHOOTING
4.15 Procedure to check
start
Oscilloscope setting
1. Check Power Source Block
2. Check VCXO Block
3. Check Ant. SW Module
Agillent 8960 : Test mode(WCDMA) Ch. 9750 (Uplink) Ch. 10700 (Downlink)
4. Check WCDMA Block
Agillent 8960 : Test mode(GSM) Ch. 62, P.L. 7 level setting Ch. 62, -60dBm setting
5. Check GSM Block
Redownload SW, Cal
- 132 - 4. TROUBLE SHOOTING
4.16 Checking Common Power Source Block
➂ Step 2 GSM PAM Block
➀ Step 1 Regulator Block
➃ Vincenne
Step 3 WCDMA PAM Block
➁ ➄
Power Source Block
(Bottom) (Top)
Figure 4-16-1. Common Source Block
- 133 - 4. TROUBLE SHOOTING
4.16 Checking Common Power Source Block Diagram
VBAT Vincenne 0.1ohm PASENSE+ VBATI VDDRTC VDDBUF VBAT_A VDD_D VBAT_C (2.75V/200mA) VDDBUCK R VDDPA SWBUCK L VSSBUCK
VDD_E PBUCK (1.8V/100mA) NBUCK DCIO
VDD_B VBUCK VDD_A VDD_IO VCORE(1.5V) VDD_D
2.75V Ingela VCCA
VCCB 2.75V Wopy Herta VDIG 2.75V VBATI
WIVI REG 2.8V V_wivi_A N101 V_wivi_B GSM PAM
VCC UMTS PAM VCCBIAS DCDC VCC N301 RF
- 134 - 4. TROUBLE SHOOTING
4.16.1 Step 1
Check VBATI (R105) LP3981ILD-2.8
Figure 4-16-2. Step 1 : Regulator Block ➀
Check point R875 (C740) R847
Figure 4-16-3. Power Source Block ➄
Step 1 3.7V No Check Point (C740) in OK? Power Source Block ➄ Yes To Check Power source to Check if See The Step 2 main power source input or not
Check Point (R847) No 3.7V Check The PowerSupply in Power Source Block ➄ OK? To Check Power source Yes
Check (C740 & R847) in Block ➀➄ to check inner line No connection Short? Change Board From C740 to R847 Yes
Soldering Check Component (R847 & R875) In Power Source Block ➄
- 135 - 4. TROUBLE SHOOTING
4.16.2 Step 2
➁ GSM PAM
VBATI (R407) FL401
(Top)
Figure 4-16-4. Step 2 :GSM PAM Block ➁
Step 2 Check VBATI (R407) 3.7V No in GSM PAM Block➁ OK? to Check if main power source input or not Yes
See The Step 3
Check FL401 to check if power 3.7V No OK? source input or not Yes
Check FL401 & R407 No Short ? inner Line connection Change Board Yes
Change FL401
Check Point (C740) No in Power Source Block ➄ 3.7V OK? Check The PowerSupply To Check Power source Yes Check (C740 & R105) No in Block ➀➄ Short? Change Board to check inner line connection From C740 to R105 Yes
Soldering Check Component (R847 & R875) In Power Source Block ➄
- 136 - 4. TROUBLE SHOOTING
4.16.3 Step 3
WCDMA PAM
VBATI (R307)
Figure 4-16-5. Step 3 :WCDMA PAM Block ➂
Check point R875 (C740) R847
Figure 4-16-6. PAM Power Source ➄
Step 3 3.7V No Check VBATI (R307) OK?
in WCDMA PAM Block➂ Yes
See The Next Page
Check Point (C740) No 3.7V Check The PowerSupply in Power Source Block ➄ OK? To Check Power source Yes
Check (C740 & R105) No in Block ➂ ,➄ Short ? to check inner line connection Change Board From R307 to R105 Yes
Soldering Check Component (R847 & R875) In Power Source Block➄
- 137 - 4. TROUBLE SHOOTING
VDDB (R2251)
VDDA (R2250) Bottom Top
Figure 4-16-7. Power for Radio ASIC
R2250 Ingela(N405)
Vincenne 0 (N503) R2251 0 Wopy (N201) C116 C117 C115 10u 10u 10u 2012 2012 2012
2.75V OK? Check the Vincenne No Yes
Check Point 2.75V OK? Check the Vincenne (VDDB) No Yes
Common Input Power is OK See The Next Part
- 138 - 4. TROUBLE SHOOTING
4.16.5 Checking Regulator Part
V_ wivi_B ➁ (R104)
➃ V_ wivi_A EXTLDO (R106) ➂ (R103) LP3981ILD-2.8 Regulator
Figure 4-16-8. Regulator Block
➂ R106
➃ 0 >> V_wivi_A TXTLDO >> R103 0 ➁ R104 N101 LP3981ILD-2.8 1 6 VOUT VEN 0 >> V_wivi_B
R105 2 5 VBATI >> VIN BYPASS 0 3 4 VOUT_SE GND1 C113 C114 C112 GND2
0.1u 10u 7 0.033u 2012
Figure 4-16-9. Regulator Circuit Diagram
Check Point ➁ or ➂ No No (R106) (R108) 2.8V OK? Point ➃ High? Change the Board To Check Regulator Output Voltage Yes Yes Check EXTLOD Point➃ To Check Regula tor Circuit is OK, Change the Regula tor regulator enable See the next Page signal
- 139 - 4. TROUBLE SHOOTING
4.17 Checking VCXO Block
The reference frequency (13MHz) from B201 (Crystal) is used WCDMA TX part and BB part. Therefore you have to check below 3 point.
Check 3
Check 2
Check 1
Figure 4-17-1. Bottom Place
- 140 - 4. TROUBLE SHOOTING
Check 1. Crystal part
If you already check this crystal part, you can skip check 1.
B201.3
Figure 4-17-2. Test Point (Crystal Part)
C231 C230 R216 R212 VCXOCONT 47p 330p 10K 1K C234 C232 C224 R214
V201 NA
2.7p 4.7p 0.01u R213 B201 BBY58-02W NA TSX-8A 4 3 HOT2 GND2 C233
2 GND1 HOT1 1 NA R211 13MHz 56p R217 B201.3 10K
Figure 4-17-3. Schematic of the Crystal Part
Figure 4-17-4. 13MHz at B201.3
- 141 - 4. TROUBLE SHOOTING
Check 2. 13MHz at TX part
N304.B1 N304.C1
Figure 4-17-5. Test point (13MHz at TX part)
C331 C332 TP301 TP302 22p 0.01u
XOOA XOOB TP303 TP304 TP305 TP306
A1 QINBAR A2 TXQB QIN A3 TXQA INBAR A4 TXIB IN TXIA N304.B1 N304.C1
Figure 4-17-6. Schematic of the Tx Part
Figure 4-17-7. 13MHz at N304.B1,C1
- 142 - 4. TROUBLE SHOOTING
Check 3. 13MHz at BB part
N201.C1
Figure 4-17-8. Test point (13MHz at BB part)
N201.C1
R210 MCLK 0
L208 1uH C221 82p
C219 0.01u C223 0.01u
R215 VDD_B 10 C225 22p
C231 C230 R216 R212 C7 C6 VCXOCONT 47p 330p 10K 1K C234 MCLK
GNDLF 2.7p B10 VCCREF C10 XOIA D10
Figure 4-17-9. Schematic (13MHz at BB Part)
Figure 4-17-10. 13MHz at N201.C1
- 143 - 4. TROUBLE SHOOTING
Check B201.3 Checking 1 No VCXO part has a problem. Refer to graph 4-17-4 13MHz at VCXO Changing B201
Yes
Check N304.B1 & C1 Checking 2 No N304 has any problem. Refer to graph 4-17-7 13MH z at TX part Changing RF board
Yes
Check N304.C1 Checking 3 No N304 has any problem. Refer to graph 4-17-10 13MHz at BB part Changing RF board
VCXO part is O.K. Check next stage
- 144 - 4. TROUBLE SHOOTING
4.18 Checking Ant. SW Module Block
ANTSW2 ANTSW1 ANTSW0
LMSP43MA-288
ANTSW3
Figure 4-18-1. Antenna Switch Block(Bottom)
FL101
LMSP43MA-288 7
1
ANT GSM900_RX 2 GSM1800_RX 10 3 VDD GSM1900_RX
9 4 VC1 WCDMA 8 VC2 5 VCG 12 GSM18001900_TX 13 L105 GSM900_TX
ANTSW0 GND5 GND4 GND3 GND2 GND1 6 16 15 14 11
L104 ANTSW1
L103 ANTSW2
R102 ANTSW3 0
C110 C107 C106 C109C105 C108 C102 C104 0.01u 10p 10p 0.01u 10p 0.01u 0.01u 10p
Figure 4-18-2. Schematic of Antenna Switch Block(Bottom)
- 145 - 4. TROUBLE SHOOTING
4.19 Checking Antenna Switch Block input logic
4.19.1 Mode Logic by TP Command
WCDMA & EGSM Rx EGSM Tx
ANTSW1
Low Low ANTSW2 Low Low
High ANTSW3 Low
DCS Tx DCS Rx
ANTSW1 High Low
ANTSW2 High High
Low Low ANTSW3
PCS Rx
ANTSW1 High
ANTSW2
ANTSW3 Low
Low
- 146 - 4. TROUBLE SHOOTING
Band ANTSW0 ANTSW1 ANTSW2 ANTSW3
EGSM Tx H L L H
EGSM Rx H L L L
DCS Tx H H H L
DCS Rx H L H L
PCS RX H H L L
WCDMA H L L L
Figure 4-19-1. Antenna Switch Module Logic
- 147 - 4. TROUBLE SHOOTING
4.19.2 Checking Switch Block power source * Before Checking this part, must check common power source(through Vincenne) part
TP Command MODE=0 SWRX=64,1024,2
No Check Soldering Open? It is necessary to check short condition. Using Tester. Check 4 resistor Yes ANTSW0(L105),ANTSW1(L104) Check soldering ANTSW2(L103),ANTSW3(R102) (L105)
No No High? OK? Resoldering Check ANTSW0(L105) To check Switch input power source Yes Yes
Check each mode Change the Board By TP command
- 148 - 4. TROUBLE SHOOTING
A. EGSM Rx mode
EGSM Rx MODE=0 SWRX=64,1024,2
ANTSW1 LOW
ANTSW2 LOW
ANTSW3 High
Figure 4-19-2. EGSM Rx Mode
B. EGSM Tx mode
EGSM Tx MODE=0 SWTX=1,64,7,1024,1
ANTSW1 LOW
ANTSW2 LOW
ANTSW3 High
Figure 4-19-3. EGSM Tx Mode
- 149 - 4. TROUBLE SHOOTING
C. DCS Rx mode
DCS Rx
MODE=2 SWRX=699,1024,2
ANTSW1 LOW
ANTSW2 High
ANTSW3 LOW
Figure 4-19-4. DCS Rx Mode
D. PCS Rx mode
PCS Rx MODE=1 SWRX=661,1024,2
ANTSW1 High
ANTSW2
LOW ANTSW3
LOW
Figure 4-19-5. PCS Rx Mode
- 150 - 4. TROUBLE SHOOTING
E. DCS / PCS Tx mode
DCS / PCS Tx MODE=2 SWTX=1,699,0,1024,1
ANTSW1 High
High ANTSW2
LOW ANTSW3
Figure 4-19-6. DCS / PCS Tx Mode
- 151 - 4. TROUBLE SHOOTING
F. WCDMA mode
WCDMA Mode
MODE=4 WTXC=9750,1,1,43,0,0,255,68
ANTSW1 LOW
ANTSW2 LOW
LOW ANTSW3
Figure 4-19-7. WCDMA Mode
No Each Mode Check MARITA(D601) Logic OK?
Yes
Input Signal and Power to Antenna Switch Block is OK. See the Next Page
- 152 - 4. TROUBLE SHOOTING
4.20 Checking WCDMA Block
start
1. Check VCXO Block ➁
2. Check Ant. SW Module
➆
3. Check ➀ Control Signal ➂
Bottom View 4. Check RF TX Level
5. Check ➃ PAM Block ➄
6. Check Top View RX IQ
7. Check RF RX Level
Redownload SW, Cal
- 153 - 4. TROUBLE SHOOTING
4.20.1 Checking VCXO Block
Refer to 4.17
4.20.2 Checking Ant. SW module
Refer to 4.18
4.20.3 Checking Control Signal
First of all, you have to check control signal. (data, clk, strobe)
TP203(CLK) TP202(DATA) TP201(STROBE)
Figure 4-20-1. Test point (Control Signal)
B1 IFOUTB C1 VCCMIX D1 MIXINA E1 MIXINB F1 GNDBIAS G1 L204 C211 GNDEME H1 N201 RFIN WCDMA_RX J1 LZT-108-5323 2.2nH 22p GNDBYP K1 VCCRF C3 GNDIF L205 D3 DATA NA E3 L203 CLK F3 STROBE G3 5.6nH GLNA
C209 C210 3.3p 3.3p VTUNE VCCVCO VCCRFLO INDBYP RFOUT VCCPLL VCCPHD PHDOUT RFLOOB XOOON RXON GNDPLL K7 K8 K9 K2 K3 K4 K5 K6 H3 H4 H5 K10
C212 22p
L206 NA R205
R206 0 5.6K C216 C213 NA TP202 TP203 TP201 390p
WDAT
WCLK
WSTR
GPRFCTRL
R208 CLKREQ 100 FROM MARITA SIDE FOR POWER SAVING
Figure 4-20-2. Schematic (Control Signal)
- 154 - 4. TROUBLE SHOOTING
TP201(STROBE)
TP202(DATA)
TP203(CLK)
TP201(STROBE)
TP202(DATA)
TP203(CLK)
Figure 4-20-3. Control Signal
Check TP2011,TP202 TP203. Check shape No and pk-pk level Similar ? Download the SW Refer to Graph 4-30
After downloading Yes If signal is not OK Change the D701 Control Signal is O.K. Check next stage
- 155 - 4. TROUBLE SHOOTING
4.20.4 Checking RF TX Level
Check 1 W101
Check 2 FL101.C103 Switch Output
Check 6 N302.C307 PAM Input Check 3 FL102.C111
Check 5 Check 4 N303.Isolator Input N303. Isolator Output
Figure 4-20-4. Test point (RF TX Level)
Fig. 4-20-5 Output Level at RF test connector Fig. 4-20-6 Output Level at Switch Output ( W101 ) (FL101 , C103)
- 156 - 4. TROUBLE SHOOTING
Fig. 4-20-7 Output Level at FL102.C111 Fig. 4-20-8 Output Level at Isolator Output (N303.Out )
Fig. 4-20-9 Output Level at Isolator Input Fig. 4-20-10 Output Level at PAM Input ( N303. In) ( N302,C307)
Fig. 4-20-11 Output Level at Wivi Output ( N304.C320)
- 157 - 4. TROUBLE SHOOTING
To verify that the phone fulfils requirments on maximum output power.
Set the FDD Test of the Agillent 8960 Set the Maximum Power
Check output power at Yes the W101 with antenna Check 1 RF TX Level is OK Cable. About 23dBm? Check next stage. Refer to Graph 4-20-5
No Check the power at Yes the FL101.C103 with probe. Check 2 The W101 has any problem. Refer to Graph 4-20-6 About 15dBm? Change the W101
No Check the power at Yes the FL102.C111 with probe. Check 3 The FL101 will be broken. Refer to Graph 4-20-7 About 19dBm? Change the FL101
No
Check the power at Yes the N303.out with probe. Check 4 The FL102 has any problem. Refer to Graph 4-20-8 About 19dBm? Change the FL102
No
Check the power at Yes the N303.In with probe. Check 5 The N303 has any problem. Refer to Graph 4-20-9 About 17dBm? Change the N303
No Check the power at Yes the N302.C307 with probe. Check 6 The N302 has any problem. Refer to Graph 4-20-10 About -6dBm? You have to check PAM block.
No
The N304 will be not operated. Change the board
- 158 - 4. TROUBLE SHOOTING
4.20.5 Checking PAM Block
(Top)
VCCWPA WDCDCREF (C302) (C310) from Rosaili
Rosaili WCDMA PAM
Comp(R301) Wivi input WPAREF Duplexer Output (C307) (R306) (C111)
Figure 4-20-12. Test point
- 159 - 4. TROUBLE SHOOTING
WCDMA_TX GND4 GND3 GND5 IN OUT N303 GND1 GND2 ESI-3EAR1.950G01-T
VCCWPA
N302 RF9266 10 11 9 GND4 GND3
GND5 VDETECT 12 8 VBATI GND6 VCC_DET 13 7
GND7 GND2 14 6 R307 VCC21 VCC_BIAS2 15 5 0 C308 VCC22 VCC_BIAS1 16 4 0.01u GND8 GND1 17 3 VCC11 VCTRL2 18 2 R306 VCC12 VCTRL1 19 1 WPAREF 0 C311 C310 GND10 GND11 10p 0.1u GND9 RFINC309 RFOUT 22p 22 23 20 21
Figure 4-20-13. Schematic(PAM)
VBATI
N301 WDCDCREF MAX1820ZEBC A1 B1 _SKIP SYNC A2 C1 COMP _SHDN VCCWPA A3 C2 OUT BATT 3838 L304 A4 C3 R303 R301 REF LX 4.7uH WPOWERSENSE 33K 39K B4 C4 GND PGND C303 C304 L301 10u R302 C302 2012 10u 2012 C305 C306 22p 10u 2012 L303 100K 1000p C301 330p L302
Figure 4-20-14. Schematic(DC-DC convertor:Rosaili)
- 160 - 4. TROUBLE SHOOTING
TP Command -mode =4 -wtxc = 9750,1,1,43,0,0,255,68
Check Duplex output No Level No (C111) 23dBm ? < - Download the SW To Check PAM 10dBm? & Calibrate output Yes Yes
WCDMA PAM is OK See the Next page
No Check C307 Level Check the WCDMA RF Tx Chip(Wivi) To Check PAM Input >2dBm level Yes
Check R306 No Check the Vincenne To Check PAM control 2.5V ? signal from Vincenne to WCDMA PAM Signal line (WPAREF) Yes
Check C310 No Change To Check PAM VCC 3.4V ? 2.5V ? No the Rosaili BIAS from DC/DC convertor Yes Check R301 (VCCWPA) To Check DC/DC Change The PAM convertor COMP
- 161 - 4.20.6 Checking RX I,Q
To verify the RX path you have to check the pk-pk level and the shape of the RX I,Q.
N201.A7 (RXQA) C227 N201.A8 (RXQB) C229 N201.A9 (RXIA) C228 N201.A10 (RXIB) C226
Figure 4-20-15. WCDMA RF RX IC (Bottom)
About 2 MHz
Feed a CW signal at 2142MHz with a power level of ñ60dBm.
Figure 4-20-16. RX I,Q signal (CW:2142MHz)
About 1 MHz
Feed a CW signal at 2141MHz with a power level of ñ60dBm.
Figure 4-20-17. RX I,Q signal (CW:2141MHz)
- 162 - N201.A7 (RXQA) C227
N201.A8 (RXQB) C229
N201.A9 (RXIA) C228
N201.A10 (RXIB) C226
Figure 4-20-18. RX I, Q signal
Set the CW Mode of the Agillent 8960 Feed a CW signal at 2141MHz Set the RX Continuous mode
Check the pk-pk level at No N201.A7~A10 with About 120mVp-p? Change Wopy (N201) Oscilloscope. Refer to
Yes Check the Mean level at No N201.A7~A10 with About 160mV? Change Wopy (N201) Oscilloscope. Refer to
Yes Check the frequency at No N201.A7~A10 with About 1MHz? Change Wopy (N201) Oscilloscope. Refer to
Yes Verify whether the signal No was similar as Graph Similar? Change Wopy (N201) at N201.A7~A10 with Oscilloscope.
Yes
Check Next Stage
- 163 - 4. TROUBLE SHOOTING
4.21 Checking GSM Block
start
1. Check Regulator Circuit
➂ 2. Check VCXO Block
3. Check Ant. SW Module ➁ ➀
4. Check Control Signal ➄➅
5. Check ➃ RF TX Path
6. Check RF RX Path
Redownload SW, Cal
- 164 - 4. TROUBLE SHOOTING
4.21.1 Checking Regulator Circuit Refer to 4.16 Checking Power Source block IF you already check this point while checking power source block , You can skip this test.
4.21.2 Checking VCXO Block Refer to 4.17 Checking VCXO block IF you already check this point while checking VCXO block , You can skip this test.
4.21.3 Checking Ant. SW Module Refer to 4.18 Checking Ant. SW Module IF you already check this point while checking Ant. SW module , You can skip this test.
- 165 - 4. TROUBLE SHOOTING
4.21.4 Checking Control Signal
Test Program Script
MODE=0 SWTX=1,64,7,1024,1
TXON VDD_A (R421) ➀ (C426)
VDD_A VDD_A (L416) (L411)
RADDAT (TP408) ➂ LPF block RADSTR (TP407) ➁ Vtune (C448) RADCL K(TP40 6)
➀ C433 C427 22p 22p
R421 TXON 0 R412 RXON
BSEL0 D3 H1 F1 K1 J1 G1 C3 G3 F3 E3 E1 D1 C1 B1 PCTL BSEL TXON RFHB RFHA
K2 RXON A1 TXOLA TXOLB NC5 TXOHA TXOHB RFHD GNDRF2 GNDRF1 K3 VCCBUF A2 MODA RFHC K4 A3 MODB GNDPLANE GNDRF K5 A4 MODC RFLB K6 A5 MODD RFLA K7 A6 VCCPLLN405 VCCRF K8 A7 XOOB LZT-108-5325 QRB K9 A8 XOOC QRA K10 A9 NC6 IRB H3 A10 GNDBUF IRA H4 C4 NC3 REON H5 C5 PS CLK H6 C6 GNDPLL DATA H7 C7 XOOLA STROBE VTUNE VCCVCO NC2 NC1 NC4 GNDVCO5 GNDVCO4 GNDVCO3 GNDVCO6 PHDOUT GNDSILENT GNDVAR GNDVCO2 GNDVCO1 F8 E8 H8 D8 C8 G8 J10 F10 E10 H10 D10 C10 B10 G10
TP406
L413 2012 TP408
100uH ➁ TP407 C444 R425 R426 R427 L414
560 1800p 120 390 C439 C445 C447 C448 C450 C449 0.01u 1200p 560p 330p ➂ 22p 0.01u
- 166 - 4. TROUBLE SHOOTING
Figure 4-21-1. GSM RF Control signal
Check TP406,TP408,TP407. Check if there is any Major difference. Refer to left side of Figure 4-21-1
No No Similar? Short? Redownload SW
Yes Yes
Change the board
Check R421,C448. Check if there is any Major difference. Refer to right side of Figure 4-21-1 No No Resoldering VDD_A block Similar? Short? (L416, L411, L414, R409)
Yes Yes
Control signal is OK. Resoldering LPF block See next page to check
- 167 - 4. TROUBLE SHOOTING
4.21.5 Checking RF Tx Path
A. GSM Tx path Level
Figure 4-21-2. GSM/DCS/PCS Tx Path Level
- 168 - 4. TROUBLE SHOOTING
➀ ➃' ➃
N404 N403 N401 ➂ ➂' ➄
➁ ➄'
N405
Figure 4-21-3. Test Point of GSM/DCS/PCS Tx Path
➀ W101 KMS-507 C103 L101 G2 R101 0 RF ANT ANTPAD101 G1 33p 1.8nH
L102 FL101 C101 8.2nH LMSP43MA-288 7 1.2p 1
ANT GSM900_RX 2 GSM1800_RX 10 3 VDD GSM1900_RX
9 4 VC1 WCDMA 8 VC2 5 VCG 12 GSM18001900_TX 13 GSM900_TX GSM_RX GND5 GND4 GND3 GND2 GND1
6 DCS_RX 16 15 14 11 PCS_RX
DCS_TX GSM_TX
- 169 - 4. TROUBLE SHOOTING
B. GSM Tx Output Level Check
Figure 4-21-4. GSM/DCS/PCS Tx Level at ➀
Test Program Script
1. GSM Tx 2. DCS Tx 3. PCS Tx MODE=0 MODE=2 MODE=1 SWTX=1,64,5,1024,1 SWTX=1,699,0,1024,1 SWTX=1,661,0,1024,1
v Agilent 8960 Setting : GSM BCH+TCH Mode v Oscilloscope Setting
Check GSM/DCS/PCS output power at ➀ . Check if there is any Major difference. No Refer to Figure 4-21-4. Similar? See Next page to check Tx path GSM>32dBm DCS>29dBm Yes PCS>29dBm
GSM/DCS/PCS Tx path OK. See Chapter 4.21.6 to check Rx path
- 170 - 4. TROUBLE SHOOTING
C. GSM RF Transceiver IN/OUT Signal Check
DCS/PCS Tx GSM Tx (R414) ➃ (R418)
N404
MODA N403 (R410) GSM Tx ➁ MODB (L406) (R411) ➂ MODC (R424) DCS/PCS Tx MODD (L405) (R423)
N404 LDB21897M15C
4 R418 B2 1 UB 3 0 B1 NC
GND1 GND2 L406 R419 2 5 6 33nH NA C429
33p
R417 0 ➃ ➂
L404 75 N403 LDB211G8020C BLM15BB750SN1J 4 R414 B2 1 UB 18 3 B1 NC
GND1 GND2 L405 R415 R416 2 5 6 22nH 270 270 C428 12p
L403
R410 MODA C425 100 R411 22p MODB 100 R424 D3 H1 F1 C3 K1 J1 G1 MODC G3 F3 E3 E1 D1 C1 B1 100 R423 MODD PCTL BSEL RFHB RFHA TXON 100 K2 RXON A1 TXOLA TXOLB NC5 TXOHA TXOHB RFHD GNDRF2 GNDRF1 K3 VCCBUF A2 MODA RFHC K4 A3 MODB GNDPLANE GNDRF K5 A4 MODC RFLB K6 A5 MODD RFLA K7 A6 VCCPLLN405 VCCRF K8 A7 ➁ XOOB LZT-108-5325 QRB K9 A8 XOOC QRA K10 A9 NC6 IRB H3 A10 GNDBUF IRA H4 C4 NC3 REON H5 C5 PS CLK H6 C6 GNDPLL DATA H7 C7 XOOLA STROBE VTUNE VCCVCO NC2 NC1 NC4 GNDVCO5 GNDVCO4 GNDVCO3 GNDVCO6 GNDSILENT PHDOUT GNDVAR GNDVCO2 GNDVCO1 F8 E8 H8 D8 C8 G8 J10 F10 E10 H10 D10 C10 B10 G10
- 171 - 4. TROUBLE SHOOTING
MODA
MODB
Figure 4-21-5. GSM/DCS/PCS Tx MODE signal
Check Mode(A/B/C/D)signal at ➁. No Similar? Resoldering MODE block Check if there is any Major (R423, R424, R411, R410) difference. Refer to Figure 4-21-5 Yes
Check GSM RF Transceiver No ➂ GSM/DCS/PCS Redownload SW Output power at . >5dBm
Yes
Check GSM/DCS Tx Balun Resoldering Tx Balun GSM/DCS/PCS No output power at ➃ . GSM : N404 >5dBm DCS/PCS : N403
Yes
See Next page to check Tx path
- 172 - 4. TROUBLE SHOOTING
D. GSM PAM Check
GSM Tx (C410)
Vapc (C406) ➄ DCS Tx (C409)
BLM15AB601SN1J L401 PAREG
R402 C401 3K R401 C402 IOUT 1K 100p 150p
➄
C406 C405 33p 100p 6 2 12 18
C407 VCC2 VCC1 NA VAPC
C410 VSUPPLY 10 3 GSM_TX EGSM_OUT DCS_PCS_IN 33p C411 0 15 4 DCS_TX DCS_PCS_OUT EGSM_IN 2.2nH R403 SKY77321 1 C409 TX_ENABLE 13 N401 5 NA RSVD BS PGND GND7 GND6 GND5 GND4 GND3 GND2 GND1 9 8 7 11 19 17 16 14
- 173 - 4. TROUBLE SHOOTING
TXON TXON
Vapc (GSM) Vapc (DCS/PCS)
Figure 4-21-6. GSM Tx control signal Figure 4-21-7. DCS/PCS Tx control signal
Check Vapc level. Check if there is any Major No Vapc>1.5 V? Redownload SW, Cal difference. Refer to Graph 4-21-6/7 Yes
Check GSM/DCS PAM GSM:33.5dBm No Changing GSM PAM output power at ➄ . DCS: 31.0dBm (N401)
Yes
GSM Tx path OK. See Next page to check
- 174 - 4. TROUBLE SHOOTING
4.21.5 Checking RF Tx Path
A. GSM Tx path Level GSM Herta PD Pre- Clk ADC ADC scaler 2.5Vpp GSM/DCS/PCS I/Q Level : I/Q ➀ filter Loop GSM Ingela ➁ Q+/Q- : 200mVpp / /I- GSM/DCS/PCS I/Q Level I+ SAW DCS RX FL402 GSM RX SAW GSM RX Z401 GSM Rx : Ch64, -50dBm, CW GSM Rx : Ch64, -50dBm, : Ch699, -50dBm, CW DCS/PCS Rx ' ➂ FEC1G96FA0F00 ➂ GSM : -.51.5dBm PCS RX SAW RX PCS SA DCS/PCS: -51.5dBm GSM -50dBm : DCS-50dBm : 507 nna SW module nna SW te Mobile Switch Mobile KMS- nna An LMSP43MA-288 Ante
Figure 4-21-2. GSM/DCS/PCS Tx Path Level
- 175 - 4. TROUBLE SHOOTING
FL402 ➂'
➀ FL403
N405 Z401
➂
➁
Test Program Script
1. GSM Tx 2. DCS/PCS Tx MODE=0 MODE=2(DCS),1(PCS) SWTX=1,64,5,1024,1 SWTX=1,699,0,1024,1
v Agilent 8960 Setting CW Mode GSM : -50dBm@Ch65(948MHz) DCS : -50dBm@Ch700(1842.8MHz) PCS : -50dBm@ch700(1889.0MHz) v Oscilloscope Setting
- 176 - 4. TROUBLE SHOOTING
B. GSM I/Q Signal Check
Idata (TP402) ➀ DCLK (TP403) QRB (R428) Qdata (TP404) QRA (R429) ➁
IRA (R430)
IRB (R431)
TP404 TP402 TP403 N402 LZN-901-0536-R1A ➀ F1 AVDD D3 I2CDAT D1 D5 I2CCLK QDAT G8 A4 QDATA SYSCLK2_MCLK IDAT IDATA D2 C5 RESETON_RESETB DCLK DCLK A8 IRA A7 IRB A6 H4 QRA AUXO2 A5 G5 QRB BEARP B4 H5 RXSTR BEARN G7 PCMUL E4 E6 AUXI1 GPDAT F2 E5 CCO GPCLK F3 C3 D3 H1 F1 K1 J1 G1 G3 F3 E3 E1 D1 C1 B1 MICIP G1 C3 MICIN DAC01 ➁ B8 B3 GPA0 DAC02 PCTL BSEL B6 A3 RFHB RFHA TXON
K2 RXON A1
TXOLA TXOLB GPA1 DAC03 NC5 TXOHA TXOHB RFHD C6 GNDRF2 GNDRF1 K3 VCCBUF A2 MODA RFHC GPA2 K4 A3 C7 MODB GNDPLANE GNDRF GPA3 K5 A4 C8 C2 MODC RFLB GPA4 DACCLK K6 A5 D6 C1 MODD RFLA GPA5 DACDAT K7 A6 D8 D4 VCCPLLN405 VCCRF GPA6 DACSTR K8 A7 R430 D7 XOOB LZT-108-5325 QRB GPA7 K9 A8 0 R431 E2 XOOC QRA DEC1 K10 A9 0 R429 H7 H2 NC6 IRB PCMDL DEC2 H3 A10 0 R428 F6 H3 GNDBUF IRA PCMCLK DEC3 H4 C4 0 G6 B2 NC3 REON PCMSYN DEC4 H5 C5 E7 E1 PS CLK ADSTR DEC5 H6 C6 GNDPLL DATA H7 C7 E3 XOOLA STROBE REXT A1 A2 NC4 VTUNE VCCVCO NC2 NC1 GNDVAR GNDSILENT GNDVCO1 GNDVCO2 GNDVCO5 GNDVCO4 GNDVCO3 GNDVCO6 PHDOUT R405 VSS1 VDD1 100K B1 B5 VSS2 VDD2 C4 B7 F8 E8 H8 D8 C8 G8 J10
F10 VSS3 VDD3 E10 H10 D10 C10 B10 G10 E8 F5 VSS4 VDD4 F4 F8 VSS5 VDD5 F7 H6 VSS6 VDD6 G3 VSS7 G4 G2 VSS8 NC1 H8 H1 VSS9 NC2
- 177 - I Data QRB QRA
Q Data IRB IRA DCLK
Figure 4-21-9. Herta IQ data and DCLK Figure 4-21-10. Ingela IQ signal
QRB
QRA
Figure 4-21-11. Ingela IQ signal
- 178 - v Agilent 8960 Setting CW Mode GSM : -50dBm@Ch65(948MHz) DCS : -50dBm@Ch700(1842.8MHz) PCS : -50dBm@ch700(1889.0MHz) v Oscilloscope Setting
Check GSM/DCS/PCS Rx IQ data at➀ . No Check if there is any Similar? Redownload SW, Cal Major difference. Refer to Graph 4-21-9. Yes
Check GSM/DCS/PCS Rx IQ IQ signal No signal level at ➁ : 200mV? See Next page to check Rx path Refer to Graph 4-21-10. Yes
GSM Rx path OK. See Next page to check
- 179 - C. GSM RF Level Check
➂' FL402
➂' FL403
Z401
➂
Figure 4-21-12. GSM/DCS/PCS Rx path
Z401 SAFEC942MFL0F00
FL402 FL403 SAFEC1G84FA0F00 SAFEC1G96FA0F00 3 2 C431 3 2 3 2 O1 G1 O1 G1 C437 O1 G1 C412 1 1 1 IN IN IN O2 G2 DCS_RX O2 G2 PCS_RX O2 G2 GSM_RX 33p 1.5nH 33p 4 5 4 5 4 5
v Agilent 8960 Setting CW Mode GSM : -50dBm@Ch65(948MHz) DCS : -50dBm@Ch700(1842.8MHz) PCS : -50dBm@ch700(1889.0MHz)
Check GSM/DCS/PCS Rx signal level at ➂ . GSM:-51.5dBm No Change Ant. SW module DCS/PCS:-51.5dBm (N1000)
Yes
GSM Rx path OK.
- 180 - 4.22 Checking Bluetooth Block
➁
➀
start
1. Check BT Regulator Block
2. Check BT Chip Block
** BT - Bluetooth
- 181 - VDIG VBATI
VBT VTF R2171 R2192 100K 0 U510 R2186 1 5 75 VDD VOUT 2 GND R2179 R599 0 3 4 75 BTF_REG_EN CE NC
R2177 C1899 R1131N281D5-TR-F C594 C1915 NA 4.7u 4.7u 1608 NA 1608
BT and T-Flash Regulator-2.85V
U604 BGB202_S2 R650 22K 25 15 CLKREQ GPIO10 GP_CLK 30 REF_CLK
R651 0 45 50 RESOUT2n RESET_N TCK_JTAG 47 TMS_JTAG 49 TDI_JTAG 44 48 UARTRTS3 GPIO2_CTS_UART TDO_JTAG 41 UARTCTS3 GPIO3_RTS_UART 43 21 UARTRX3 GPIO4_TXD_UART GPIO0 42 20 UARTTX3 GPIO5_RXD_UART GPIO1 4 6 35 PCMDATB GPIO6_DA_IP C647 22p 2 33 2 1 GND2 GND4 R656 33p L602 33p
PCMSYN GPIO7_FSC_IP ANT IN FEED NC2 36 17 OUT PCMCLK GPIO8_DCLK_IP VANLI NC1 GND3 34 22 GND1 PCMDATA GPIO9_DB_IP VANLO 5 16 3 CN601 L601 27nH ANT601 VBAT C643 100p 29 MCLK XTAL1_SYS MM8430-2600B R652 120K 28 1 XTAL2_SYS GND1 120K 3 GND2 C642 100p 19 4 RTCCLK XTAL1_LPO GND3 18 5 XTAL2_LPO GND4 6 GND5 24 7 GPIO11 GND6 31 8 GPIO12 GND7 23 9 GPIO13 GND8 Bluetooth (BGB202/S2) ➁ VBT 32 10 GPIO14 GND9 11 GND10 39 12 VDDIORF GND11 38 13 VDD_IOV GND12 14 GND13 R648 1 27 51 POR_DISABLE GND14 2012 40 52 VREG18 GND15 37 53 VDD18 PGND R649 NA
C646 C640 1_8V_DECOUP1 1_8V_DECOUP2 0.1u 10u 2012 26 46 ➀ C641 C645 0.1u 0.1u
VBT C646
MCLK C643 Bluetooth Antenna ANT601
RTCCLK C642
Bluetooth chip Output C647
BTF_REG_EN R599
VBT at Regulator output R2186
- 182 - Checking Bluetooth Regulator Block
TP Command -pctr = 3,4,1 -pdin = 3,4 BTF_REG_EN R599 -pdou = 3,4,1 -brts =1 -ltcx = 3 -dacc =0,2 responsed value -Btfa=1,1 -Btfa=1,2
VBT at Regulator output R2186
Check voltage level at No BTF_REG_EN . R599 About 2.85V? Check Marita (D601) with Oscilloscope
Yes
No About Check voltage level 2.85V? Change Regulator(U510) At VBT.R2186 with Oscilloscope
Yes
Check Next Stage
- 183 - Checking Bluetooth Block
TP Command E5515C 8960 setting -pctr = 3,4,1 -Center Frequency => 2441MHz -pdin = 3,4 -Span =500kHz -pdou = 3,4,1 -brst =1 VBT C646 -ltcx = 3 → LTCX=response value,OK -dacc =0,2 response value MCLK C643 -Btfa=1,1 -Btfa=1,2 -Btsr=2 RTCCLK C642
Bluetooth chip Output C647
Check voltage level at No VBT . C646 2.85V? Check BT regulator Block with Oscilloscope
Yes
No Check frequency at 13MHz ? Check VCXO block MCLK , C643 with Oscilloscope Yes
No 32.768k ? Check Marita Block ( D601 ) Check frequency at RTCCLK , C642 with Oscilloscope Yes
No Over Change BT Chip (U604) Check Power lever -40dBm ? at Bluetooth chip Output C647 with Oscilloscope
Yes
Check Next Stage
- 184 - 5. BLOCK DIAGRAM
5.1 GSM & WCDMA RF Block
UMTS UMTS IF Filter UMTS RF Filter Z201 FL201 Duplexer FL102 VCO UMTS Receiver Antenna N201(Wopy) XO D701 Wanda UMTS PAM VCO Isolator N302 UMTS TX Filter Test Conn. Tank W101 N303 FL301
UMTS Transmitter DCDC N304(Wivi) N301
Varactor Crystal 3M-1 Switch V201 B201 FL101
GSM
DCS Rx Filter FL402 ADC PCS Rx Filter ADC FL403 GSM ADC N402 Z401 GSM Transceiver Clk Marita GSM RX Filter N405(Ingela) D601 Loop PD GSM PAM DCS/PCS Balun filter N401 N403 Pre- GSM Balun N404 scaler
Bluetooth Antenna
Test Conn. CN601 BGB202
Bluetooth U604
Figure 5-1-1. RF Block Diagram
- 185 - 5. BLOCK DIAGRAM
5. BLOCK DIAGRAM
Block Ref. Name Part Name Function Comment
Common FL101 LMSP43MA-288 Switch Band select
W101 KMS-507 Test Connector Calibration, etc
B201 TSX-8A_13MHz Crystal Reference -13M
WCDMA FL102 DFYY61G95LBNBC-TT1 Duplexer TRX
N201 LZT-108-5323 Receiver RX
FL201 SAFEH2G14FA0F00R00 RX RF Filter RX
Z201 TMXU753 RX IF Filter RX
N301 MAX1820ZEBC DC/DC TX
N302 RF9266 PAM TX
N303 ESMI-3EAL1.95G01-T Isolator TX
N304 LZT-108-5322 Transmitter TX
FL301 SAFEH1G95FL0F00R00 TX RF Filter TX
D701 ROP-101-3033_1 Analog Baseband TRX
GSM FL402 SAFEB1G84FA0F00 DCS RX Filter Direct Conversion
Z401 SAFEB942MFL0F00 GSM RX Filter Direct Conversion
FL403 SAFEB1G96FA0F00 PCS RX Filter Direct Conversion
N405 LZT-108-5325 Transceiver TRX
N401 SKY77321 PAM GSM/DCS/PCS Tri
N404 LDB21897M15C-003 GSM Balun TX
N403 LDB211G8020C-001 DCS/PCS Balun TX
D601 ROP-101-3035-_1 Modem
Bluetooth U604 BGB202_S2 Bluetooth
Table 5-1-1. RF Part Component List
- 186 - 5. BLOCK DIAGRAM
6. DOWNLOAD
6.1 The Purpose of Downloading Software
• To make a phone operate at the first manufacturing – A phone = Hardware + Software – A phone cannot operate with hardware alone. – The hardware with the suitable software can operate properly. • To upgrade the software of the phone – The software of the phone may be changed to enhance the performance of the phone. – The older version software of the phone can be replaced to the newer version. • Download Tools – FlashRW : Download tool for U8XX0 software
6.2 Download Environment Setup
U8550 UART data cable
USB cable
Figure 6-2-1. U8XX0 Download can be done via UART & USB
- 187 - 6. DOWNLOAD
6. DOWNLOAD
6.3 U8XXX Download 6.3.1. U8XXX Download(1) - FlashRW configuaration A. Execute FlashRW_V200_Red.exe B. Press the “Global Settings” on the top menu to configure FlashRW environment.
- 188 - 6. DOWNLOAD
C. Select Loader File for Product. You can use browse button to select Loader File. You must select only cxc1325414_R3V_u8550R. fldr for U8550. Loader File is provided with FlashRW.
D. Select Port configurations for both RS232 Port and USB Port. Baudrate should be 115200bps.
You have to do FlashRW configuration only at the first time of installation
- 189 - 6. DOWNLOAD
6.3.1. U8XXX Download(2) - Phone Model Selection A. Press Button for Model. B. Select Model U8120 for U8550.
- 190 - 6. DOWNLOAD
6.3.1. U8XXX Download(3) - Download file selection A. 1. Press “Add” button to select LGE SSW files to download. B. Don’t Press “Add1” button to select LGE GDFS file to download. If you download old released LGE GDFS file, The phone will break down. This “Add1” button will be used for upgraded if needed. Only When LGE propose this action, you must press this button.
- 191 - 6. DOWNLOAD
6.3.1. U8XXX Download(4) - Connect & Download A. Click on connector icon( ) to connect to the phone Check the Dialog Box that say “Please,switch on the target”. B. Connect the phone to PC via Cable for Downloading. Phone should be turned off. C. Turn the phone on to connect to PC.
A
- 192 - 6. DOWNLOAD
6.3.1. U8XXX Download(5) - USB Driver Install A. If you use FlashRW Tool firstly, Error will happen because of USB Driver uninstalled.
You have to do FlashRW USB Driver Installation only at the first time of installation
- 193 - 6. DOWNLOAD
B. Push “the Next Button” in Found New Hardware Wizard C. Select “Search for a suitable driver for my device” in Found New Hardware Wizard
- 194 - 6. DOWNLOAD
D. Select “Specify a location” in Found New Hardware Wizard E. Push “the Browse Button” , and then select “USB driver Information file” This File is provided with FlashRW.
- 195 - 6. DOWNLOAD
F. Push “the Next Button” in Found New Hardware Wizard G. Push “the Finish Button” in Found New Hardware Wizard
- 196 - 6. DOWNLOAD
H. Close FlashRW.exe I. Remove & Insert Main battery to reset the phone This action for USB Driver Install is done only at the first time of installation If you want to download Software, just do as same as U8XXX Download (4) - Connect & Download says
- 197 - 6. DOWNLOAD
6.3.1. U8XXX Download(6) - Connect & Download
< After Downloading finished >
- 198 - 6. DOWNLOAD
6.3.1. U8XXX Download(7) - Trouble shooting Check these questions when trouble happens. A. Check if UART & USB Port configuration is right. B. Do not change RS-232 baud rate(115200BPS). It is fixed and never changed. C. Check if UART & USB Cable is connected. D. You can’t select any GDFS File. If you do, Trouble will happen in the phone. E. Don’t disconnect downloading cable while downloading LGE SSW images into phone.
- 199 - 6. DOWNLOAD
7. CALIBRATION
7.1 General Description
This document describes the construction and the usage of the software used for the calibration of LG’s GSM/GPRS/WCDMA Multimedia Mobile Phone (U8550). The calibration menu and their results are displayed in PC terminal by Mobile phone. This calibration software includes GSM, DCS, WCDMA Band RF parts calibration and Battery calibration. This calibration software was called “XCALMON(eXtended CALibration and MONitor program )”. From now on, the calibration software will be called XCALMON in this document.
7.2 XCALMON Environment
7.2.1 H/W Environment
- PC with RS-232 Interface & GPIB card installed - GSM/GPRS/WCDMA Multimedia Mobile Set (U8550) - Agilent 8960 Series 10 E5515C Instrument (E1985B ver 04.08) - Tektronix PS2521G Power Supply - ETC (GPIB cable, Serial cable, RF cable, Power cable, Dummy battery)
7.2.2 S/W Environment
- National Instrument GPIB & VISA (ver 2.60 full) driver install - Agilent 8960 VXI driver(E1960) install - XCALMON EXE files - OS : Window98, Window2000, WindowXP - Serial port configuration : Baud rate: 115200 / Char length: 8bit / No Parity/ No Flow control Stop bits: 1 bit
7.2.3 Configuration Diagram of Calibration Environment
U8550
Figure 7-1. Calibration Configuration Figure
- 200 - 7. CALIBRATION
7.3 Calibration Explanation
7.3.1 Overview
In this section, it is explained each calibration item in the XCALMON. Also the explanation includes technical information such as basic formula of calibration and settings for key parameters in each calibration procedure. At first, when any of calibration is done, the results are displayed in the XCALMON result window and the result of calibration will be stored in GDFS(Global Data Flash Storage).
7.3.2 Calibration Items
A. EGSM 900 Band
- MODA-D(MD bit) Delay Calibration - RXVCO Varactor Operating Point Calibration - TXVCO Varactor Operating Point Calibration - TX Loop Bandwidth Calibration - VCXO Calibration - TX Power Calibration - RSSI and AGC Calibration
B. DCS 1800 Band
- RXVCO Varactor Operating Point Calibration - TXVCO Varactor Operating Point Calibration - TX Loop Bandwidth Calibration - TX Power Calibration - RSSI Calibration
C. WCDMA Band
- RF VCO Center Frequency Calibration - TX Carrier Suppression Calibration - TX LPF Bandwidth Calibration - TX Maximum Output Power Calibration - TX Power Table Calibration - TX Open Loop Power Control Calibration - RX LPF Bandwidth Calibration - RX LNA Gain Switch and AGC Hysteresis Calibration - RX AGC Gain Max and Rx RSSI Calibration
- 201 - 7. CALIBRATION
7.3.3 EGSM 900 Calibration Items
A. MOD-A(MD bit) Delay Calibration
- Purpose The procedure is designed to calibrate the timing alignment between the MODA-D signals and the reference signal (13 MHz). It also ensures that the MOD signals have stable values when they are clocked into the divider of the Phase-Locked Loop (PLL). - Procedure Proposal 1. Set the ME to mid channel in the GSM TX band. 2. Set the delay setting in default mode, that is, no delay. 3. Wait approximately 300 us to 400 us to allow the PLL to lock. 4. Measure the RMS phase error. A threshold value of > 20 deg indicates that the PLL is running in the forbidden time region. 5. Save the RMS phase error result locally. 6. Step up the delay setting according to Table 10.1 below. 7. Repeat from step 4. 8. Choose delay setting that gives maximum distance to the consecutive field of corrupted RMS phase error values in the vector. 9. Store delay setting both to the GD_RF_Mod_Delay and to the GD_DirMod_Mod_Delay. 10. Reset the radio.
Index DIMC MD [0] 0 00(0) [1] 0 01(1) [2] 0 10(2) [3] 0 11(3) [4] 1 00(0) [5] 1 01(1) [6] 1 10(2) [7] 1 11(3)
Table 7-1. Delay Settings for the MOD-A
- 202 - 7. CALIBRATION
B. RXVCO Varactor Operating Point Calibration
- Purpose To adjust the varactor diode to a pre-determined operating point, so that the loop voltage of the RXVCO (measured with an ADC in AB 2000) is within the valid range. This is necessary to secure that all RX channels can be reached. - Procedure Proposal 1. Put the ME in static RX mode. 2. Measure the loop voltage with the AB 2000 ADC for all CVCO settings, that is, 0 ~ 7. Find a CVCO value that fulfills the requirements on loop voltage for low and high channel. 3. If there are several CVCO values that fulfill the loop voltage requirements, then the optimum CVCO value is the one that centers the loop voltage within the specified limits. 4. Store the selected CVCO in the memory. (GD_ RX_VCO_Centre_Frequency_Adjustment_Band) 5 Reset the radio.
C. TXVCO Varactor Operating Point Calibration
- Purpose To adjust the varactor diode to a pre-determined operating point, so that the loop voltage of the TXVCO (measured with an ADC in AB 2000) is within the valid range. This is necessary to secure that all TX channels can be reached.
- Procedure Proposal 1. Put the phone in static TX mode. 2. Measure the loop voltage with the AB 2000 ADC for all CVCO settings, that is, 0 ~ 7. Find a CVCO value that fulfills the requirements on loop voltage for low and high channel. 3. If there are several CVCO values that fulfill the loop voltage requirements, then the optimum CVCO value is the one that centers the loop voltage within the specified limits. 4. Store the selected CVCO in the memory. (GD_TX_VCO_Centre_Frequency_Adjustment_Band) 5. Reset the radio.
D. TX Loop Bandwidth Calibration
- Purpose The loop bandwidth is calibrated to match the pre-filtering of the modulation in DB 2000 by adjusting the phase detector current. Note: This also indirectly adjusts the VCO gain that can otherwise not be calibrated. This will ensure a correct transfer function for the modulation and keep phase error to a minimum.
- 203 - 7. CALIBRATION
- Procedure Proposal 1. Put the ME in switched TX mode on mid channel in frequency interval 11 for EGSM (with random modulation). 2. Measure the RMS phase error at the RF connector. 3. Tune the phase detector current (IPHD) until the phase error is minimized. If two IPHD settings gave the same RMS, choose the lowest value. Measure 10 bursts for each value. 4. Calculate and store the IPHD values in GDFS (GD_IPHD_8Temperature_and_24Channel_Compensation_Band) 5. The offsets in the table are steps in the IPHD Table 10.2 and all offsets refer to the calibrated value (Trim) at mid channel in room temperature.
Frequency Interval 0123456789101112 13 14 15 16 17 18 19 20 21 22 23 0-2-2-2-2-1-1-1-1-10 0 00011 1 1 1 1 2 2 2 2 1-2-2-2-2-1-1-1-1-10 0 00011 1 1 1 1 2 2 2 2 2-2-2-2-2-1-1-1-1-10 0 00011 1 1 1 1 2 2 2 2 3-2-2-2-2-1-1-1-1-10 0 00011 1 1 1 1 2 2 2 2 5-2-2-2-2-1-1-1-1-10 0 00011 1 1 1 1 2 2 2 2 4-2-2-2-2-1-1-1-1-10 0 00011 1 1 1 1 2 2 2 2 6-2-2-2-2-1-1-1-1-10 0 00011 1 1 1 1 2 2 2 2 7-2-2-2-2-1-1-1-1-10 0 00011 1 1 1 1 2 2 2 2
Table 10-2. IPHD Compensation for EGSM Band
E. VCXO Calibration
- Purpose This procedure aims to calibrate the value of DAC3 to establish a VCXO-frequency that is sufficiently close to 13 MHz at room temperature. It also ensures that the VCXO tuning range is sufficient, and that the temperature compensation table for VCXO is completed accordingly. Note: The frequencies in this section are related to the 13 MHz VCXO-frequency. Depending on the calibration procedure, the 13 MHz VCXO frequency can be acquired by first measuring an EGSM, DCS, or W-CDMA RF frequency at the antenna and then translating the measured frequency to the 13 MHz VCXO frequency. - Procedure Proposal 1. Put the ME in switched low power TX mode with a modulated carrier on a mid channel. Use the calibrated value of the cap array and phase detector current. 2. Tune DAC3 in AB 2000 (VCXOCONT) to end and mid values, and check tuning range.
- 204 - 7. CALIBRATION
Acquire the following VCXO (13 MHz) frequencies: fmin = 13 MHz VCXO-frequency @ DAC3=1 fmid = 13 MHz VCXO-frequency @ DAC3=1024 fmax = 13 MHz VCXO-frequency @ DAC3=2047 Note that it is necessary to translate the measured RF-frequency (EGSM, DCS, or W-CDMA) to the 13 MHz VCXO-frequency. 3. Acquire the ME temperature, TCal, from the temperature sensor in ME. 4. Store fmin, fmid, fmax and TCal for calculation. 5. Calculate the DAC-value, VCXOCONTCal, that gives zero frequency error at the mid channel, using piecewise linear interpolation, and store the value in the memory (GD_RF_SYNT_CONFIG_ID and GD_VCXO) 6. Calculate K_LO = (fmid - fmin)/1023 K_HI = (fmax - fmid)/1023 Each value is then multiplied by 100 and rounded to nearest integer, with the results stored in the memory (GD_RF_SYNT_CONFIG_ID). AFC_DAC_STEP_LO = ROUND(100*K_LO) AFC_DAC_STEP_HI = ROUND(100*K_HI) where ROUND(x) = x rounded to the nearest integer.
F. TX Power Calibration
- Purpose These procedures describe how to tune the different power levels of the power amplifier to output powers corresponding to values in GSM 05.05, and explain how to calculate intermediate power levels that will ensure a good power versus time performance.
- Procedure Proposal 1. Reset the DIRMOD-block, and select a ‚mid channel using the trimmed value on the capacity array for VCO tuning and a default IPHD value as phase detector current. Turn on dummy burst modulation. 2. Use the Multi-burst method to characterize the relation between output power and the DACvalue. Then store the DAC values that give the closest approximations to the power targets defined in Table 10-3. 3. To avoid yield problems with the power template and switching transients spectrum a margin to the compression point of the PA should be observed. However, the output power must be kept within the tolerances specified in Table 10-3. 4. Store DAC values in memory (GD_FullPower_Band). 5. Initiate the intermediate value calculation, which calculates and store the values in memory (GD_IntermediatePower_Up/Down_1..7_Band). 6. The difference between the transmitter power at two adjacent power control levels, measured at the same frequency, shall not be less than 0.5 dB and not more than 3.5 dB.
- 205 - 7. CALIBRATION
Parameter Target Full Power (dBm) Tolerances (dB) PL 5 33.0 +0.5 – 1.0 Vol PL 6 31.0 ±0.3 Vol PL 7 29.0 ±0.5 Vol PL 8 27.0 ±0.5 Vol PL 9 25.0 ±0.5 Vol PL 10 23.0 ±0.5 Vol PL 11 21.0 ±0.5 Vol PL 12 19.0 ±0.5 Vol PL 13 17.0 ±0.5 Vol PL 14 15.0 ±0.5 Vol PL 15 13.0 ±0.5 Vol PL 16 11.0 ±0.5 Vol PL 17 9.0 ±0.5 Vol PL 18 7.0 ±0.5 Vol PL 19 5.0 ±0.5 Vol
Table 10-3. Target Power Levels for EGSM
G. RSSI and AGC Calibration
- Purpose This procedure satisfies the two following requirements: Calibrate an absolute power level on the antenna to a corresponding RSSI value. This value together with a pre-defined slope figure is then used to calculate the RSSI value of an arbitrary received antenna power. The formula y=kx+m is used. (Where k is the slope value, x the RSSI value, y the actual level, and m is an offset value.) Calculate the attenuation when the Low Noise Amplifier is switched off in the receiver branch. The attenuation value is stored in the flash memory and used when very high input signals are fed into the ME. - Procedure Proposal 1. Select switched receiver on a mid EGSM Channel. 2. Feed a modulated -68.5 dBm signal, on the same mid EGSM-Channel to the antenna input. Measure the RSSI value, calculate the RSSI table and store the value in GDFS as parameter: GD_RXLEVS_DBM_BURST_M_BAND. 3. On the same channel, now feed a modulated -50 dBm signal and measure the RSSI value. 4. Switch off the LNA, using the command FREC=3,0,1, and measure the RSSI value.
- 206 - 7. CALIBRATION
5. Calculate the difference between on and off (converting the result to ‚real dB attenuation) and store the result in GD_MPH_RX_AGC_Parameters_Band.
7.3.4 DCS 1800 Calibration Items
A. RXVCO Varactor Operating Point Calibration
- Purpose To adjust the varactor diode to a pre-determined operating point, so that the loop voltage of the RXVCO (measured with an ADC in AB 2000) is within the valid range. This is necessary to secure that all RX channels can be reached. - Procedure Proposal 1. Put the ME in static RX mode. 2. Measure the loop voltage with the AB 2000 ADC for all CVCO settings, that is, 0 ~ 7. Find a CVCO value that fulfills the requirements on loop voltage for low and high channel. 3. If there are several CVCO values that fulfill the loop voltage requirements, then the optimum CVCO value is the one that centers the loop voltage within the specified limits. 4. Store the selected CVCO in the memory. (GD_BAND_RX_VCO_Centre_Frequency_Adjustment) 5 Reset the radio.
B. TXVCO Varactor Operating Point Calibration
- Purpose To adjust the varactor diode to a pre-determined operating point, so that the loop voltage of the TXVCO (measured with an ADC in AB 2000) is within the valid range. This is necessary to secure that all TX channels can be reached. - Procedure Proposal 1. Put the phone in static TX mode. 2. Measure the loop voltage with the AB 2000 ADC for all CVCO settings, that is, 0 ~ 7. Find a CVCO value that fulfills the requirements on loop voltage for low and high channel. 3. If there are several CVCO values that fulfill the loop voltage requirements, then the optimum CVCO value is the one that centers the loop voltage within the specified limits. 4. Store the selected CVCO in the memory. (GD_BAND_TX_VCO_Centre_Frequency_Adjustment) 5. Reset the radio.
C. TX Loop Bandwidth Calibration
- Purpose The loop bandwidth is calibrated to match the pre-filtering of the modulation in DB 2000 by adjusting the phase detector current. Note: This also indirectly adjusts the VCO gain that can otherwise not be calibrated. This will ensure a correct transfer function for the modulation and keep phase error to a minimum.
- 207 - 7. CALIBRATION
- Procedure Proposal 1. Put the ME in switched TX mode on mid channel in frequency interval 11 for DCS (with random modulation). 2. Measure the RMS phase error at the RF connector. 3. Tune the phase detector current (IPHD) until the phase error is minimized. If two IPHD settings gave the same RMS, choose the lowest value. Measure 10 bursts for each value. 4. Calculate and store the IPHD values in GDFS (GD_IPHD_8Temperature_and_24Channel_Compensation_Band) 5. The offsets in the table are steps in the IPHD Table 10.4 and all offsets refer to the calibrated value (Trim) at mid channel in room temperature.
Frequency Interval 0123456789101112 13 14 15 16 17 18 19 20 21 22 23 0-6-6-5-4-4-3-3-2-2-1-10 0 1 1 2 2 3 3 4 4 5 5 5 1-6-6-5-4-4-3-3-2-2-1-10 0 1 1 2 2 3 3 4 4 5 5 5 2-6-6-5-4-4-3-3-2-2-1-10 0 1 1 2 2 3 3 4 4 5 5 5 3-6-6-5-4-4-3-3-2-2-1-10 0 1 1 2 2 3 3 4 4 5 5 5 4-6-6-5-4-4-3-3-2-2-1-10 0 1 1 2 2 3 3 4 4 5 5 5 5-6-6-5-4-4-3-3-2-2-1-10 0 1 1 2 2 3 3 4 4 5 5 5 6-6-6-5-4-4-3-3-2-2-1-10 0 1 1 2 2 3 3 4 4 5 5 5 7-6-6-5-4-4-3-3-2-2-1-10 0 1 1 2 2 3 3 4 4 5 5 5
Table 10-4. IPHD Compensation for DCS Band
D. TX Power Calibration
- Purpose To tune the different DCS power levels of the power amplifier to output powers corresponding to values in GSM 05.05 and calculate the intermediate levels that ensure a good power versus time performance. - Procedure Proposal 1. Reset the DIRMOD-block, and select a ‚mid channel using the trimmed value on the capacity array for VCO tuning and a default IPHD value as phase detector current. Turn on dummy burst modulation. 2. Use the Multi-burst method to characterize the relation between output power and the DACvalue. Then store the DAC values that give the closest approximations to the power targets defined in Table 10-5.
- 208 - 7. CALIBRATION
3. To avoid yield problems with the power template and switching transients spectrum a margin to the compression point of the PA should be observed. However, the output power must be kept within the tolerances specified in Table 10-5. 4. Store DAC values in memory (GD_FullPower_Band). 5. Initiate the intermediate value calculation, which calculates and store the values in memory (GD_IntermediatePower_Up/Down_1..7_Band). 6. The difference between the transmitter power at two adjacent power control levels, measured at the same frequency, shall not be less than 0.5 dB and not more than 3.5 dB.
Parameter Target Full Power (dBm) Tolerances (dB) PL 0 30.0 +0.5 – 1 Vol PL 1 28.0 ±0.3 Vol PL 2 26.0 ±0.5 Vol PL 3 24.0 ±0.5 Vol PL 4 22.0 ±0.5 Vol PL 5 20.0 ±0.5 Vol PL 6 18.0 ±0.5 Vol PL 7 16.0 ±0.5 Vol PL 8 14.0 ±0.5 Vol PL 9 12.0 ±0.5 Vol PL 10 10.0 ±0.5 Vol PL 11 8.0 ±0.5 Vol PL 12 6.0 ±0.5 Vol
PL 13 4.0 ±0.5 Vol PL 14 2.0 ±0.5 Vol PL 15 0.0 ±1 Vol
Table 10-5.Target Power Levels for DCS
- 209 - 7. CALIBRATION
E. RSSI Calibration
- Purpose This procedure calibrates an absolute power level on the antenna against a corresponding RSSI value. This value together with a pre-defined slope figure is then used to calculate the RSSI value of an arbitrary received antenna power. The formula y=kx+m is used. (Where k is the slope value, x the RSSI value, y the actual level, and m is an offset value). - Procedure Proposal 1. Select switched receiver on a mid DCS-Channel. 2. Feed a modulated -68.5 dBm signal, on the same mid DCS Channel to the antenna input. Measure the RSSI value, calculate the RSSI table, and store it to the memory (GD_BAND_RXLEVS_DBM_BURST_M[2])-1 byte.
7.3.5 WCDMA Calibration Items
A. RF VCO Center Frequency Calibration
- Purpose This procedure is designed to calibrate the RFVCO (Radio Frequency Voltage Controlled Oscillator) center frequency of the Ericsson RF 2110 (hereafter referred to as the RF 2100) and ensure that all channels can be reached with sufficient margin. The objective of the calibration is to determine a CVCO (Center VCO) value that guarantees the functionality of the RFLO (Radio Frequency Local Oscillator). - Procedure Proposal 1. Start the VCXO and RFVCO. VCXOCONT is set to its calibrated value, Ericsson AB 2000 DAC3. 2. Measure the loop voltage (WRFLOOP), with the AB 2000 ADC (GPA4), for all CVCO settings, that is, 0-7. Find a CVCO value that fulfills the requirements on loop voltage for low and high channel. If there are several CVCO values that fulfill the loop voltage requirements, then the optimum CVCO value is that that centers the loop voltage within the specified limits. 3. Store the calibrated CVCO value in GD_RF_SYNT_CONFIG_ID.
B. TX Carrier Suppression Calibration
- Purpose DC offset compensation the carrier, to the wanted signal at the IQ-modulator output. The leakage is caused by imperfections in the baseband IQ-path and inside the IQ-modulator. It impairs the modulation accuracy and results in a high vector magnitude (EVM). The outcome of the calibration is values for RECDCI and RECDCQ that minimize the carrier. - Procedure Proposal 1. Set the ME in TX mode on mid-channel. Use typical TX settings. Generate 960 kHz squarewave on both I and Q with amplitude = 8 (sine-wave could be used instead). Start with the best value from earlier calibrated units on RECDCI on RECDCQ.
- 210 - 7. CALIBRATION
2. Measure the relative power between the 1950 MHz carrier and 1949.04 MHz at the antenna output. Jump to step 6 if the requirement is met. 3. Step RECDCI from 0 to 3. Set TXON = 0 and wait 1 ms before changing RECDCI from 3 to 5. Set TXON = 1, wait 1 ms and continue with stepping from 5 to 7. 4. Set RECDCI to the value that minimizes the 1950 MHz carrier. If this involves a change of sign the TXON switching and delay sequence in point 3 must be executed. Jump to 6 if the requirement is met. 5. Find and set RECDCQ to the value that minimizes the 1950 MHz carrier. This can be made by stepping RECDCQ from 0 to 7 with the TXON switching and delay sequence in step 3. 6. If the requirements are not met, repeat steps 3, 4 and, if necessary, 5 once with the new RECDCI and RECDCQ (found in 4 and 5) as initial values. Otherwise proceed with step 6. 7. Save the final dBc value (for statistics), RECDCI and RECDCQ. Store the calibrated parameters in GD_RF_TX_CONFIG_ID.
C. TX LPF Bandwidth Calibration
- Purpose The low pass filters within the Ericsson DB 2100 (hereafter referred to as DB 2100) are designed to prevent spurious emissions output from the TX IQ-D/A (Digital-Analog) converters ®´ without adversely affecting the signal or causing a deterioration of the modulation accuracy. The objective of this calibration is to determine the values for LPQ and LPBW that offer the best trade off against the system-related requirements. These settings determine the cut-off frequency and should always have the same value. - Procedure Proposal 1. Use typical TX settings. Generate a 960 kHz square-wave at baseband without phase shift between I and Q. The amplitude should be about 50% of full scale. 2. Measure the relative power between 1952.88 MHz (fc + 3*960 kHz) and 1949.04 MHz (fc ®´ 960 kHz) in dB at the antenna output. Find the setting of LPQ = LPBW between 3 and 15 that obtains the dBc value closest to the typical value. Start with the best value from earlier calibrated units. Spectrum analyzer settings (example): RBW = 300 kHz, Span = 8 MHz. 3. Set LPQ=LPBW to the found value in 2. Also save the dBc and the decided LPQ = LPBW value for statistics. Store the calibrated parameters in GD_RF_TX_CONFIG_ID.
D. TX Maximum Output Power Calibration
- Purpose These procedures verify that the ME can meet the requirements on maximum output power. The calibration aims to establish WPABias, VGA and QVGA settings that fulfill ACLR requirements for maximum output power, both in high, medium, and low gain mode. These calibrations are designed to conform to the ME maximum output power and ACLR requirements specified in 3GPP Spec TS34.121. - Procedure Proposal 1. Use typical TX settings, mid channel. 2. Set gain to the best value based upon previous calibrated units.
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3. Measure output power as broadband power. 4. If the ACLR requirements, described in Table 11 are not met, calculate the test step necessary to achieve the correct power. Use correlation from earlier calibrated units to calculate the new gain setting (default correlation between VGA and output power is 1 dB and for QVGA 0.25dB). 5. Measure ACLR at this power level. 6. If the ACLR requirement is not met, reduce VGA and QVGA. 7. Measure and store the temperature at this point. This provides the value for TPmax. 8. This power and gain setting is to be used in calibration of TX power table. 9. Set gain to maximum power in medium gain mode and measure ACLR at this power level. RFBias should be set to 1 and WPABias should be set to the same value as for maximum output power. 10. If the requirements are not met, step the gain down and measure ACLR until the requirements are met. The correlation between ACLR and output power is that 1 dB in power equals typical 3 dB in ACLR. Use correlation from earlier calibrated units to calculate the new gain setting. 11. This power, Pmax meas MG, is input to the calibration of TX power table. 12. Set gain to maximum power in low gain mode and measure ACLR at this power level. RFBias should be set to 1 and WPABias should be set to the same value as for maximum output power. 13. If the requirements are not met, step the gain down and measure ACLR until the requirements are met. Use known correlation from earlier calibrated units to calculate the new gain setting. 14. This power, Pmax meas LG, and gain setting provides input to the calibration of TX power table.
E. TX Power Table Calibration
- Purpose The calibration data contained within the TX Power Table controls the gain for all types of power change; including, the inner-loop power control and maximum output power of the platform. The purpose of this calibration is to complete the TX Power gain table with values for VGA, QVGA, RFBIAS, WPABias, and WDCDCREF that meet the specified requirements for innerloop power-control and Maximum output power. The size of hysteresis area must also be found. These calibrations are designed to conform to the ME maximum output power, inner loop power control, change of TFC and (PRACH preamble tolerances) requirements specified in 3GPP Spec TS34.121. - Procedure Proposal This calibration consists of two parts: first measurements and then an off-line calculation. The measurement results are used for characterizing the hardware so that proper settings can be calculated for all tables. Settings and limitations are also used from maximum output calibration. 1. Perform measurements (1) VGA behavior in LG (Low Gain) mode. PABias should not be offset and RFBIAS should be 1. (2) VGA behavior in MG (Medium Gain mode). PABias should not be offset and RFBIAS should be 1. (3) QVGA behavior in LG mode (4) IQ-Gain behavior in LG mode. (5) WPABias gain step size. Every eighth setting is measured twice. For better accuracy take the average of each step pair. Interpolate the gain steps in between the averaged measured values. (6) WDCDCREF gain step size. Every fifth setting is measured twice. For better accuracy take the average of each step pair. Interpolate the gain steps in between the averaged measured values.
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(7) Size of step between LG/MG and MG/HG and between each setting of RFBIAS (1-7). The main purpose is to find the relative difference at different frequencies. Distribute with equal frequency offset except if there are known ‚worst-case frequencies. Measured at 5 channels, maximum and minimum steps reported. Average value of minimum and maximum should be used in following calculations. (8) Measure properties: Measure the following properties using a modulated signal: WPA-gain expansion versus output power on mid channel. Compensation needed for maximum output power over the band (13 channels). 2. Perform offline calculations (1) Calculate the compensation values for Table 10-6. Store these values in GD_RF_TXGAIN_TB_SEL_ID. (2) Extract the range of needed compensation tables (minimum and maximum). (3) Calculate the expected compensation for each table in dB (use ‚table 0 for the table that is ‚0 dB or closest to ‚0 dB) and spread out the rest to achieve equidistant compensations. (4) Calculate and store the 24 sets of tables, GD_RF_TX_GAIN_TB0_ID to GD_RF_TX_GAIN_TB23_ID. Each set of tables shall include: One High-gain table: 44 bytes. One Low-gain table: 44 bytes. One RFBias table: 22 bytes. One WDCDCRef table: 44 bytes. One WPABias table: 44 bytes. One value for IQ-Gain: 1 bit (will occupy 1 byte). One value for TABLE_OVERLAP: 1 byte. One value for UPPER_LIMIT: 1 byte. (5) Calculate the actual compensation (for maximum output power) that each of these 24 tables will give. Store this in GD_RF_TX_FREC_INT_ID. 3. Store data in GDFS
UARFCN Temp. 9612 9637 9662 9687 9712 9737 9763 9788 9813 9838 9863 9888 -15 0 15 30 45 60 75 90
Table 10-6.The Complete Gain Compensation Table
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E. TX Open Loop Power Control Calibration
- Purpose The purpose of the calibration of open loop power control is to store parameters for the Open Loop Power Control algorithm. This is a pure off-line calculation. Use data (positions and output power, in dBm) from table 0. Curve fitting should be done preferably with minimum square method. System related requirements: Open loop power control Maximum allowed UL TX Power UE Transmitted power - Procedure proposal 1. Create a curve fitting for the low-gain region, use positions with a power greater than -50 dBm: Position = B3 * Pout + A3 2. Extract A3 and B3. 3. The power level (output power) at the highest position in the low-gain region sets the parameter P2. 4. Divide the high-gain region into two regions at the split between mid-gain and high-gain. The output power at this position sets the parameter P1. 5. Do a curve fitting for the mid-gain region (where RFBias > 0) of the highgain region, use power- levels from P2: Position = B2 * Pout + A2 6. Extract A2 and B2 7. Do a curve fitting for the high-gain region (where RFBias = 0) of the highgain region: Position = B1 * Pout + A1 8. Extract A1 and B1 9. Save A1, A2, A3, B1, B2, B3, P1 and P2 in GD_RF_TX_GAIN_PARAM_ID.
Figure 7-2. Example of Position versus Power and Calculated Equations
- 214 - 7. CALIBRATION
F. RX LPF Bandwidth Calibration
- Purpose This procedure calibrates the LPF bandwidth. The bandwidth of the channel filters will affect system parameters as reception sensitivity and adjacent channel selectivity. The procedure also verifies that the IF-filter is properly matched.
Figure 7-3. AGC Block Diagram (Parameter Ak, Output1, and Pref)
- Procedure Proposal 1. Feed a CW carrier at 2140 MHz with a power of -60dBm into the antenna connector. 2. Set UE in RX-mode on 10695ch. 3. Set the AGC_UL and AGC_LL to minimum. GLNA is forced to high gain mode. 4. Set RF 2110 LPQ and LPBW to 8, that is, LPQ=LPBW=8. 5. Get Ak (output2) from N slots. Calculate Average_Ak (Ak_IB) according to the equation below. N should be as large as possible, with respect to time consumption.
6. Set UE on 10705ch and get Ak (output2). Calculate Average_Ak (Ak_LB) according to the Equation 1. 7. Calculate IF-filter symmetry using the following equation. IF_SYM = Ak_IB - Ak_LB 8. Set UE on 10685ch and get Ak (output2). Calculate Ak (Ak_OB) according to the Equation 1. 9. Calculate selectivity level using following equation. Ak_SE = Ak_OB - Ak_IB 10. If the requirement is not met, decrease LPBW and LPQ one step and repeat from 8. 11. Store the resulting LPBW and LPQ in GD_RF_RX_CONFIG_ID.
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F. RX LNA Gain Switch and AGC Hysteresis Calibration
- Purpose This procedure calibrates the gain correction parameter of Ak in the AGC algorithm between GLNA=0 and GLNA=1; that is, it establishes the gain difference in the LNA between high gain mode and low gain mode. It also calibrates AGC_UL and AGC_LL, the upper and lower Ak values where the AGC should switch between high and low LNA gain (AGC hysteresis).
Ak (DEC)
72 + AGC_CR AGC_ GMAX
GVGA (DEC)
Ak=GVGA+(GLNA*AGC_CR)
72 AGC_UL AGC_CR
AGC_LL
GLNA=1 GLNA=0
6 AGC_ GMIN 0 0 RF Input Lev el (dBm/3.84 MHz) RF Input Level (dB m/3.84 MHz)
Figure 10-4. LNA Gain Switch and AGC Hysteresis Parameters
1. Set the UE in RX-mode on 10695ch. 2. Feed a CW carrier at 2140 MHz with a power level of -65dBm. 3. Set the AGC_UL and AGC_LL to maximum. GLNA is forced to low gain mode. 4. Get average Ak from Equation 1 and save it. (Ak_LG) 5. Set the AGC_UL and AGC_LL to minimum. GLNA is forced to high gain mode. 6. Get average Ak. (Ak_HG) 7. (Ak_LG) - (Ak_HG) = (Correction). 8. Round off (Correction) to integer (AGC_CR) and store it in GDFS (GD_RF_RX_CONFIG_ID). AGC_CR is an AGC algorithm parameter and is set to DB 2100 RFIF. 9. Calculate AGC_LL=8+AGC_CR and AGC_UL=18+AGC_CR and store them in GDFS (GD_RF_RX_CONFIG_ID). AGC_LL and AGC_UL are AGC algorithm parameters and are set to DB 2100 RFIF.
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G. RX AGC Gain Max and RX RSSI Calibration
- Purpose To prevent wind up in AGC algorithm, this procedure calibrates the absolute power levels at the antenna connector against RSSI values and the maximum gain setting for AGC. Reference [6] specifies that the reporting range of the RSSI should be between -100 dBm to -25 dBm. The specified accuracy requirement is applied to the received power from -94 through -50 dBm. This is the last RX calibration. LPBW, LPQ, AGC_CR, AGC_LL and AGC_UL must be calibrated according to above calibrations respectively and applied to this calibration. Initially, the AGC anti-wind up is turned on using AGC_GMAX=127. Use the calibrated value after step 2, otherwise the AGC wind up may occur at the beginning of the RSSI calibration. - Procedure Proposal 1. Set the ME in RX-mode on channel 10695. 2. Feed a CW carrier at 2140 MHz with a power level of -105 dBm. Get average_Ak (output2), add 6 to the value and store it in GDFS as AGC_GMAX (GD_RF_RX_CONFIG_ID), rounded off to an integer. Set the AGC parameter AGC_GMAX to the calibrated value. 3. Clear Ak ‚table 0. 4. Change the CW carrier power level to -95 dBm. 5. Read Ak value (output2) and calculate Average_Ak (Equation 1). Store Pin_Corrected (Equation 2) at Ak=round(Average_Ak). N in Equation 1 should be as large as possible. Pin_Corrected = Pin-round(Average_Ak)+Average_Ak Equation 2 6. Then increase the output level of the signal generator to -80, -60, -40 and -25 dBm and store the corrected RF input level and Ak to the memory respectively. 7. Use the average Ak values and Pin_Corrected from the two lowest power levels (-95 and - 80 dBm) to extrapolate Ak and Pin_Corrected for -110 dBm according to: Average_Ak_110 = 2*Average_Ak_95 - Average_Ak_80 Pin_Corrected_110 = Pin_Corrected_95 - Pin_Corrected_80 8. Store Average_Ak_110 and Pin_Corrected_110 according to step 4. 9. Perform the interpolation. AK_BANK_SEL in DB 2100 shall be set to 0. 10. Measure the ME temperature (T) and save for offline calculations. 11. Store the result to GDFS. (GD_RF_RX_AK_TB0_ID). When stored in GDFS, the first position in the table (Ak=0) should be replaced with the table number (0-23) in bcd format and the second position (Ak=1) set to 0xffff to flag that the table is calibrated. Position 2 to 5 should be set to zero. 12. Perform the offline calculations and check the requirements.
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7.3.6 Baseband Calibration Item
A. Battery Voltage Calibration
- Purpose Calibrates the voltage table for the power management functionality. Some voltage measurements in the remaining test will be done with calculated voltage levels from this test. - Procedure Proposal 1. Send the command LVBA=0 to reset local values in Test Program. 2. Set voltage on VBATT to 3.20 V. 3. Send the command LVBA=5,0x140 to read the low voltage level from ADC. 4. Set voltage on VBATT to 4.10 V. 5. Send the command LVBA=5,0x19A to read the high voltage level from ADC. 6. Send the command LVBA=1 to store local values into global data. 7. Send the command LVBA=3 to view and record values stored in global data.
Voltage Level on VBATT (V) Min. Typ. Max. Unit 3.2 19 2E 3C HEX 25 42 60 DEC 4.1 64 7E 96 HEX 100 125 150 DEC
Table 10-7. Battery Voltage Calibration Limits
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7.4 Program Operation
7.4.1 XCALMON Program Overview
When you try to calibrate the U8550 mobile phone, you should make a configuration of calibration environment like Figure7-1. And if you finish making configuration, please execute the XCALMON program. Running the XCALMON program, you should show XCALMON program window like Figure7-5. If XCALMON program would be executed, it checks the connection of instruments and initializes them automatically. The result of checking and initializing instruments was shown like Figure7-6. XCALMON supports three functions. - Calibration of EGSM 900, DCS 1800, and WCDMA band - Instrument (Agilent8960, Tektronix PS2521G) control - UART communication with U8550 mobile phone XCALMON has three windows and each window support different function. - ITP(Integrated Test Program) starting window using production loader - Calibration tree window - Command window which supports interactive ITP commands like Hyper terminal
Figure 7-5. XCALMON Window
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7.4.2 XCALMON Icon Description
A. DOS Window Icon
When you click the DOS window icon, then you should see the ITP command window like DOS window of DOS-operating system. In ITP command window, you should communicate with U8550 mobile phone which is running in ITP mode. For example, if you will enter command “VERS” and enter the return key, you should get the response of the present running ITP version information from U8550 mobile phone.
Figure 7-6. XCALMON ITP Command Window
B. Calibration Tree Window Icon
When you click the calibration window icon “C”, then you should see the calibration tree window. That will be shown all calibration items. If you want to calibrate U8550 mobile phone for all calibration items, you should select “Calibration” and push “F4” button in your keyboard. Also there are four tap view in calibration window. - OUTPUT : All results of calibration - STATUS : Summary of calibration result - INSTRUMENT : Control and view instrument connection status - UART : Control and view UART connection status
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Figure 7-7. XCALMON Calibration Tree Window (OUTPUT Tab)
Figure 7-8. XCALMON Calibration Tree Window (INSTRUMENT Tab)
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Figure 7-9. XCALMON Calibration Tree Window (UART Tab)
C. ITP Starting Window Using Production Loader
When you click the ITP starting window icon”L”, then you should see the ITP starting window. That dialog window just wait for power-on of U8550 mobile phone. When it will occur power-on, it automatically start ITP running. If you want to change the start address of ITP, you could change that address directly. To change ITP start address is possible when we download “Production loader” previously.
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Figure 7-10. XCALMON ITP Starting Window (Using Production Loader)
7.4.3 Calibration Procedure
Calibration procedure of XCALMON was the same as below procedure. - Configuration of calibration - Running ITP using production loader - Calibration start using XCALMON - Verification of calibration result
A. Configuration of Calibration
Configure to calibrated U8550 mobile phone like Figure7-1. If configuration will be accomplished, start XCALMON program.
B. Running ITP Using Production Loader
If XCALMON will be executed, you should run ITP using “L” ITP starting icon at first. Click the “L” icon, then you will see the ITP start window like Figure7-10. When you will turn on the U8550 mobile phone, the production loader will be downloaded automatically like Figure7-11 and then it will execute the ITP at once. If the ITP will operate normally, you should see the characters “TP, OK” in ITP command window like Figure7-12.
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Figure 7-11. Production Loader Downloading
Figure 7-12. ITP Start Complete Window
- 224 - 7. CALIBRATION
C. Calibration Start Using XCALMON
If you want to calibrate U8550 mobile phone, click the calibration icon “C”. And then you will see the calibration tree window like Figure7-6. To start calibration, you should select “Calibration” item and push “F4” button in your keyboard.
D. Verification of calibration result
If the calibration will be ended, you will see several message window and the result of calibration through OUTPUT & STATUS tab view. The detail explanation of those will be described in chapter 7.4.4
7.4.4 Calibration Result Message
If the calibration is over without error, “PASS” message window will show up like Figure7-13. On the contrary, if the calibration is over with some error, “FAIL” message window will show up like Figure7-14. Additionally, in all of the cases, it is possible to check the calibration result with OUTPUT & STATUS tab view.
Figure 7-13. Calibration PASS Message Window
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Figure 7-14. Calibration FAIL Message Window
Figure 7-15. Calibration Result from OUTPUT Tab View
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Figure 7-16. Calibration Result from STATUS Tab View
- 227 - - 228 - 8. CIRCUIT DIAGRAM
1 2 3 4 5 6 7 8 9 10 11 12
A A C111 22p
L199 100nH
FL102 DFYY61G95LBNBC-TT1
WCDMA_TX TX ANT RX WCDMA_RX G3 G4 G5 G6 G1 G2
B B W101 KMS-507 C103 L101 G2 R101 0 RF ANT ANTPAD101 G1 33p 1.8nH
L102 FL101 C101 8.2nH LMSP43MA-288 7 1.2p 1
ANT GSM900_RX 2 GSM1800_RX 10 3 VDD GSM1900_RX
9 4 VC1 WCDMA 8 VC2 5 VCG 12 GSM18001900_TX 13 C L105 GSM900_TX GSM_RX C
ANTSW0 GND5 GND4 GND3 GND2 GND1
6 DCS_RX 16 15 14 11 L104 PCS_RX ANTSW1
DCS_TX L103 ANTSW2 GSM_TX
R102 ANTSW3 0
D D
C110 C107 C106 C109C105 C108 C102 C104 0.01u 10p 10p 0.01u 10p 0.01u 0.01u 10p
E R2250 E VDD_A VDD_A 0 R2251 VDD_B VDD_B 0
C116 C117 C115 10u 10u 10u 2012 2012 2012
F F
R106 V_wivi_A 0 VBATI R103 EXTLDO 0 R104 N101 LP3981ILD-2.8 1 6 V_wivi_B VOUT VEN 0
R105 2 5 G VIN BYPASS G 0 3 4 VOUT_SE GND1 C113 C114 C112 GND2
0.1u 10u 7 0.033u 2012
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229 8. CIRCUIT DIAGRAM
1 2 3 4 5 6 7 8 9 10 11 12
A A
Z201 TMXU753
6 1 IN- IN+ 5 2 SHIELD GND 4 3 OUT+ OUT-
C218 C222 2200p C220 2200p 1.2p
B L207 B 100nH
1608
C227 VDD_B RXQA 0.01u C229 RXQB 0.01u C228 C201 C203 RXIA 27p 27p 0.01u C226 RXIB 0.01u R210 R204 R203 R201 C205 MCLK 75 75 0 0 NA L208 L202 1uH C221 82nH 82p C C C219 0.01u C202 C223 0.01u 0.01u L201 R202 82nH 3.3K R215 VDD_B C215 C214 C208 C204 C207 10 22p 22p 0.1u 22p 2200p C225 22p C206 22p C231 C230 R216 R212 A7 A8 A9 A10 C7 A4 A5 A1 A3 A6 C4 C5 C6 A2 VCXOCONT 47p 330p 10K 1K IRA IRB CDI QRA QRB CDQ C234 C232 C224 IFINA IFINB
MCLK R214 IFOUT VCCIF VCCLF NA GNDLF V201
2.7p 4.7p 0.01u R213 B1 GNDMIX B10 IFOUTB VCCREF B201 NA C1 C10 BBY58-02W VCCMIX XOIA TSX-8A D1 D10 4 MIXINA XOIB 3 HOT2 GND2 C233 E1 E10 2 GND1 HOT1 1 NA D MIXINB VCCBUS R211 D F1 F10 GNDBIAS IFLOA 13MHz 56p G1 G10 L204 C211 GNDEME IFLOB R217 H1 N201 H10 RFIN GNDRFLO 10K WCDMA_RX J1 LZT-108-5323 J10 2.2nH 22p GNDBYP RFLOOA K1 C8 VCCRF XOOA C3 D8 GNDIF XOOB L205 D3 E8 DATA GNDREF NA E3 F8 L203 CLK GNDBUS F3 G8 IFLO STROBE REFON G3 H8 5.6nH GLNA GNDVCO IFLOBAR C240 22p C209 C210 RFLO 3.3p 3.3p R218 VTUNE VCCVCO VCCRFLO RXON GNDTUNE INDBYP RFOUT VCCPLL VCCPHD PHDOUT RFLOOB XOOON GNDPLL GNDPHD NA C239 22p K3 K7 K8 K9 H4 H7 K2 K4 K5 K6 H3 H5 H6 K10 RFLOBAR XOOA XOOB E E C212 22p R221 VDD_B C237 C235 10 0.01u 22p L206 NA R205 R220 0 R206 C238 C236 10 5.6K 0.01u 22p C216 C213 NA TP202 TP203 TP201 390p
WDAT R209 F WRFLOOP F WCLK 0
C217 WSTR 5600p
R207 GPRFCTRL 0
R208 CLKREQ 100 FROM MARITA SIDE FOR POWER SAVING
G G
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MFG ENGR CHK: Page 2 of 7(RF Part 2 of 4) Changed by: Date Changed: Time Changed: QA CHK: REV: Drawing Number: Page: SG Kang 2004, May 16 12:50:11 pm 2 1 2 3 4 5 6 7 8 9 10 11 12
230 8. CIRCUIT DIAGRAM
1 2 3 4 5 6 7 8 9 10 11 12
A A
WCDMA_TX GND4 GND3 GND5 IN OUT N303 GND1 GND2 ESI-3EAR1.950G01-T
B B
VBATI
VCCWPA
N302 N301 WDCDCREF MAX1820ZEBC RF9266 A1 B1 10 11 9 _SKIP SYNC A2 C1 C COMP _SHDN VCCWPA C GND4 GND3 R308 A3 C2 GND5 VDETECT OUT BATT 3838 12 8 L304 0 VBATI A4 C3 R303 GND6 VCC_DET R301 REF LX 13 7 4.7uH WPOWERSENSE C312 33K 39K B4 C4 GND7 GND2 22p GND PGND C303 C304 L301 14 6 10u R302 R307 C302 2012 10u 2012 C305 C306 VCC21 VCC_BIAS2 22p 10u 2012 L303 100K 1000p 15 5 0 C301 C308 VCC22 VCC_BIAS1 330p L302 16 4 0.01u GND8 GND1 17 3 VCC11 VCTRL2 18 2 R306 VCC12 VCTRL1 19 1 WPAREF 0 C311 C310 IFLOBAR GND9 RFIN RFOUT 10p 0.1u GND10 GND11 C309 D 22p RFLO IFLO D 22 23 20 21 C318 C333 100p 100p
L306 0
RFLOBAR NA R316
V_wivi_A C319
4.7p L305 BLM15BB750SN1J R310 R311 R309 75 0 0 V_wivi_B 10 C317 C313 22p 0.01u C314 C322 C315 C323 C325 C324 0.01u 0.01u 10p 10p 0.01u 10p R319 V_wivi_A 0 L307 L309 C331 C332 TP301 TP302 E 5.6nH 5.6nH E 22p 0.01u C326 10p XOOA XOOB TP303 B301 TP304 C320 TP305 E3 D3 C3 F3 F1 V_wivi_AV+ VO RTEMP G3 J1 I1 H1 G1 E1 D1 C1 B1 TP306
4 3 5 3 1 33p C307 G3 G2 G1 GND1 I2 IFLO RFLO DATA 2 33p 6 L308 J2 XOOC XOOB A1 VCCRF GND2 NC O I1 OUT GNDBB QINBAR TXQB VCCBUS GNDBUS VCCIFLO IFLOBAR 5 1 2 4 10nH J3 GNDIFLO A2 SAFEH1G95FL0F00R05FL301 OUTBAR RFLOBAR QIN TXQA LM20BIM7X-NOPB J4 GNDRFLO1 A3 C321 GNDRF INBAR J5 A4 TXIB R304 R305 MIXOUT IN J6 A5 TXIA NA NA 33p MIXOUTBAR VCCBB J7 A6 VCCIF VCCIFPHD C330 J8 N304 A7 IFBP PHDIFOUT 22p J9 LZT-108-5322 A8 IFBPBAR VCCIFPLL J10 A9 R320 VTUNERF GNDIFVCO1 F H3 A10 10 F C316 GNDRFLO2 VCCIFVCO R315 H4 C4 V_wivi_B 22p GNDRF1 CLK H5 C5 680 GNDRF2 GNDIFPHD H6 C6 L311 GNDRF3 GNDIFPLL C335 C337 H7 C7 WDAT GNDIF WON 22p 0.01u 15nH WCLK GNDIFVCO2 VCCRFVCO VTUNEIF PHDRFOUT GNDRFPLL GNDRFPHD GNDTUNERF GNDRFVCO2 GNDRFVCO1 GNDTUIF VCCRFPLL VCCRFPHD STROBE TXON R317 WSTR F8 E8 D8 H8 C8 G8 I10 F10 E10 D10 H10 B10 C327 C10 V_wivi_A G10 0 4p
C328 L310 47p 15nH R314 R313 R318
680 0 4.7K R312 C329 C334 C336 V_wivi_B NA 150p 3300p G 0 G
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MFG ENGR CHK: Page 3 of 7(RF Part 3 of 4) Changed by: Date Changed: Time Changed: QA CHK: REV: Drawing Number: Page: SG Kang 2004, May 16 5:04:02 pm 3 1 2 3 4 5 6 7 8 9 10 11 12
231 8 CIRCUIT DIAGRAM
1 2 3 4 5 6 7 8 9 10 11 12
VBATI
A A FL401 NFM21PC105B1A3 1 2 IN OUT 34 G1 G2 C422 C420 C424 C423 10u 10u 0.01u 22p 2012 2012
R408 PASENSE+ 0 R407 0.05 R413 PASENSE- BLM15AB601SN1J 0 L401 C408 PAREG 100p B B R402 C401 3K R401 C402 IOUT 1K 100p 150p
VDIG
R404
0 C414 TP404 TP402 TP403 0.01u N402 LZN-901-0536-R1A F1 AVDD D3 I2CDAT I2CDAT D1 D5 I2CCLK QDAT I2CCLK TP405 G8 A4 QDATA C SYSCLK2 SYSCLK2_MCLK IDAT IDATA C TP401 D2 C5 R409 RESOUT3n RESETON_RESETB DCLK DCLK VDD_A A8 0 IRA A7 C406 C405 C426 IRB A6 H4 33p 100p 22p QRA AUXO2 VDIG A5 G5 QRB BEARP B4 H5
6 RXSTR BEARN 2 RXON R406
12 G7 18 N404 PCMUL 0 LDB21897M15C E4 E6 AUXI1 GPDAT 4 F2 E5 C407 R418 B2 CCO GPCLK VCC2 VCC1 VDIG_HERTA
VAPC 1 F3 NA UB MICIP 0 3 G1 C3 C410 VSUPPLY B1 C430 MICIN DAC01 C419 C421 NC
10 3 GND1 GND2 L406 B8 B3 GSM_TX EGSM_OUT DCS_PCS_IN R419 GPA0 DAC02 0.01u NA 2 5 6 33nH B6 A3 33p C411 NA C429 2.2p FL402 GPA1 DAC03 0 15 4 SAFEC1G84FA0F003 2 C6 DCS_TX DCS_PCS_OUT EGSM_IN C431 C434 GPA2 L407 O1 G1 1 C7 2.2nH R403 33p IN GPA3 SKY77321 O2 G2 DCS_RX
1 4.7nH R420 C8 C2 C409 TX_ENABLE 6.8nH 33p 10p GPA4 DACCLK 13 N401 5 R417 4 5 D6 C1 NA RSVD BS C432 GPA5 DACDAT 0 L408 D8 D4 GPA6 DACSTR 6.8nH D7 D 2.2p GPA7 D E2 DEC1 H7 H2 PGND GND7 GND6 GND5 GND4
GND3 GND2 GND1 PCMDL DEC2 F6 H3 PCMCLK DEC3 C416
9 8 7 G6 B2 11 19 17 16 14 PCMSYN DEC4 C418 0.068u E7 E1 L404 C436 ADSTR DEC5 C413 0.068u C415 0.068u 75 N403 E3 2.7p FL403 REXT C417 0.068u LDB211G8020C SAFEC1G96FA0F003 2 BLM15BB750SN1J 4 R414 B2 O1 G1 C437 C438 0.068u 1 L409 1 A1 A2 L402 UB IN R405 VSS1 VDD1 O2 G2 PCS_RX
18 3 4.7nH R422 100K B1 B5 B1 6.8nH 1.5nH 10p VSS2 VDD2
NC 4 5
GND1 GND2 L405 C4 B7 75 R415 R416 C435 VSS3 VDD3 2 5 6 22nH E8 F5 C446 C403 270 270 VSS4 VDD4 C433 C427 F4 F8 NA 22p C404 2.7p VSS5 VDD5 C428 L410 F7 H6 22p VSS6 VDD6 22p 22p 12p 15nH G3 VDIG_HERTA VSS7 G4 G2 VSS8 NC1 R421 H8 H1 TXON VSS9 NC2 0 R412 Z401 RXON C454 SAFEC942MFL0F00 E E BSEL0 33p 3 2 L403 O1 G1 C412 L415 1 PCTL IN GSM_RX 18nH O2 G2 33p R410 4 5 MODA C425 C453 100 R411 22p MODB 33p 100 R424 D3 H1 F1 C3 K1 J1 G1 MODC G3 F3 E3 E1 D1 C1 B1 100 R423 L416 MODD VDD_A PCTL BSEL RFHB RFHA TXON 100 K2 RXON A1 TXOLA TXOLB L411 NC5 TXOHA TXOHB RFHD GNDRF2 GNDRF1 K3 VCCBUF A2 MODA RFHC C452 C451 VDD_A K4 A3 C440 C443 MODB GNDPLANE GNDRF 0.01u 22p K5 A4 22p 0.01u MODC RFLB K6 A5 MODD RFLA K7 A6 VCCPLLN405 VCCRF C441 K8 A7 R430 XOOB XOOB LZT-108-5325 QRB K9 A8 0 R431 1000p XOOC QRA K10 A9 0 R429 F NC6 IRB F L412 H3 A10 0 R428 GNDBUF IRA 5.6uH H4 C4 0 NC3 REON 1608 H5 C5 PS CLK C442 H6 C6 GNDPLL DATA XOOA H7 C7 1000p XOOLA STROBE NC4 VTUNE VCCVCO NC2 NC1 GNDVCO5 GNDVCO4 GNDVCO3 GNDVCO6 PHDOUT GNDVCO2 GNDSILENT GNDVAR GNDVCO1 F8 E8 H8 D8 C8 G8 J10 F10 E10 H10 D10 C10 B10 G10 GPRFCTRL PULSESKIP
TP406 RADCLK
L413 2012 TP408 RADDAT G 100uH G TP407 RADSTR
C444 R425 R426 R427 L414 VLOOP VDD_A 560 1800p 120 390 C439 C445 C447 C448 C450 C449 0.01u 1200p 560p 330p 22p 0.01u
H Engineer: H JS Joo LG ELECTRONICS INC. Drawn by: Mobile Handsets R&D Center JS Joo HW Group, Development Lab 6 R&D CHK: TITLE: Size: U8550-spfy0106301-1.1 A2 DOC CTRL CHK: GSM/DCS (INGELA) 12 1 8 A MFG ENGR CHK: Page 4 of 7(RF Part 4 of 4) Changed by: Date Changed: Time Changed: QA CHK: REV: Drawing Number: Page: JS Joo 2004, May 16 7:25:06 pm 4 1 2 3 45 6 7 8 9 10 11 12
232 8. CIRCUIT DIAGRAM
1 2 3 4 5 6 7 8 9 10 11 12
VEXT15_M VEXT15_W VBATI VCAM_2.8V VBATI VCAM_VGA_2.8V VBATI VCAM_1.8V VDIG VEXT15_M VDIG VDIG VBATI
VBT VTF R501 R502 R2237 NA R2238 C509 R2171 U503 U501 N501 R2192
R2240 100p A R526 0 1 5 R503 0 1 5 VUSB A VDD VOUT VDD VOUT U502 PWRRSTn ON_OFF BYPASS 100K 0 2 2 0 1 5 0 N502 0 N702 0 3 4 GND GND VDD VOUT U510 R2186 R527 0 3 4 R505 0 3 4 2 1 5 1 5 1 5 75 CAM28_EN CE NC CAM28_VGA_EN CE NC GND IN OUT IN OUT GND VDD VOUT R508 3 4 2 2 CAM18_EN CE NC GND R2179 R1114N281D-TR-F R1114N281D-TR-F 2 2 R599 0 3 4 75 R528 C522 C523 R504 C502 C503 0 GND GND VIN VOUT CE NC 1u 1u C501 R1114N181D-TR-F C504 VBUS 15 BTF_REG_EN 0.47u 0.47u R507 R514 100K 1608 100K 1608 1u 2.2u R515 10K 3 4 R2239 10K 3 4 LP2985IM5X-3.3 R2177 C1899 R1131N281D5-TR-F C1915 1608 1608 EN BYPASS EN BYPASS 10K C594 100K 1608 1608 C510 C508 NA 4.7u 4.7u USBSENSE NA C512 C513 C1917 C1918 R513 1608 1608 AAT3218IGV-1.5-T1 C511 AAT3218IGV-1.5-T1 C1916 2.2u 4.7u 0.01u 0.01u 1608 1608 51K 1608 1u 1u 1608 1u 1u MEGA_2.8V Camera Analog Power VGA_2.8V Camera Analog Power 1.8V Camera power 1608 1608 3.3V USB Regulator BT and T-Flash Regulator-2.85V 1.5V Regulator for Marita PLL 1.5V Regulator for Wanda PLL
VDIG B B VDIG
R2134 NA RESOUT0n C597 0.1u
TP504 TP505 R2132 R547 IRQ0n 10K R546 R2129 100K TWL93004CZQWR_VINCENNE100K 100K PWRRSTn C4 A9 ONSWA RESETB ONSWAn C5 C1 IND_SINK ONSWBn ONSWB IRQ A7 B8 VBATI ONSWC ONSWC PWRRST V501 DALC208SC6 SPK_MIC_BIAS B7 A6 R2196 1 6 INTLCKB LED1 IO1 IO4 U506 R536 0 1 5 220 VDD VOUT M1 B6 2 5 R570 0 2 RTCCLK XTAL1 LED2 REF2 REF1 GND R553 M2 L1 R540 3 4 XTAL2 32KHZ AUDIO_AMP_EN CE NC C2 3 4 VRTC 0 SIMOFF IO2 IO3 X502 FB504 0 F1 1 5 C527 R1112N241B-TR-F C576 SIMVCC P1 P5 R538 TP502 TP503 TP501 1608 V502 2 6 R509 1K 4.7u 2.2u R542 P2 P6 H1 C533 1u 3 7 VBACKUP 100K 1608 1608 C SIMDAT0 SDAT RB521S-30 P3 P7 FB502 C J3 H3 15K 0 R544 4 8 SIMCLK0 SCLK SIMDAT P4 P8 H2 G1 R543 47 11 9 R535
SRST SIMCLK GND3 GND1 BA501 SIMRST0 G2 R541 0 12 10 SIMRST GND4 GND2 FB501 1K K9 F3 MCLK CDCDA C516 MCLK C8 C530 NA KPD9D-8S-2.54SF R518 0 R516 I2CDAT SDA MIC2P B9 F2 VDD_A VDD_B VBAT_C VRTC VMEM VDIG VCORE C556 C557 R517 0 1 X501 SCL CDCDB C553 FB503 0.068u 100 I2CCLK K3 R521 CLKREQ CLK_REQ 1u 1000p 22p C10 B12 1608 PWRREQn SLEEP VDD_A VBATI U8360-MIC 22K C518 2 R506 R520 J12 A11 0 0 0 R522 0 R519 0 VREF VDD_B 2012 MIC2N L5 2 DEC0 R512 0 0.068u 100 K6 C11 R523 DEC1 EXTLDO EXTLDO 0.22 MOTOR_BATT C521 C514 C549 C538 C539 C544 K7 R2225 R2255 0 1 C515 C520 R551 R563 R560 VBATI DEC2 R600 0 VBAT_C 0.1u R562 H12 M11 CN501 22p 22p 1K IREF VDD_D 0.1u 0.1u 0.1u L12 NA 47p 47p 100K VDD_E L2 VDDLP A12 VBAT_A R2150 0.51 R2256 FB505 M12 D703 VBAT_B 2012 A2 NA 1608 2012 C596 2012 C551
D VDDBUCK C546 KDS160E D A3 VBAT_C A4 Q502 C591 NA 1u C531
PBUCK 10u 10u 0.1u R2254 10u 10u C595 C600 C550 E1 0.1u 0.1u 10u
C534 VBAT_D MOTOR_BATT A5 3D2 S2 4
100K NBUCK 25G1 G2 NA R2127 C588 B4 2826 R593 NA MOD1 1S1 D1 6 2012 2012 10u 2012 L503 22uH 0.22 C7 A1 NTJD4105CT1G 2012 ADSTR SWBUCK B2 V503 VBUCK M10 C3 RB521S-30 VDIG GPA0 VDD_IO VCORE ADCSTR L10 RTEMP GPA1 K10 R2197 0 GPA2 VLOOP L11 B5 GPA3 DACO1 WPOWERSENSE K11 G11 WDCDCREF L501 BLM15BB750SN1J R510 0 CN502 GPA4 DACO2 WRFLOOP J11 H11 WPAREF EARP 13 GPA6 DACO3 JACK_DET J10 N503 VCXOCONT L502 R511 0 15 GPA7 VBACKUP J9 A8 EARM R569 0 17 R571 R2252 GPA12 TXON C507 C532 1u D9 G10 TXON C552 470p BLM15BB750SN1J 1 GPA13 EXPOUT F10 C598 470p C554 1u R566 0 2 NA 10K FF_IN 47p E2 R579 0 3 DCIO DCIN_3 D1 M4 4 E CHREG BEARP C555 E D3 1 X503 5 CHSENSE+ C566 D2 L3 10p 6 R2253 CHSENSE- BEARN 22p C569 JACK_DET D1 7 0 Q501 0 10K G C537 47p N504 IP4025CX20-LF U8360-MIC D2 2 R2191 R2126 R2236 F11 L4 R577 0 NA 8 FGSENSE+ AUXO1 VBATI S1 D3 0 A2 VDIG 9 DCIN_2 MICP C565 C558 C559 S2 D4 L9 R574 620 C585 100u D4 10 0.05 0.05 R899 R875 R847 CCO AFMS_R_INT NA 47p 47p S3 D5 R2205 F12 R572 620 2527 C1 A1 11 FGSENSE- CCO MICN 68 D6 0 12 SI7411DN-T1-E3 0.1 D7 H10 M8 C568 0.068u D2 A3 R591 120K VSS_A MIC1P MICP_INT ATMS 0 G3 R559 0 14 R2130 C599 C548 VSS_B R2131 R567 C6 L8 22K C567 0.068u D1 A4 C583 NA 16 10p 10p VSS_C MIC1N MICN_INT ATMS_CAP 1 3 4 5 6 R2248 68 VBATI VBAT E3 R2249 18 100K VSS_D C575 D1 D10 M6 R581 0 D3 B4 R584 0 D2 D3 D4 D5 SUB AUXI1 ATMS_INT AFMS_R U508 B1 M7 1u R596 120K C-1827541 VSSBUCK MIC2P NLAS4684FCT1 L7 MIC2P C2 A5 GND
C590 SMF05C-TCT
MIC2N ATMS_AD AFMS_L D702 MIC2N R582 0 C586 NA D4 L6 2 TEST AUXI2 B4 10u HOOK C584 100u D5 B5
AFMS_L_INT VDD V+ 2012 R2194 0 B11 K12 R561 0 2527 C2 C4 BDATA GPA5 D501 C571 C570 IN1 NO1 C561
R548 4.7 B3 J4 C562 B1 C3 VIBR AUXO2 68p GND1 GND4 68p U509 LM4809LD MOTOR_BATT R575 0 B2 C4 A2 A4 7 8 C592 100u F C540 GND2 GND5 IN2 NO2 VDD VOUT1 F
1u 2527 C9 E4 RB521S-30 B3 C5 22p C543 DACDAT VSSTH31 C581 22p C541 GND3 GND6
DACDAT 0.1u B10 F4 NA C3 C1 R580 33n R592 120K 1
NA COM1 NC1
DACSTR VSSTH30 47p 1u C542 VIN1 DACSTR A10 G4 6 C593 100u R565 R2135 DACCLK DACCLK VSSTH29 TJATTE2 R587 VOUT2 8.2K 180K R878 H4 A3 A1 R583 33n R597 120K 5 2527 VSSTH28 COM2 NC2 VIN2 C1930 1% 1% 100K R2138 J5
VSSTH27 GND 10p C1931 100K R843 J6 2 3 VSSTH26 C564 BYPASS GND 10p VDIG J7 B1 R588 4 9 PT501 100K VSSTH25 _SHDN BGND VBATI VBATI E10 J8 C573 1u R585 0 R586 100K 2012 10u 47K VSSPA VSSTH24 0 C580 G12 H9 1608 C587 3300p HS_SPK_SEL 1% VDDPA_DAC VSSTH23 1u C12 G9 R589 VDDBUF VSSTH22 1608 C1932 E12 F9 C572 1u C589 4700p 100K R564 0 PASENSE+ VSSTH21 C1933 10p PASENSE+ E11 E9 1608 1608 PASENSE- VSSTH20 10p R576 PASENSE- D11 D8 VBATI PAREG VSSTH19 PAREG D12 D7 0 R558 0 2 4 IOUT IOUT VSSTH18 1 3 HS_AMP_EN U505 TPA2005D1ZQYR D6 R539 C528 R537 D1 B4 VSSTH17 R598 R594 IN- VDD1 R545 0 K1 F7 R578 33n C4 LIN PCMSYN PCMSYN VSSTH1 RIN 0 18K VDD2 C563 LOUT
R554 0 J1 G7 0 ROUT 4.7K 4.7K B1 PCMCLK VSSTH2 C529 NC 10u PCMCLK R556 0 K2 G6 16 5 R534 C1 PCMO VSSTH3 VREF NFSPR 68p IN+ 2012 PCMDATB R555 0 J2 E5 15 6 A4 PCMDATA PCMI VSSTH4 GND NFHPR 18K VO- SPK_LEFT_M GUIDE HOLE E6 14 7 C526
VSSTH5 V+ U507 NFSPL G M5 E7 13 8 A1 D4 G R549 R557 R550 R552 C535 VDDCODEC VSSTH6 1u STBY NFHPL 33n _SD VO+ SPK_LEFT_P OJ500 OJ501 OJ503 OJ504 OJ505
E8 NJM2705PC1 VSSTH7 C574 C577 100K 100K 100K 100K 0.068u F8
VSSTH8 1u GND1 GND2 GND3 GND4 GND5 GND6 GND7 M3 G8 1608 R595 SW1 SW2 PS VDDBEAR VSSTH9 LMON R590
H8 A2 A3 B3 C2 C3 D2 D3
VSSTH10 9 8.2K
H7 12 11 10 10K VSSTH11 M9 H6 VDDADC VSSTH12 H5 R573 0 C582 VSSTH13 3D_OFF K8 G5 R524 1K VSSADC VSSTH14 3D_CTRL1 4700p K5 F5 R525 1K U504 TPA2005D1ZQYR VSSCODEC VSSTH15 3D_CTRL2 R533 R532
1u 1u K4 D5 C524 D1 B4 VSSBEAR VSSTH16 C579 3300p IN- VDD1 1u C545 C547 C536 33n C4 C517 C519 C578 0 18K VDD2 B1 1u 1u 2700p C525 NC R531 C1 68p IN+ A4 18K VO- SPK_RIGHT_M C560 A1 D4 33n _SD VO+ SPK_RIGHT_P GND1 GND2 GND3 GND4 GND5 GND6 GND7
H Engineer: H A2 A3 B3 C2 C3 D2 D3 R530 Jeongseok Lee LG ELECTRONICS INC. AUDIO_AMP_EN Drawn by: Mobile Handsets R&D Center 0 HW Group, Development Lab 6. R529 Jeongseok Lee R&D CHK: TITLE: Size: 100K A2 DOC CTRL CHK: U8550-spfy0106301-1.1 12 1 8 A Vincenne, Regulators MFG ENGR CHK: Page 5 of 7(Baseband 1 of 3) Changed by: Date Changed: Time Changed: QA CHK: REV: Drawing Number: Page: J.S. Lee 2004, May 16 7:25:29 pm 5 12 3 4 5 6 7 8 9 10 11 12
233 8. CIRCUIT DIAGRAM
1 2 3 4 5 6 7 8 9 10 11 12
U604 BGB202_S2 R650 22K 25 15 CLKREQ GPIO10 GP_CLK A 30 A REF_CLK
R651 0 45 50 RESOUT2n RESET_N TCK_JTAG 47 TMS_JTAG 49 TDI_JTAG 44 48 UARTRTS3 GPIO2_CTS_UART TDO_JTAG 41 UARTCTS3 GPIO3_RTS_UART 43 21 UARTRX3 GPIO4_TXD_UART GPIO0 42 20 UARTTX3 GPIO5_RXD_UART GPIO1 4 6 35 PCMDATB GPIO6_DA_IP R606 C647 22p 2 GND2 33 2 1 GND4 R656 33p L602 33p
RTCCLK PCMSYN GPIO7_FSC_IP ANT IN FEED NC2 47 36 17 OUT PCMCLK GPIO8_DCLK_IP VANLI NC1 VTF VCORE VCORE VDIG GND3 GND1 VRTC VUSB VMEM
VEXT15_M 34 22 VMEM ONSWC VEXT15_M PCMDATA GPIO9_DB_IP VANLO 5 RF I/F 16 3 CN601 L601 27nH ANT601 VBAT C2100 and C2101 close to B2100 C643 100p 29 MCLK XTAL1_SYS MM8430-2600B 4 1 R652 120K 28 1 XTAL2_SYS GND1 120K 3 B601 GND2 32.768KHz C608 C607 C642 100p 19 4 0 RTCCLK XTAL1_LPO GND3 RXON MODA MODB MODC MODD TXON RADCLK RADSTR RADDAT BSEL0 GPRFCTRL ANTSW0 ANTSW1 ANTSW2 ANTSW3 PCTL 0 IDATA QDATA DCLK 18 5 0.1u B 0.1u 0.1u 0.1u XTAL2_LPO GND4 B 22p 22p 6 GND5 24 7 0.1u 0.1u 0.1u 0.1u 0.1u 0.1u 0.1u 0.1u 0.1u 0.1u 0.1u 0.1u 0.1u 0.1u 0.1u 0.1u 0.1u GPIO11 GND6 32.768KHz R629 3 C635 0.1u C609 C605 0.1u C622 C623 C604 R604 2 31 8
R605 NA GPIO12 GND7 23 9 GPIO13 GND8 Bluetooth (BGB202/S2) 0 MC-146_12.5pF C621 C610 C601 C603 C619 C602 C620 0.1u C618 0.1u C627 0.1u C629 C612 0.1u C624 C633 C614 C626 C632 C631 C628C630 0.1u C634 C611 C625 VBT 32 10 GPIO14 GND9 11 GND10 39 12 VDDIORF GND11 RTC_GND 38 13 R631 100 R632 NA R627 VDD_IOV GND12 ADR(1:24) 14 GND13 R648 1 27 51 E2 J7 F3 F2 K4 G3 R12 Y14 M20 D20 B12 R1 Y1 AA7 H20 A15 L21 A17 B1 W10 W12 H4 L8 V11 W11 P12 K3 L7 G2 K8 G1 H3 K7 J2 J4 J3 J1 Y12 AA13 AA19 N1 C2 B16 A13 A11 B8 A5 A3 H2 R14 K2 A9 B6 R20 M2 N2 Y10 U1 AA1 AA3 Y6 Y18 V20 N21 B21 A19 K20 E1 J21 AA11 POR_DISABLE GND14 C17 2012 40 52 A1 ADR(1) VREG18 GND15 B17 37 53 A2 ADR(2) VDD18 PGND PCTL DCLK TXON
RXON G13 R649 NA
RTCIN IDATA ADR(3) 1_8V_DECOUP1 1_8V_DECOUP2 RFSTR RFCLK RFDAT C VDDA0 VDDA1 VDDA2 A3 C646 C640 QDATA VDDMC VDDDM VDDE00 VDDE01 VDDE02 VDDC01 VDDC02 VDDC03 VDDC04 VDDC05 VDDC06 VDDC07 VDDC08 VDDC09 VDDC10 VDDC11 VDDC12 VDDC13 VDDC14 VDDC15 VDDC00 VDDC16 VDDC17 VDDC18 RTCCLK RTCOUT VDDRTC C16 ANTSW0 ANTSW1 ANTSW2 ANTSW3 VDDUSB ADR(4) VDDE101 VDDE102 VDDE104 VDDE106 VDDE108 VDDE110 VDDE112 VDDE200 VDDE201 R633 VDDE202 VDDE203 VDDE204 VDDE205 VDDE206 VDDE207 VDDE208 VDDE209 DIRMOD3 DIRMOD0 DIRMOD1 DIRMOD2 A4 0.1u 10u R634 B C606 330p RTCDCON 2012 BANDSEL0 BANDSEL1 Q602 P13 C15 ADR(5) 26 46 SERVICE_N MCLK MCLK RTCBDIS_N A5 RN1107 R3 B15 120K NA SYSCLK0 A6 ADR(6) C641 C645 T2 H12 E SYSCLK1 SYSCLK1 A7 ADR(7) 0.1u 0.1u R616 47 T3 D14 SYSCLK2 SYSCLK2 A8 ADR(8) L3 B14 SERVICE_N A9 ADR(9) R2 C14 C PWRRSTn RESPOW_N A10 ADR(10) C F4 G12 RESOUT0n RESOUT0_N A11 ADR(11) R613 L1 B13 RESOUT1n RESOUT1_N A12 ADR(12) P8 C13 100K RESOUT2n RESOUT2_N A13 ADR(13) U2 H11 RESOUT3n RESOUT3_N A14 ADR(14) U3 D12 C613 RESOUT4_N A15 ADR(15) A1 A2 A7 A8 M1 M2 M7 M8 M8 C12 ADR(16) DAT(0:15) 1000p CLKREQ A16 R615 T4 G11 ADR(17) PWRREQn PWRREQ_N A17 DU0 DU1 DU2 DU3 DU4 DU5 DU6 DU7 D11 J7 E3 ADR(1:24) A18 ADR(18) DAT(15) D15 A25 130K M3 C11 H6 D3 ISSYNCn ISSYNC_N A19 ADR(19) DAT(14) D14 A24 M4 H10 G6 C3 ISEVENTn ISEVENT_N A20 ADR(20) DAT(13) D13 A23 ADR(24) V2 C10 H5 C7 IRQ0_N A21 ADR(21) DAT(12) D12 A22 ADR(23) D10 J4 B7 CLKREQ A22 ADR(22) DAT(11) D11 A21 ADR(22) M14 H9 G4 E6 R628 VGA_IO_OFF GPIO00 A23 ADR(23) DAT(10) D10 A20 ADR(21) P18 C9 J3 B3 100K I2C_VGA_EN GPIO01 A24 ADR(24) DAT(9) D9 A19 ADR(20) R21 G2 B2 TP621 CAM28_VGA_EN GPIO02 DAT(8) D8 A18 ADR(19) R8 A7 DAT(0:15) H7 D2 GPIO03 D0 DAT(0) DAT(7) D7 A17 ADR(18) P9 B7 J6 F8 GPIO04 D1 DAT(1) DAT(6) D6 A16 ADR(17) AA2 C7 G5 E8 CIRES_N_MEGA GPIO05 D2 DAT(2) DAT(5) D5 A15 ADR(16) Y3 D7 J5 F7 IRQ0n HS_AMP_EN GPIO06 D3 DAT(3) DAT(4) D4 A14 ADR(15) W4 C6 H4 D8 D GPIO07 D4 DAT(4) DAT(3) D3 A13 ADR(14) D V5 B5 G3 C8 VDIG UARTRX0 GPIO10 D5 DAT(5) DAT(2) D2 A12 ADR(13) Y4 C5 H3 B8 UARTTX0 GPIO11 D6 DAT(6) DAT(1) D1 A11 ADR(12) V6 D6 H2 E7 AUDIO_AMP_EN GPIO12 D7 DAT(7) DAT(0) D0 A10 ADR(11) R612 W5 B4 VMEM D7 HS_SPK_SEL GPIO13 D8 DAT(8) A9 ADR(10) Y5 C4 K3 F6 NA GPIO14 D9 DAT(9) _F3_CE A8 ADR(9) AA5 D5 G8 E2 PULSESKIP GPIO15 D10 DAT(10) MEM_CS0_N _F2_CE A7 ADR(8) W6 B3 K1 F2 GPIO16 D11 DAT(11) MEM_CS1_N _F1_CE A6 ADR(7) V7 D4 C1 I2C_MEGA_EN GPIO17 D12 DAT(12) A5 ADR(6) W7 C3 R626 C5 B1 CAM28_EN GPIO20 D13 DAT(13) S_CS2 A4 ADR(5) Y7 B2 J1 D1 GPIO21 D14 DAT(14) _S_CS1 A3 ADR(4) P10 A1 E1 3D_OFF GPIO22 D15 DAT(15) 1K A2 ADR(3) P15 D6 F1 GPIO23 D601 MEM_CS2_N _P1_CS A1 ADR(2) N14 J8 ADR(1:24) K2 G1 UARTRX3 GPIO24 CS0_N MEM_CS0_N MEM_CS3_N _P2_CS U603 A0 ADR(1) W20 H7 UARTTX3 GPIO25 D751668A1ZZG_MARITA CS1_N MEM_CS1_N EUSY0211101 UART3 V19 B10 K8 UARTCTS3 GPIO26 CS2_N MEM_CS2_N ADR(24) P_MODE_CRE For the Bluetooth W21 D9 C6 UARTRTS3 GPIO27 CS3_N MEM_CS3_N MEM_CLK CLK U18 C8 VMEM G7 GPIO30 WE_N MEM_WE_N MEM_WAIT_N WAIT T18 D8 CAM18_EN GPIO31 OE_N MEM_OE_N U19 C1 F4 KEY_LED_ONOFF GPIO32 MEMBE0_N MEM_BE0_N RESOUT0n _F_RST U20 D3 R636 100K E4 VMEM GPIO33 MEMBE1_N MEM_BE1_N _F_WP E N15 B9 E5 E BTF_REG_EN GPIO34 MEMADV_N MEM_ADV_N MEM_ADV_N _ADV U21 G8 B6 GPIO35 MEMCLK MEM_CLK F2_VCC1 T19 D2 H8 K6 3D_CTRL2 GPIO36 MEMWAIT_N MEM_WAIT_N MEM_OE_N _F2_OE F2_VCC2 T20 J2 TF_DETECT GPIO37 _F1_OE R19 D19 H1 USBSENSE GPIO40 PDIRES_N LCDRESX _R_OE R18 C19 VCORE VDIG B5 3D_CTRL1 GPIO41 PDIC0 LCDCSX_SUB F1_VCC1 V17 D18 F5 L4 GPIO42 PDIC1 LCDWRX MEM_WE_N _F_WE F1_VCC2 AA21 C20 D5 FOLDER_DET GPIO43 PDIC2 LCDRS LCD I/F _R_WE Y19 MARITA C21 GPIO44 PDIC3 LCDCSX_MAIN R603 NA AA20 E18 R609 F3 Must change to LCD_VSYNC_OUT TP601 GPIO45 PDIC4 LCDRDX R601 MEM_BE1_N _R_UB W19 B18 2 C2 BL_SLEEP_EN GPIO46 PDID0 PDID0 MEM_BE0_N _R_LB Y20 D17 VDIG VDIG 4.7K 3.3K J8 GPIO47 PDID1 PDID1 VCCQ2 C18 B4 K7 PDID2 PDID2 VSS7 VCCQ1
P3 B19 1 3 C4 L3 DACCLK DACCLK PDID3 PDID3 I2CCLK VSS6 VCCQ0 P2 A20 L1 DACDAT DACDAT PDID4 PDID4 Q601 VSS5 P4 H13 R630 R610 PMST3904 L2 K4 DACSTR DACSTR PDID5 PDID5 VSS4 S_VCC P7 G14 L5 ADCSTR ADCSTR PDID6 PDID6 3.3K 1.2K VSS3 B20 R611 NA L6 K5 PDID7 PDID7 VSS2 P_VCC J15 Y2 L7 USBDP USBDP I2CSCL I2CCLK_DRIVER VSS1 J20 W3 R641 100K L8 D4 USBDM USBDM I2CSDA I2CDAT VSS0 F_VPP F USB H19 H18 F USBPUEN USBPUEN CIPCLK CIPCLK H15 0.1u 0.1u 0.1u CIVSYNC CIVSYNC 0.1u N3 G21 HSSLRXCLK HSSLRXCLK CIHSYNC CIHSYNC I2C_MEGA_EN N8 E19 HSSLRX HSSLRX CIRES_N CIRES_N_VGA N4 E20 VDIG R602 C615 C639 C637 HSSL HSSLTXCLK HSSLTXCLK CID0 CID0 C638 N7 E21 U601 A2 C2 HSSLTX HSSLTX CID1 CID1 A3 C3 100K H14 CID2 CID2 L14 F19 IN2 IN1 VDIG
NC0 CID3 CID3 COM2 COM1 E5 F20 B1 B4 NC CID4 CID4 GND DG3516DB-T5-E1V+ G18 VTF CID5 CID5 G19 NC2 NC1 CID6 CID6 NO2 NO1 C616 G20 IRRX IRTX SIMDAT0 SIMRST0_N SIMCLK0 SIMDAT1 SIMRST1_N SIMCLK1 KEYOUT0_N KEYOUT1_N KEYOUT2_N KEYOUT3_N KEYOUT4_N KEYOUT5_N KEYIN2_N KEYIN3_N KEYIN4_N MMCCLK KEYIN0_N KEYIN1_N TCK TDI MMCCMD MMCDAT MSSCLK MSBS MSSDIO PCMCLK PCMSYN PCMDATA PCMDATB IRCTRL RTCK VSSUSB TSYP TSYM VSSE110 VSSE112 VSSE200 VSSE201 VSSE202 VSSE203 VSSE207 VSSE208 VSSE209 VSSE210 VSSE211 VSSMC VSSRTC TRST_N TSXP TSXM TMS TDO TEMU0_N TEMU1_N VSSE00 VSSE01 VSSE02 VSSE100 VSSE102 VSSE104 VSSE106 VSSE108 VSSE204 VSSE205 VSSE206 VSSDM VSSA0 VSSA1 VSSA2 CID7 CID7 0.1u A1 C1 A4 C4 R2244 R2245 L4 V3 Y8 V4 V9 Y9 E4 V8 E3 H8 A2 R4 U4 R9 G4 G9 M7 W8 W1 W2 W9 J14 J19 J18 L15 L19 F18 L18 P20 P19 P14 Y17 V16 V15 Y15 V13 V18 Y21 Y13 P11 V10 Y16 V12 V14 N18 N19 N20 K19 K14 K15 R13 R10 A21 D16 K18 R11 D15 D13 G10 M19 M18 M15 AA9 W18 W17 W15 W16 W14 W13 CAMERA I/F AA17 AA15 NA NA 100K VTF 100K R614 100K S601 500873-0802 JTAG I/F I2CDAT_MEGA GND DAT2_RSV R655 I2CCLK_MEGA R654 470 R621 100K RTC_GND CD_DAT3_CS
MARITATEMU0 R619 TF_DETECT G CMD_DI G MARITATEMU1 TF_CMD VDD I2C_VGA_EN CLK_SCLK R607 R608 TF_CLK VDIG R618 VSS R617 56K R620 56K KEYIN3 KEYIN4 KEYIN0 KEYIN1 KEYIN2 NA 3.3K U602 DAT0_DO SIMRST0 SIMDAT0 SIMCLK0 A3 C3 A2 C2
KEYOUT0 KEYOUT1 KEYOUT2 KEYOUT3 KEYOUT4 KEYOUT5 100K TF_DAT DAT1_RSV PCMCLK PCMSYN IN2 IN1 VDIG PCMDATA PCMDATB COM2 COM1 1u
B1 B4 0.1u GND GND DG3516DB-T5-E1V+ R653
R2242 R2243 470K
NC2 NC1 NO2 NO1 C617 TF_CLK TF_CMD 1608 C644 NA NA 0.1u C636 A1 C1 A4 C4 TF_DAT R2246 R2247
NA NA I2CDAT_VGA Trans-Flash I2CCLK_VGA
H Engineer: H Jeongseok Lee LG ELECTRONICS INC. Drawn by: Mobile Handsets R&D Center Jeongseok Lee HW Group, Development Lab 6. R&D CHK: TITLE: Size: U8550-spfy0106301-1.1 A2 DOC CTRL CHK: 12 1 8 A MARITA, MEMORY, BLUETOOTH MFG ENGR CHK: Page 6 of 7(Baseband Part 2 of 3) Changed by: Date Changed: Time Changed: QA CHK: REV: Drawing Number: Page: mentor Tuesday, September 04, 2003 9:42:54 am 6 1 2 3 4 5 6 7 8 9 10 11 12
234 8. CIRCUIT DIAGRAM
1 2 3 4 5 6 7 8 9 10 11 12 VCAM_2.8V VCAM_1.8V VCAM_2.8V VCAM_2.8V
R741 2.7K R715 0 FLASH3 A KEY_LED_ONOFF R714 0 A FLASH2 R742 R732 0 R729 R728 FLASH1 1 2 3 VBATI R731 0 12 CPO_LTC_FLASH NA CN702 R799 NA Q701 G1 G2 10
EMX18 FB702 R727 R739 0 1 26 CPO_LTC_FLASH C711 2.2u C708 2.2u R740 0 2 25 12 R738 CPO_LTC_LCDBL FL704 10 5 10 5 3 24 R726 0 CIRES_N_MEGA 4 23 1u 5 4 6 3 1u 1u 1u 1u G2 G1 G2 G1 6 5 4 0 5 22 KEY_LED- CID0 OUT4 IN4 INOUT_B4 INOUT_A4 I2CCLK_MEGA 14 6 4 6 21 6 4 C1- C2- C1+ C2+ CPO CID1 OUT3 IN3 INOUT_B3 INOUT_A3 I2CDAT_MEGA 7 3 7 20 7 3 C710 C714 C715 C713 C716 CID2 OUT2 IN2 INOUT_B2 INOUT_A2 SYSCLK1 15 8 2 8 19 8 2 VIN CID3 OUT1 IN1 INOUT_B1 INOUT_A1 CIVSYNC 22 9 1 9 18 9 1 MAIN1 LCDBL1 CIHSYNC Keypad Backlight Control 21 NFA21SL207X1A45L FL706 10 17 R725 0 ICVE21184E150R101FR MAIN2 LCDBL2 7 20 11 16 DVCC MAIN3 LCDBL3 19 12 15 U701 MAIN4 LCDBL4 23 13 14 R718 51 LTC3206EUF AUX1 LCDBL5 CIPCLK
1 10 5 R713 NA SUB1 10 2 R730 G3 G4 R724 R709 NA B BL_SLEEP_EN ENRGB SUB2 G2 G1 C706 C1920 B 24 R711 NA AUX2 CID4 OUT4 IN4 20p NA R733 0 8 16 6 4 10K R710 NA I2CDAT SDA RED FLASH1 CID5 OUT3 IN3 10K 9 17 7 3 NA NA NA I2CCLK_DRIVER SCL GREEN FLASH2 CID6 OUT2 IN2 R737 0 18 8 2 I2CCLK BLUE FLASH3 CID7 OUT1 IN1 VBATI VDIG R734 NA 9 1 CN703 NFA21SL207X1A45L FL705 C701 NA C703 C702 C704 PGND 1 24 SGND IMS IRGB 25 13 11 2 23 12 SPK_LEFT_P SPK_RIGHT_P 3 22 SPK_LEFT_M SPK_RIGHT_M C709 1.3M CAMERA CONNECTOR 4 21 C712 KEYOUT0 KEYIN0 5 20 KEYOUT1 KEYIN1 6 19 2.2u 2.2u KEYOUT2 KEYIN2 7 18 R736 3K KEYOUT3 KEYIN3 R735 12K 8 17 KEYOUT4 KEYIN4 EARP VCAM_VGA_2.8V 9 16 VDIG KEYOUT5 ONSWAn EARM CSPEMI608 FL702 10 15 C1 A1 FILTER2_1 FILTER1_1 PDID7 11 14 C2 A2 KEY_LED- FOLDER_DET FILTER2_2 FILTER1_2 PDID6 12 13 LCD BL and Cam Flash Driver LTC3206 C3 A3 FILTER2_3 FILTER1_3
0 PDID5 C4 A4 NA FILTER2_4 FILTER1_4 PDID4 C5 A5 C FILTER2_5 FILTER1_5 PDID3 C C6 A6 FILTER2_6 FILTER1_6 PDID2 CN701 C7 A7 R723 R721 FILTER2_7 FILTER1_7 PDID1 51 52 C8 A8 FILTER2_8 FILTER1_8 PDID0 KEYPAD B to B Connector 1 50 ICVE21184E150R101FR 2 49
1 9 3 48 G4 G3 G2 G1 SYSCLK1 INOUT_A1 INOUT_B1 2 8 4 47 I2CDAT_VGA INOUT_A2 INOUT_B2 B4 B3 B2 B1 3 7 5 46 I2CCLK_VGA INOUT_A3 INOUT_B3 4 6 6 45 CIVSYNC INOUT_A4 INOUT_B4 7 44
G1 G2 8 43 Must change to LCD_VSYNC_OUT 5 VEXT15_W VRTC VCORE FL703 10 9 42 10 41 IND_SINK FL701 11 40 10 5 C727 0.1u R702 0 12 39 CIRES_N_VGA G2 G1 C725 0.1u 13 38 INOUT_B4 INOUT_A4 LCDWRX C723 0.1u R722 NA 14 37 6 4 INOUT_B3 INOUT_A3 LCDCSX_MAIN C738 0.1u R720 NA 15 36 7 3 INOUT_B2 INOUT_A2 LCDCSX_SUB C722 0.1u R719 NA 16 35 8 2 INOUT_B1 INOUT_A1 LCDRDX C734 0.1u R712 NA R717 0 17 34 R706 0 9 1 D CIHSYNC LCDRESX D C735 0.1u R716 51 18 33 R2241 0 ICVE21184E150R101FR CIPCLK VGA_IO_OFF C736 0.1u 19 32 R704 0 LCDRS VDIG VCORE C724 0.1u 20 31 DCIN_3 LCDBL1 C720 0.1u 21 30 R707 NA KEYIN1 LCDBL2 C721 0.1u 22 29 R703 NA KEYIN2 LCDBL3 C737 0.1u 23 28 R705 NA KEYIN3 LCDBL4 C719 0.1u R701 0 24 27 R708 0 CPO_LTC_LCDBL LCDBL5 C728 0.1u 25 26 53 54 C717 0.1u 47p C705 C726 2.7K 3.3K R745 R744 C1919 C707 C731 0.1u NA C733 0.1u 20p NA
Q702 PMST3904 C718 0.1u 2
WSTR 3 1 T2 E7 E8 E9 E5 E6 B1 D2 K2 R1 U5 B8 U6 B9 A7 A6 A3 B6 C7 C9 A8 C8 B2 C6 A5 A1 A2 B3 C4 B4 G1 M1 F17 L15 T17 E10 D16 A17 B14 A12 H17 K17 R12 U10 R11 R13 U16 R16 N17 C10 R746 A10 LCD, VGA CAMERA CONNECTOR
NA VDD6 VDD5 VDD4 VDD3 VDD2 VDD9 VDD8 VDD7 G16 VDD1 VDD0 VDD21 VDD20 VDD19 VDD18 VDD17 VDD16 VDD15 VDD14 VDD13 E JTAG_TRSTN VDD12 VDD11 VDD10 E EMIF_A1 EMIF_A9 EMIF_A8 EMIF_A7 EMIF_A6 EMIF_A5 EMIF_A4 EMIF_A3 G17 EMIF_A2 C2 VDDA_TX VDDA_RX EMIF_A11 EMIF_A10 EMIF_A12 EMIF_A23 EMIF_A15 EMIF_A14 EMIF_A13 EMIF_A22 EMIF_A21 EMIF_A20 EMIF_A19 EMIF_A18 EMIF_A17 EMIF_A16
JTAG_TCK VDDA_BG EMIF_D0
VCORE G15 VDD_DPLL C1 JTAG_TMS VDD_CLK32 EMIF_D1 F16 F5 JTAG_TDI EMIF_D2
G13 VDDA_CS_APLL E3 JTAG_TDO EMIF_D3 E15 G5 EMU1 EMIF_D4 F13 E1 VDIG EMU0 EMIF_D5 100K F2 EMIF_D6 F1 EMIF_D7 N701 G3 VDIG IO Connector(24Pin) EMIF_D8 IP4022CX20-LF C4 KNATTE G2 X701 EMIF_D9 29 R749 R748 100K R17 H5
RADIO_CLK EMIF_D10 VCC DCIN_2 GND2 WCLK P15 H1 D2 A1 25 RADIO_DAT EMIF_D11 DTMS_i DTMS_e VBAT_GND WDAT M13 H2 D3 A2 1 RADIO_STR EMIF_D12 DFMS_i DFMS_e BATT_ID J2 C3 A3 R758 0 2 EMIF_D13 UARTRX0 CTMS_i CTMS_e HF_MODE R10 J3 D4 A4 R757 100K 3 ADC_I_IN EMIF_D14 UARTTX0 CFMS_i CFMS_e VBACKUP DSR RXIA N10 J5 D5 A5 L702 4 ADC_I_IN_INV EMIF_D15 SERVICE_N VPPFLASH_i VPPFLASH_e PWR_+5V_1 RXIB R9 K3 D1 B1 R756 0 5 ADC_Q_IN EMIF_D16 ONSWBn CTS_ON_i CTS_ON_e BLM18PG121SN1J PWR_+5V_2 RXQA T9 K5 C5 B5 6 ADC_Q_IN_INV EMIF_D17 DCIN_3 DCIO_i DCIO_e ON_SW1 RXQB T10 K1 7 ADC_RXEXTREF_P EMIF_D18 PCM_RXA_IN N9 L1 C739 8 ADC_RXEXTREF_N EMIF_D19 GND5 GND4 GND3 GND2 GND1 PCM_CLK F C730 0.1uM16 L3 9 F ADCSTR AD_STR EMIF_D20 0.1u PCM_SYNC M2 C2 C1 B4 B3 B2 10 EMIF_D21 USB_RX N8 D701 L5 R755 100K 11 DAC_I_OUT EMIF_D22 PCM_TXA_OUT TXIA U8 N1 12 DAC_I_OUT_INV EMIF_D23 PWR_GND_1 TXIB U7 D751980C1ZPHR_WANDA M3 13 DAC_Q_OUT EMIF_D24 RXD TXQA R7 M5 14 DAC_Q_OUT_INV EMIF_D25 TXD TXQB T7 P2 15 DAC_TXEXTRES EMIF_D26 USB_TX P3 R754 0 16 EMIF_D27 USB_PWR B16 R2 R753 0 17 HSSLTX HSSLRX_D EMIF_D28 DCD A16 T1 R752 0 18 HSSLTX_CLK EMIF_D29 RI_TMS HSSLRXCLK A15 N5 19 HSSLTX_D EMIF_D30 PWR_GND_2 HSSLRX C14 U1 20 HSSLRX_CLK WANDA EMIF_D31 RFR_RTS HSSLTXCLK 21 PWR_+4_2V_1 D4 U3 22 ID_BALL EMIF_AWE_N PWR_+4_2V_2 A13 T3 23 IS_SYNC_N EMIF_ARE_N CTS ISSYNCn B12 U2 24 IS_EVENT_N EMIF_AREADY DTR ISEVENTn U12 APLL_ATEST1 VBAT_1 26 27 VBAT_2 C729 U13 N12 28 GND1 MCLK MCLK EXT_MEM_UBUS10 330p T16 T14 CLK32 EXT_MEM_UBUS11 VBUS VBAT G RTCCLK R15 R14 G HCLK EXT_MEM_UBUS12 T15 E17 CLKREQ CLKRQ EXT_FRAME_STROBE USBPUEN 33u N13 6 5 4 3 1 RESOUT1n RESET_N NUF2221W1T2 0.01u USBDM D2 D3 CTS D5 D4 D3 D2 D1 N15 34 12 DACCLK DAC_CLK GND 3_3V RTS 3216 1608
L13 N6 2 5 11 GND C742 1u C740 DACDAT DAC_DAT CPU_IACK USBDP D1 D4 DSR C741 0.1u C743
M15 R5 1 6 10 2 DAC_STR CPU_XF NC4 UTXD V701 DACSTR N7 L701 9 SMF05C-TCT CPU_IRQ1 NC3 URXD E12 R6 8 TP705 UART_TX CPU_IRQ0 USB FILTER NC2 PWR C13 M17 7 GND701 TP704 UART_RX CPU_CLKOUT TP701 VBAT VBAT 6 ON_SW ON_SW 5 VSS10 VSS11 VSS12 VSS13 VSS8 VSS9 VSS14 VSS15 VSS16 VSS17 VSSA_BG VSS0 VSS1 VSS3 VSS4 VSS5 VSS6 VSS7 VSS24 VSS2 VSS20 VSS21 VSS22 VSS23 ANALOG_ENABLE BOOTMODE2 BOOTMODE3 BG_REF APLL_BYPASS BOOTMODE0 BOOTMODE1 GPO0 GPO1 GPO2 TESTMODE CS_BYPASS VSS18 VSS19 VSSA_CS_APLL VSSA_RX VSSA_TX GPO3 GPO4 GPO5 GPO6 GPO7 NC1 UFLS 4 TX TX F3 L2 T4 T6 T8 3 D3 N3 R3 R4 H3 B7 C5 C3 R8 J16 J15 J13 F15 L17 L16 T11 T12 E11 E13 P16 C16 B15 C15 U11 C11 C17 B17 K13 H16 U15 U17 D15 A11 C12 B11 B10 N11 K15 K16 H15 H13
1% RX R747 RX 2 R743 GND GND 1 TP707 TP706 TP708 NA C732 2.5G 3G 0.1u
43K UART1 TP703 TP702
H Engineer: H Jeongseok Lee LG ELECTRONICS INC. Drawn by: Mobile Handsets R&D Center Jeongseok Lee HW Group, Development Lab 6 R&D CHK: TITLE: Size: U8550-spfy0106301-1.1 A2 DOC CTRL CHK: WANDA, Connector 12 1 8 A
MFG ENGR CHK: Page 7 of 7(Baseband Part 3 of 3) Changed by: Date Changed: Time Changed: QA CHK: REV: Drawing Number: Page: J.S. Lee 2004, May 16 7:25:29 pm 7 1 2 3 4 5 6 7 8 9 10 11 12
235 8. CIRCUIT DIAGRAM
1 2 3 45 67 8 9 10
A A
VDIG
R1 100K FOLDER_DET
A3212EEH-T U1 6 1 ONSWAn KEYIN0 KEYIN1 KEYIN2 KEYIN3 KEYIN4 VDD OUTPUT 5 2 SIDE KEY Keypad NC2 NC1 4 C2 GND2 C1 7 3 0.1u PGND GND1 10p SIDE1 CN2 R24 1 2 470 SIDE2 3 R25 4 R27 470 KEYOUT0 SIDE3 470 R28 VA2
Folder Detect TVS3 END1 470 D1 C6 C5 C4 B B NA NA NA INSTPAR
LEFT SPEAKER UCLAMP0501H END 1SS388 FB3 1 4 7 * UP EVL14K02200 EVL14K02200 VA1 G2 EVL14K02200 VA3 TP3 2 + 1 4 5 STAR1 UP1 TP4 1 - FB4 G1 C9 C10 CN4 KEYOUT2 47p 47p
RIGHT SPEAKER 2 5 8 0 DOWN 2 6 9 10 DOWN1 FB1 G2 TP1 2 + TP2 1 - KEYOUT3 FB2 G1 C7 C8 CN3 47p 47p
VBATI VDIG C 3 6 9 # RIGHT C 3 8 7 SHARP1 RIGHT1
CN1 1 24 2 23 3 22 KEYOUT4 R21 0 4 21 R18 0 KEYOUT0 KEYIN0 R20 0 5 20 R19 0 KEYOUT1 KEYIN1 R22 0 6 19 R17 0 KEYOUT2 KEYIN2 R13 0 7 18 R16 0 SEND BACK GAME LEFT KEYOUT3 KEYIN3 CLEAR R12 0 8 17 R8 0 KEYOUT4 KEYIN4 SEND1 CLEAR1 BACK1 GAME1 LEFT1 R11 0 9 16 R7 0 KEYOUT5 ONSWAn 10 15 11 14 R9 0 KEY_LED- FOLDER_DET 12 13 KEYOUT5
AXK6F24345 TVS2 TVS1 INSTPAR INSTPAR MENU SEARCH MULTI CAM OK MENU1 SEARCH1 MULTI1 CAM1 OK1 UCLAMP0501H UCLAMP0501H
D D KEYOUT1 KEYPAD B to B Connector
VBATI
R32 100K PG05DBTFC LEBB-S14H LEBB-S14H LEBB-S14H LEBB-S14H LEBB-S14H LEBB-S14H LEBB-S14H LEBB-S14H LEBB-S14H LEBB-S14H LEBB-S14H LD5 LD8 LD3 LD1 LD6 LD2 LD9 LD7 LD4 Section Date Sign & Name Sheet/ LEBB-S14H LD11 LD10 LD12 LD13 MODEL Sheets LEBB-S14H R33 100K 7/27 U8550(GD32) C3 Designer JS Lee PG05DBTFC 0.1u 2004 1/1 R4 R3 R6 R2 R5 150 150 150 150 150 150 150 150 150 150 150 150 150 R29 R26 R14 R15 R30 R23 R31 R34 100K R10 E Checked PG05DBTFC DRAWING KEY_LED- NAME U8550 Keypad-1.0 Approved
DRAWING Iss.Notice No. Date Name enter draw_number LG Electronics Inc. NO.
1 2 34 5 LGIC(42)-A-5505-10:01 LG Electronics Inc.
236 8. CIRCUIT DIAGRAM
1 2 3 4 5 6 78 9 10
A A
EDLM0005801 VCAM_1.8V VCAM_2.8_DVDD VCAM_2.8_AVDD
LD1 CN1
G1 R1 51 26 1 FLASH3 25 2 FLASH2 24 3 CIRES_1.3M FLASH1 23 4 I2C_CLK CPO_LTC_FLASH 22 5 I2C_DAT CID0 21 6 CID1 20 7 SYSCLK CID2 19 8 CIVSYNC CID3 18 9 CIHSYNC CID4 17 10 CID5 16 11 CID6 B 15 12 B CID7 14 13 CIPCLK G2
TP1 TP2 TP3 TP4 MAIN-to-FPCB Connector
C C VCAM_1.8V VCAM_2.8_AVDD VCAM_2.8_DVDD
CN2 1 24 2 23 I2C_CLK CID7 3 22 I2C_DAT CID6 4 21 CID5 5 20 CIVSYNC CID4 6 19 CIHSYNC CID3 7 18 SYSCLK CID2 8 17 CID1 9 16 CID0 10 15 CIPCLK 11 14 CIRES_1.3M 12 13
D D FPCB-to-1.3M Connector
Section Date Sign & Name Sheet/ MODEL Sheets 03/28 U8550 Designer JS Lee 2005 1/1
E Checked DRAWING NAME U8550 Mega Camera FPCB-1.0 Approved
DRAWING Iss. Notice No. Date Name enter draw_number LG Electronics Inc. NO.
1 23 4 5 LGIC(42)-A-5505-10:01 LG Electronics Inc.
237 8. CIRCUIT DIAGRAM
1 2 3 4 5 6 7 8 9 10
A A
LD2 R3 R6 0 EARP LEBB-S14H 0 C3 NA LD1 R7 0 R4 EARM VCAM_VGA_2.8V VDIG LEBB-S14H 0 C1 C2 NA NA
CN2 51 52 1 50 2 49 CID0 3 48 CID1 4 47 CID2 5 46 CID3 PDID7 B 6 45 B CID4 PDID6 7 44 CID5 PDID5 8 43 CID6 PDID4 9 42 CID7 PDID3 10 41 IND_SINK PDID2 11 40 PDID1 12 39 CIRES_N PDID0 13 38 SYSCLK1 LCDWRX 14 37 I2C_DAT LCDCSX_MAIN 15 36 I2C_CLK LCDCSX_SUB 16 35 CIVSYNC LCDRDX 17 34 CIHSYNC LCDRESX 18 33 CIPCLK VGA_IO_OFF 19 32 LCDRS 20 31 DCIN_3 MLED1 21 30 KEYIN1 MLED2 22 29 KEYIN2 MLED3 23 28 KEYIN3 MLED4 24 27 CPO_LTC_LCDBL MLED5 25 26 53 54
VDIG R11 0 AXK8L50125BG CN3 CN1 C LEFT HEADER C 1 20 R12 10 G1 2 19 R10 0 1 40 3 18 2 39 C4 CENTER 4 17 3 38 5 16 4 37 6 15 1u 5 36 7 14 MAIN-to-LCD Connector 6 35 C5 RIGHT 8 13 7 34 9 12 8 33 10 11 1u 9 32 10 31 AXK720145G 11 30 VDIG 12 29 13 28 R9 OLD - NA 14 27 NEW - 0R VGA Camera Connector 15 26 R1 0 16 25 17 24 100K 18 23 19 22 20 21
G2 D AXK8L40125G D Header
LCD Connector
TP1 TP2 TP3 TP4 TP5 TP6
Section Date Sign & Name Sheet/ MODEL Sheets 04/26 U8550(GD32) Designer JS Lee 2005 1/1
E Checked DRAWING U8550 LCD FPCB-1.0 NAME Approved
DRAWING Iss. Notice No. Date Name enter draw_number LG Electronics Inc. NO.
1 2 3 4 5 LGIC(42)-A-5505-10:01 LG Electronics Inc.
238 9. PCB LAYOUT
239 9. PCB LAYOUT
240 9. PCB LAYOUT
241 9. PCB LAYOUT
242 9. PCB LAYOUT
243 9. PCB LAYOUT
244 9. PCB LAYOUT
245 9. PCB LAYOUT
246 247 10. EXPLODED VIEW & REPLACEMENT PART LIST
10.1 EXPLODED VIEW
69 67 70 71 65 66 68 62 60 63 64 72 58 61 56 59 40 73 53 57 39 54 43 55 47 51 42 38 41 44 48 19 29 18 30 32
17 21 31
12 22 10 78 09 20
07 06
05
04 03 77 76 74 75
01 52 50 49 46
45 33 24 35 37 36 16 28 23 34 15 26 13 27 25 14 23-1 08 11
02
248 NO DESCRIPTION Q'TY DRAWING NO REMARK NO DESCRIPTION Q'TY DRAWING NO REMARK 1 WINDOW LCD(SUB) 1 AWAZ00071## 01:SILVER, 02:GREEN, 03:ORANGE 40 BUTTON,SIDE 1 MBJL0022901 2 DECO(3 LOGO) 1 MDAY0006801 41 PLATE,FACE 1 MPFC0070301 3 DECO FOLDER(UPPER) 1 MDAE00304## 01:SILVER, 02:GREEN, 03:ORANGE 42 COVER,FRONT 1 MCJK00418## 01:SILVER, 02:GREEN, 03:ORANGE 4 TAPE,WINDOW(SUB) 1 MTAE0023901 43 STOPPER 1 MSGY00111## 01:SILVER, 02:GREEN, 03:ORANGE 5 TAPE,DECO 1 MTAA0094701 44 KEYPAD,DIAL 1 MKAA00126## 01:SILVER, 02:GREEN, 03:ORANGE 6 DECO,WINDOW 1 MDAM0006901 45 CAP,RECPTACLE 1 MCCE00212## 01:SILVER, 02:GREEN, 03:ORANGE 7 COVER,FOLDER(UPPER) 1 MCJJ0034201 46 CAP,MULTIMEDIA CARD 1 MCCG00031## 01:SILVER, 02:GREEN, 03:ORANGE 8 PAD,FLEXIBLE FPCB 1 MPBF0012401 47 DOME ASSY,METAL 1 ADCA0035301 9 GASKET(CINNECTOR) 1 MGAD0096801 48 STPPER,HINGE 1 MSGB0010901 10 PAD,LCD(SUB) 1 MPBQ0024101 49 MIKE 2 SGEY0003707 11 DOME ASSY METAL 1 ADCA0035201 50 PAD,SPEAKER 2 MPBN0022601 12 PCB ASSY,FLEXIBLE(LCD) 1 SACY0038001 51 PCB ASSY,KEYPAD 1 SAEY0044401 13 LCD MODULE 1 SVLM0015201 52 SPEAKER 2 SUSY0017501 14 KEYPAD(MOD) 1 MKAZ00233## 01:SILVER, 02:GREEN, 03:ORANGE 53 FRAME,SHILED 1 MFEA0007801 15 TAPE,BUTTON 1 MTAG0001101 54 PCB ASSY,MAIN 1 SAFY0134601 16 BRACKET(MOD) 1 MBFZ0022101 55 BRACKET,CAMERA 1 MBFP0003001 17 PAD,LCD(MAIN) 1 MPBG0034601 56 TAPE(CAMERA MEGA) 1 MTAZ0083001 18 MAGNET 1 MMAA0001801 57 CAMERA,MEGA 1 SVCY0007701 19 COVER,FOLDER(LOWER) 1 MCJH0026901 58 PCB ASSY,FLEXIBLE(CAMERA) 1 SACY0038101 20 SCREW MACHINE,BIND 4 GMEY0009201 59 TAPE(CAMERA FPCB) 1 MTAZ0083201 21 CAP,SCREW(FOLDER,L,UP) 1 MCCH0054501 60 GASKET(MEGA CAMERA FPCB) 1 MGAD0102701 22 CAP,SCREW(FOLDER,R,UP) 1 MCCH0054601 61 GASKET(CONNECTOR) 1 MGAD0096701 23 PAD,CAMERA 1 MPBT0019601 62 VIBRATOR,MOTOR 1 SJMY0007007 23-1 CAMERA,VGA 1 SVCY0009101 63 SCREW MACHINE,BIND 1 GMEY0009201 24 RECEIVER 1 SURY0009501 64 CONTACT,ANTENNA 1 MCIA0014801 25 TAPE,DECO 1 MTAA0094601 65 ANTENNA 1 SNGF00110## 01:GREEN, 02:ORANGE, 03:SILVER 26 DECO,FOLDR(LOWER) 1 MDAF00074## 01:SILVER, 02:GREEN, 03:ORANGE 66 DECO,REAR 1 MDAK00072## 01:SILVER, 02:GREEN, 03:ORANGE 27 TAPE(R,DOWN) 1 MTAZ0086801 67 WINDOW,FLASH 1 MWAH0001601 28 CAP,SCREW(FOLDER,R,DOWN) 1 MCCH00548## 01:SILVER, 02:GREEN, 03:ORANGE 68 WINDOW,CAMERA 1 MWAE0009301 29 TAPE(L,DOWN) 1 MTAZ0086901 69 TAPE(DECO CAMERA) 1 MTAA0095201 30 CAP,SCREW(FOLDER,L,DOWN) 1 MCCH00547## 01:SILVER, 02:GREEN, 03:ORANGE 70 DECO,CAMERA 1 MDAD00130## 01:SILVER, 02:GREEN, 03:ORANGE 31 TAPE,WINDOW(MAIN) 1 MTAD0037101 71 CAP,SCREW(MAIN,L) 1 MCCH0054901 32 WINDOW,LCD(MAIN) 1 AWAB00183## 01:SILVER, 02:GREEN, 03:ORANGE 72 CAP,SCREW(MAIN,R) 1 MCCH0055001 33 DECO,SPEAKER 1 MDAN00068## 01:SILVER, 02:GREEN, 03:ORANGE 73 CAP,MOBILE SWITCH 1 MCCF0030501 34 TAPE(DECO SPEAKER) 1 MTAA0094901 74 HOLDER,CARD 1 MHGB0001401 35 BRACKET,SPEAKER 1 MBFK0001901 75 GASKET(REAR) 1 MGAD0096901 36 TAPE(BRACKET SPEAKER) 1 MTAA0094801 76 COVER,REAR 1 MCJN0037501 37 DECO,FRONT 1 MDAG0012501 77 SCREW MACHINE,BIND 6 GMEY0009201 38 CAP,EARPHONE JACK 1 MCCC00252## 01:SILVER, 02:GREEN, 03:ORANGE 39 HINGE,FOLDER 1 MHFD0011201
249 250 10. EXPLODED VIEW & REPLACEMENT PART LIST
10.2 Replacement Parts Note: This Chapter is used for reference, Part order
Location Level Description Part Number Specification Color Remark No.
1 IMT,FOLDER TIFF0009903 Green
2 AAAY00 ADDITION AAAY0128401 Green
3 MCJA00 COVER,BATTERY MCJA0021801 PC, UV SPRAY White
2 APEY00 PHONE APEY0224002 GREEN COLOR Green
3 ACGG00 COVER ASSY,FOLDER ACGG0061902 Green
Without 4 ABFZ00 BRACKET ASSY ABFZ0005801 MOD BUTTON SUPPORT BRACKET ASS'Y Color
Without 5 MBFZ00 BRACKET MBFZ0022101 SUS 0.5T PRESS, NON-COATING 16 Color
Without 5 MTAZ00 TAPE MTAZ0083301 Color
COVER ASSY, 4 ACGH00 ACGH0035502 Green FOLDER(LOWER)
5 MCJH00 COVER,FOLDER(LOWER) MCJH0026901 PC, UV, Silver 19
5 MDAF00 DECO,FOLDER(LOWER) MDAF0007402 Green 26
5 MFBB00 FILTER,RECEIVER MFBB0012601 Black
Without 5 MMAA00 MAGNET,SWITCH MMAA0001801 DIA3.0x2.0t 18 Color
Without 5 MPBG00 PAD,LCD MPBG0034601 MAIN LCD PAD 17 Color
5 MPBT00 PAD,CAMERA MPBT0019601 Black 23
Without 5 MTAA00 TAPE,DECO MTAA0094601 25 Color
Without 5 MTAD00 TAPE,WINDOW MTAD0037101 0.15T 31 Color
Without 5 MTAZ00 TAPE MTAZ0086801 27 Color
Without 5 MTAZ01 TAPE MTAZ0086901 29 Color
COVER ASSY, 4 ACGJ00 ACGJ0046802 Green FOLDER(UPPER)
5 MCJJ00 COVER,FOLDER(UPPER) MCJJ0034201 Silver 7
5 MDAE00 DECO,FOLDER(UPPER) MDAE0030402 Green 3
5 MDAM00 DECO,WINDOW(SUB) MDAM0006901 AL DICASTING Silver 6
Without 5 MDAY00 DECO MDAY0006801 0.2t 2 Color
BROWN 5 MGAD00 GASKET,SHIELD FORM MGAD0096801 LCD LEFT 9 GOLD
- 251 - 10. EXPLODED VIEW & REPLACEMENT PART LIST
Location Level Description Part Number Specification Color Remark No.
Without 5 MGAD01 GASKET,SHIELD FORM MGAD0097801 LCD-UPPER CONTACT, 2POINT Color
5 MKAZ00 KEYPAD MKAZ0023302 Green 14
5 MPBF00 PAD,FLEXIBLE PCB MPBF0012401 Black 8
5 MPBQ00 PAD,LCD(SUB) MPBQ0024101 Black 10
Without 5 MTAA00 TAPE,DECO MTAA0094701 5 Color
Without 5 MTAE00 TAPE,WINDOW(SUB) MTAE0023901 4 Color
Without 5 MTAG00 TAPE,BUTTON MTAG0001101 MOD KEY FIX TAPE 15 Color
4 ACGK00 COVER ASSY,FRONT ACGK0056402 Green
Without 5 MBFK00 BRACKET,SPEAKER MBFK0001901 CHROME PLATING 35 Color
Without 5 MBJL00 BUTTON,SIDE MBJL0022901 ABS+URETHANE CHROME PLATING 40 Color
5 MCCC00 CAP,EARPHONE JACK MCCC0025202 PC+URETHANE UV COATING Green 38
5 MCCE00 CAP,RECEPTACLE MCCE0021202 URETHANE SPRAY Green 45
5 MCCG00 CAP,MULTIMEDIA CARD MCCG0003102 PC+URETHANE UV COATING Green 46
5 MCJK00 COVER,FRONT MCJK0041802 Green 42
Without 5 MDAG00 DECO,FRONT MDAG0012501 PC,UV 37 Color
5 MDAN00 DECO,SPEAKER MDAN0006802 Green 33
5 MPBN00 PAD,SPEAKER MPBN0022601 Black 50
Without 5 MPFC00 PLATE,FACE MPFC0070301 SUS 0.2T 41 Color
5 MSGY00 STOPPER MSGY0011102 Green 43
Without 5 MTAA00 TAPE,DECO MTAA0094801 36 Color
Without 5 MTAA01 TAPE,DECO MTAA0094901 34 Color
Without 5 MTAA02 TAPE,DECO MTAA0095001 Color
4 AWAB00 WINDOW ASSY,LCD AWAB0018302 MAIN LCD INMOLD WINDOW Green 32
5 BFAA00 FILM,INMOLD BFAA0032102 BLACK Black
Without 5 MWAC00 WINDOW,LCD MWAC0054301 PMMA, INMOLD Color
4 AWAZ00 WINDOW ASSY AWAZ0007102 SUB WINDOW Green 1
5 BFAA00 FILM,INMOLD BFAA0029201 A Transparent
5 MWAF00 WINDOW,LCD(SUB) MWAF0027901 PMMA, TRANSPARENT INMOLD + SILK Silver
4 GMEY00 SCREW MACHINE,BIND GMEY0009201 1.4 mm,3.5 mm,MSWR3(BK) ,B ,+ ,HEAD D=2.7mm Black 20,63,77
- 252 - 10. EXPLODED VIEW & REPLACEMENT PART LIST
Location Level Description Part Number Specification Color Remark No.
4 MCCH00 CAP,SCREW MCCH0054501 SILICON RUBBER, FOLDER LIGHT Gray 21
4 MCCH01 CAP,SCREW MCCH0054601 SILICON RUBBER, FOLDER LEFT Gray 22
4 MCCH02 CAP,SCREW MCCH0054702 Green 30
4 MCCH03 CAP,SCREW MCCH0054802 Green 28
4 MGAZ01 GASKET MGAZ0022702 Gold
4 MGAZ02 GASKET MGAZ0022703 Gold
4 MGAZ04 GASKET MGAZ0022701 Gold
Without 4 MHFD00 HINGE,FOLDER MHFD0011201 39 Color
Without 4 MIDZ00 INSULATOR MIDZ0056801 Color
Without 4 MIDZ02 INSULATOR MIDZ0075001 Color
4 MKAA00 KEYPAD,DIAL MKAA0012602 Green 44
Without 4 MLAC00 LABEL,BARCODE MLAC0003401 EZ LOOKS(user for mechanical) Color
Without 4 MSGB00 STOPPER,HINGE MSGB0010901 PC 48 Color
Without 4 MTAB00 TAPE,PROTECTION MTAB0084901 Color
Without 4 MTAB01 TAPE,PROTECTION MTAB0085001 Color
Without 6 ADCA00 DOME ASSY,METAL ADCA0035201 FOLDER MOD BUTTON DOME ASSY 11 Color
3 ACGM00 COVER ASSY,REAR ACGM0059602 REAR+CAMERA WINDOW ASS'Y Green
4 GMEY00 SCREW MACHINE,BIND GMEY0009201 1.4 mm,3.5 mm,MSWR3(BK) ,B ,+ ,HEAD D=2.7mm Black 20,63,77
4 MCCZ00 CAP MCCZ0008903 White
4 MCIA00 CONTACT,ANTENNA MCIA0014801 PRESS, 0.15T Gold 64
4 MCJN00 COVER,REAR MCJN0037501 PC, UV White 76
4 MDAD00 DECO,CAMERA MDAD0013002 Green 70
4 MDAK00 DECO,REAR MDAK0007202 Green 66
BROWN 4 MGAD00 GASKET,SHIELD FORM MGAD0096701 MAIN CONNECTOR 61 GOLD
BROWN 4 MGAD01 GASKET,SHIELD FORM MGAD0096901 LCD RIGHT 75 GOLD
Without 4 MHGB00 HOLDER,CARD MHGB0001401 74 Color
Without 4 MLAB00 LABEL,A/S MLAB0000601 HUMIDITY STICKER Color
4 MLAN00 LABEL,QUALCOMM MLAN0000601 Black,95C Transparent
4 MPBT00 PAD,CAMERA MPBT0019701 Black
- 253 - 10. EXPLODED VIEW & REPLACEMENT PART LIST
Location Level Description Part Number Specification Color Remark No.
4 MPBZ00 PAD MPBZ0101301 Black
Without 4 MTAA00 TAPE,DECO MTAA0095101 Color
Without 4 MTAA01 TAPE,DECO MTAA0095201 69 Color
Without 4 MTAB00 TAPE,PROTECTION MTAB0089201 Color
Without 4 MTAB01 TAPE,PROTECTION MTAB0089301 Color
Without 4 MWAE00 WINDOW,CAMERA MWAE0009301 0.8T, PMMA SHEET 68 Color
4 MWAH00 WINDOW,FLASH MWAH0001601 PMMA Transparent 67
4 SJMY00 VIBRATOR,MOTOR SJMY0007007 3 V,.08 A,5*12.4 ,Cylinder Motor 62
Without 3 ACGN00 COVER ASSY,CAMERA ACGN0004501 CAMERA + BRACKET ASS'Y Color
Without 4 ABFZ00 BRACKET ASSY ABFZ0005701 MEGA CAMERA BRACKET ASS'Y Color
Without 5 MBFP00 BRACKET,CAMERA MBFP0003001 PC 55 Color
Without 5 MTAZ00 TAPE MTAZ0083001 56 Color
Without 5 MTAZ01 TAPE MTAZ0083201 59 Color
Without 4 MGAD00 GASKET,SHIELD FORM MGAD0102701 60 Color
3 GMEY00 SCREW MACHINE,BIND GMEY0009201 1.4 mm,3.5 mm,MSWR3(BK) ,B ,+ ,HEAD D=2.7mm Black 20,63,77
3 MCCF00 CAP,MOBILE SWITCH MCCF0030501 White 73
3 MCCH00 CAP,SCREW MCCH0054901 SILICON RUBBER, MAIN LEFT White 71
3 MCCH01 CAP,SCREW MCCH0055001 SILICON RUBBER, MAIN RIGHT White 72
Without 3 MFEA00 FRAME,SHIELD MFEA0007801 PC 53 Color
Without 3 MLAK00 LABEL,MODEL MLAK0009001 Color
Without 5 ADCA00 DOME ASSY,METAL ADCA0035301 MAIN BUTTON DOME ASSY 47 Color
5 MGAZ00 GASKET MGAZ0022901 Gold
Without 5 MLAB00 LABEL,A/S MLAB0000601 HUMIDITY STICKER Color
Without 5 MLAC00 LABEL,BARCODE MLAC0003401 EZ LOOKS(user for mechanical) Color
- 254 - 10. EXPLODED VIEW & REPLACEMENT PART LIST
10.2 Replacement Parts Note: This Chapter is used for reference, Part order
Location Level Description Part Number Specification Color Remark No.
4 SACY00 PCB ASSY,FLEXIBLE SACY0038001 Silver 12
PCB ASSY, 5 SACB00 SACB0025501 Green FLEXIBLE,INSERT
5 SACE00 PCB ASSY,FLEXIBLE,SMT SACE0033801 Silver
PCB ASSY,FLEXIBLE,SMT 6 SACC00 SACC0018001 Silver BOTTOM
7C4CAP,CERAMIC,CHIP ECCH0000276 1 uF,10V,Z,Y5V,HD,1608,R/TP
7C5CAP,CERAMIC,CHIP ECCH0000276 1 uF,10V,Z,Y5V,HD,1608,R/TP
CONNECTOR,BOARD TO 7 CN3 ENBY0019501 20 PIN,.4 mm,ETC , ,H=1.5, Socket BOARD
7 LD1 DIODE,LED,CHIP EDLH0006001 Blue ,1608 ,R/TP ,Blue SMD LED
7 LD2 DIODE,LED,CHIP EDLH0006001 Blue ,1608 ,R/TP ,Blue SMD LED
7 R10 RES,CHIP ERHY0000201 0 ohm,1/16W,J,1005,R/TP
7 R11 RES,CHIP ERHY0000201 0 ohm,1/16W,J,1005,R/TP
7 R12 RES,CHIP ERHY0000203 10 ohm,1/16W,J,1005,R/TP
7R3RES,CHIP ERHY0000201 0 ohm,1/16W,J,1005,R/TP
7R4RES,CHIP ERHY0000201 0 ohm,1/16W,J,1005,R/TP
7R6RES,CHIP ERHY0000201 0 ohm,1/16W,J,1005,R/TP
7R7RES,CHIP ERHY0000201 0 ohm,1/16W,J,1005,R/TP
PCB ASSY,FLEXIBLE,SMT 6 SACD00 SACD0026201 Silver TOP
CONNECTOR,BOARD TO 7 CN1 ENBY0020201 40 PIN,0.4 mm,ETC , ,H=0.9, Header BOARD
CONNECTOR,BOARD TO 7 CN2 ENBY0022401 50 PIN,0.4 mm,ETC , ,H=0.9, Header BOARD
7R1RES,CHIP ERHY0000280 100K ohm,1/16W,J,1005,R/TP
7R9RES,CHIP ERHY0000201 0 ohm,1/16W,J,1005,R/TP
6 SPCY00 PCB,FLEXIBLE SPCY0057801 POLYI ,0.5 mm,MULTI-6 ,
4 SURY00 RECEIVER SURY0009501 ASSY ,107 dB,32 ohm,11*07 ,3T 24
4 SVCY00 CAMERA SVCY0009101 CMOS ,VGA , 23_1
MAIN ,M_220*220 S_128*160 ,M_46.5*52.3*4.3 S_7*4.3 4 SVLM00 LCD MODULE SVLM0015201 ,262k ,TFT ,TM ,(SOURCE)HD66781 (GATE)HD66783 13 ,SUB LCD:DRIVE IC(LGDP4511) ,
3.0 ,-2.0 dBd,Green 4 SNGF00 ANTENNA,GSM,FIXED SNGF0011001 65 ,GSM900+DCS1800+PCS1900+WCDMA2100,fixed
4 SACY00 PCB ASSY,FLEXIBLE SACY0038101 Silver 58
- 255 - 10. EXPLODED VIEW & REPLACEMENT PART LIST
Location Level Description Part Number Specification Color Remark No.
5 SACE00 PCB ASSY,FLEXIBLE,SMT SACE0033901 Silver
PCB ASSY,FLEXIBLE,SMT 6 SACD00 SACD0026301 Silver TOP
CONNECTOR,BOARD TO 7 CN1 ENBY0025201 26 PIN,0.4 mm,ETC , ,H=0.9, Header BOARD
CONNECTOR,BOARD TO 7 CN2 ENBY0019101 24 PIN,0.4 mm,STRAIGHT , ,H1.5, MALE BOARD
7 LD1 DIODE,LED,MODULE EDLM0005502 White ,3 LED,3.5*2.8*1.8 ,R/TP ,Flash LED
7R1RES,CHIP ERHY0000214 51 ohm,1/16W,J,1005,R/TP
6 SPCY00 PCB,FLEXIBLE SPCY0058201 POLYI ,0.5 mm,BUILD-UP 6 ,FPCB-CAMERA
4 SVCY00 CAMERA SVCY0007701 CMOS ,MEGA ,1.3M ESS Sensor 57
3 SAEY00 PCB ASSY,KEYPAD SAEY0044401 Silver 51
PCB ASSY, 4 SAEB00 SAEB0011701 Silver KEYPAD,INSERT
5 SAKY00 PCB ASSY,SIDEKEY SAKY0005401 Silver
5 SUSY00 SPEAKER SUSY0017501 ASSY ,8 ohm,90 dB,15 mm,*14mm, 3.7T 52
4 SAEE00 PCB ASSY,KEYPAD,SMT SAEE0013301 Silver
PCB ASSY,KEYPAD,SMT 5 SAEC00 SAEC0012701 Silver BOTTOM
6C1CAP,CERAMIC,CHIP ECCH0000110 10 pF,50V,D,NP0,TC,1005,R/TP
6 C10 CAP,CERAMIC,CHIP ECCH0000122 47 pF,50V,J,NP0,TC,1005,R/TP
6C2CAP,CERAMIC,CHIP ECCH0000182 0.1 uF,10V ,K ,X5R ,HD ,1005 ,R/TP
6C3CAP,CERAMIC,CHIP ECCH0000182 0.1 uF,10V ,K ,X5R ,HD ,1005 ,R/TP
6C7CAP,CERAMIC,CHIP ECCH0000122 47 pF,50V,J,NP0,TC,1005,R/TP
6C8CAP,CERAMIC,CHIP ECCH0000122 47 pF,50V,J,NP0,TC,1005,R/TP
6C9CAP,CERAMIC,CHIP ECCH0000122 47 pF,50V,J,NP0,TC,1005,R/TP
CONNECTOR,BOARD TO 6 CN1 ENBY0002107 24 PIN,.5 mm,STRAIGHT ,SILVER , BOARD
CONNECTOR,BOARD TO 6 CN3 ENBY0001803 2 PIN,1.27 mm,STRAIGHT ,SILVER , BOARD
CONNECTOR,BOARD TO 6 CN4 ENBY0001803 2 PIN,1.27 mm,STRAIGHT ,SILVER , BOARD
1-1G1A ,40 V,300 A,R/TP ,Silicon Epitaxial Schottky Barrier 6D1DIODE,SWITCHING EDSY0010401 Type Diode
6 FB1 FILTER,BEAD,CHIP SFBH0007103 75 ohm,1005 ,CHIP BEAD, 300mA
6 FB2 FILTER,BEAD,CHIP SFBH0007103 75 ohm,1005 ,CHIP BEAD, 300mA
6 FB3 FILTER,BEAD,CHIP SFBH0007103 75 ohm,1005 ,CHIP BEAD, 300mA
6 FB4 FILTER,BEAD,CHIP SFBH0007103 75 ohm,1005 ,CHIP BEAD, 300mA
6R1RES,CHIP ERHY0000280 100K ohm,1/16W,J,1005,R/TP
- 256 - 10. EXPLODED VIEW & REPLACEMENT PART LIST
Location Level Description Part Number Specification Color Remark No.
6 R11 RES,CHIP ERHY0000201 0 ohm,1/16W,J,1005,R/TP
6 R12 RES,CHIP ERHY0000201 0 ohm,1/16W,J,1005,R/TP
6 R13 RES,CHIP ERHY0000201 0 ohm,1/16W,J,1005,R/TP
6 R16 RES,CHIP ERHY0000201 0 ohm,1/16W,J,1005,R/TP
6 R17 RES,CHIP ERHY0000201 0 ohm,1/16W,J,1005,R/TP
6 R18 RES,CHIP ERHY0000201 0 ohm,1/16W,J,1005,R/TP
6 R19 RES,CHIP ERHY0000201 0 ohm,1/16W,J,1005,R/TP
6 R20 RES,CHIP ERHY0000201 0 ohm,1/16W,J,1005,R/TP
6 R21 RES,CHIP ERHY0000201 0 ohm,1/16W,J,1005,R/TP
6 R22 RES,CHIP ERHY0000201 0 ohm,1/16W,J,1005,R/TP
6 R24 RES,CHIP ERHY0000233 470 ohm,1/16W,J,1005,R/TP
6 R25 RES,CHIP ERHY0000233 470 ohm,1/16W,J,1005,R/TP
6 R27 RES,CHIP ERHY0000233 470 ohm,1/16W,J,1005,R/TP
6 R28 RES,CHIP ERHY0000233 470 ohm,1/16W,J,1005,R/TP
6R7RES,CHIP ERHY0000201 0 ohm,1/16W,J,1005,R/TP
6R8RES,CHIP ERHY0000201 0 ohm,1/16W,J,1005,R/TP
6R9RES,CHIP ERHY0000201 0 ohm,1/16W,J,1005,R/TP
SOD-523 ,5 V,240 W,R/TP ,SINGLE LINE TVS DIODE FOR 6 TVS1 DIODE,TVS EDTY0007301 ESD
SOD-523 ,5 V,240 W,R/TP ,SINGLE LINE TVS DIODE FOR 6 TVS2 DIODE,TVS EDTY0007301 ESD
SOD-523 ,5 V,240 W,R/TP ,SINGLE LINE TVS DIODE FOR 6 TVS3 DIODE,TVS EDTY0007301 ESD
6U1IC EUSY0200301 Leadless chip ,6 PIN,R/TP ,Hall S/W, Pb Free
6 VA1 VARISTOR SEVY0000702 14 V,10% ,SMD ,
6 VA2 VARISTOR SEVY0000702 14 V,10% ,SMD ,
6 VA3 VARISTOR SEVY0000702 14 V,10% ,SMD ,
PCB ASSY,KEYPAD,SMT 5 SAED00 SAED0012901 Silver TOP
6 LD1 DIODE,LED,CHIP EDLH0006001 Blue ,1608 ,R/TP ,Blue SMD LED
6 LD10 DIODE,LED,CHIP EDLH0006001 Blue ,1608 ,R/TP ,Blue SMD LED
6 LD11 DIODE,LED,CHIP EDLH0006001 Blue ,1608 ,R/TP ,Blue SMD LED
6 LD12 DIODE,LED,CHIP EDLH0006001 Blue ,1608 ,R/TP ,Blue SMD LED
6 LD13 DIODE,LED,CHIP EDLH0006001 Blue ,1608 ,R/TP ,Blue SMD LED
6 LD14 DIODE,LED,CHIP EDLH0006001 Blue ,1608 ,R/TP ,Blue SMD LED
6 LD15 DIODE,LED,CHIP EDLH0006001 Blue ,1608 ,R/TP ,Blue SMD LED
6 LD16 DIODE,LED,CHIP EDLH0006001 Blue ,1608 ,R/TP ,Blue SMD LED
- 257 - 10. EXPLODED VIEW & REPLACEMENT PART LIST
Location Level Description Part Number Specification Color Remark No.
6 LD17 DIODE,LED,CHIP EDLH0006001 Blue ,1608 ,R/TP ,Blue SMD LED
6 LD18 DIODE,LED,CHIP EDLH0006001 Blue ,1608 ,R/TP ,Blue SMD LED
6 LD19 DIODE,LED,CHIP EDLH0006001 Blue ,1608 ,R/TP ,Blue SMD LED
6 LD2 DIODE,LED,CHIP EDLH0006001 Blue ,1608 ,R/TP ,Blue SMD LED
6 LD3 DIODE,LED,CHIP EDLH0006001 Blue ,1608 ,R/TP ,Blue SMD LED
6 LD4 DIODE,LED,CHIP EDLH0006001 Blue ,1608 ,R/TP ,Blue SMD LED
6 LD5 DIODE,LED,CHIP EDLH0006001 Blue ,1608 ,R/TP ,Blue SMD LED
6 LD6 DIODE,LED,CHIP EDLH0006001 Blue ,1608 ,R/TP ,Blue SMD LED
6 LD7 DIODE,LED,CHIP EDLH0006001 Blue ,1608 ,R/TP ,Blue SMD LED
6 LD8 DIODE,LED,CHIP EDLH0006001 Blue ,1608 ,R/TP ,Blue SMD LED
6 LD9 DIODE,LED,CHIP EDLH0006001 Blue ,1608 ,R/TP ,Blue SMD LED
6 R10 RES,CHIP ERHY0000223 150 ohm,1/16W,J,1005,R/TP
6 R14 RES,CHIP ERHY0000223 150 ohm,1/16W,J,1005,R/TP
6 R15 RES,CHIP ERHY0000223 150 ohm,1/16W,J,1005,R/TP
6R2RES,CHIP ERHY0000223 150 ohm,1/16W,J,1005,R/TP
6 R23 RES,CHIP ERHY0000223 150 ohm,1/16W,J,1005,R/TP
6 R26 RES,CHIP ERHY0000223 150 ohm,1/16W,J,1005,R/TP
6 R29 RES,CHIP ERHY0000223 150 ohm,1/16W,J,1005,R/TP
6R3RES,CHIP ERHY0000223 150 ohm,1/16W,J,1005,R/TP
6 R30 RES,CHIP ERHY0000223 150 ohm,1/16W,J,1005,R/TP
6 R31 RES,CHIP ERHY0000223 150 ohm,1/16W,J,1005,R/TP
6 R35 RES,CHIP ERHY0000223 150 ohm,1/16W,J,1005,R/TP
6 R36 RES,CHIP ERHY0000223 150 ohm,1/16W,J,1005,R/TP
6 R37 RES,CHIP ERHY0000223 150 ohm,1/16W,J,1005,R/TP
6 R38 RES,CHIP ERHY0000223 150 ohm,1/16W,J,1005,R/TP
6 R39 RES,CHIP ERHY0000223 150 ohm,1/16W,J,1005,R/TP
6R4RES,CHIP ERHY0000223 150 ohm,1/16W,J,1005,R/TP
6 R40 RES,CHIP ERHY0000223 150 ohm,1/16W,J,1005,R/TP
6R5RES,CHIP ERHY0000223 150 ohm,1/16W,J,1005,R/TP
6R6RES,CHIP ERHY0000223 150 ohm,1/16W,J,1005,R/TP
6 TVS4 DIODE,TVS EDTY0008501 TFSC ,5 V,50 W,R/TP ,small size
6 TVS5 DIODE,TVS EDTY0008501 TFSC ,5 V,50 W,R/TP ,small size
6 TVS6 DIODE,TVS EDTY0008501 TFSC ,5 V,50 W,R/TP ,small size
5 SPEY00 PCB,KEYPAD SPEY0035701 FR-4 ,0.5 mm,DOUBLE ,
- 258 - 10. EXPLODED VIEW & REPLACEMENT PART LIST
Location Level Description Part Number Specification Color Remark No.
3 SAFY00 PCB ASSY,MAIN SAFY0134601 Silver 54
4 SAFB00 PCB ASSY,MAIN,INSERT SAFB0053501 Green
5 SBCL00 BATTERY,CELL,LITHIUM SBCL0001303 2 V,1 mAh,COIN ,SOLDER TYPE BACKUP BATTERY
4 SAFF00 PCB ASSY,MAIN,SMT SAFF0059401 Silver
PCB ASSY,MAIN,SMT 5 SAFC00 SAFC0065801 Green BOTTOM
6 ANT601 ANTENNA,GSM,FIXED SNGF0008301 3.0 ,-2.0 dBd, ,bluetooth_chip, 9.0x3.0x1.5
6 B201 X-TAL EXXY0016801 13 MHz,19 PPM,10 pF,40 ohm,SMD ,5*3.20*0.7 ,
6 C101 CAP,CERAMIC,CHIP ECCH0000173 1.2 pF,16V ,B ,NP0 ,TC ,1005 ,R/TP
6 C102 CAP,CERAMIC,CHIP ECCH0000155 10 nF,16V,K,X7R,HD,1005,R/TP
6 C103 CAP,CERAMIC,CHIP ECCH0000186 33 pF,50V ,J ,NP0 ,TC ,1005 ,R/TP
6 C104 CAP,CERAMIC,CHIP ECCH0000110 10 pF,50V,D,NP0,TC,1005,R/TP
6 C105 CAP,CERAMIC,CHIP ECCH0000110 10 pF,50V,D,NP0,TC,1005,R/TP
6 C106 CAP,CERAMIC,CHIP ECCH0000110 10 pF,50V,D,NP0,TC,1005,R/TP
6 C107 CAP,CERAMIC,CHIP ECCH0000110 10 pF,50V,D,NP0,TC,1005,R/TP
6 C108 CAP,CERAMIC,CHIP ECCH0000155 10 nF,16V,K,X7R,HD,1005,R/TP
6 C109 CAP,CERAMIC,CHIP ECCH0000155 10 nF,16V,K,X7R,HD,1005,R/TP
6 C110 CAP,CERAMIC,CHIP ECCH0000155 10 nF,16V,K,X7R,HD,1005,R/TP
6 C112 CAP,CERAMIC,CHIP ECCH0000161 33 nF,16V,K,X7R,HD,1005,R/TP
6 C113 CAP,CERAMIC,CHIP ECCH0000168 0.1 uF,16V,Z,Y5V,HD,1005,R/TP
6 C114 CAP,CERAMIC,CHIP ECCH0005705 10 uF,6.3V ,K ,X5R ,HD ,2012 ,R/TP
6 C117 CAP,CERAMIC,CHIP ECCH0005705 10 uF,6.3V ,K ,X5R ,HD ,2012 ,R/TP
6 C1899 CAP,CERAMIC,CHIP ECCH0006201 4.7 uF,6.3V ,K ,X5R ,TC ,1608 ,R/TP
6 C1915 CAP,CERAMIC,CHIP ECCH0006201 4.7 uF,6.3V ,K ,X5R ,TC ,1608 ,R/TP
6 C1916 CAP,CERAMIC,CHIP ECCH0000155 10 nF,16V,K,X7R,HD,1005,R/TP
6 C1917 CAP,CERAMIC,CHIP ECCH0000276 1 uF,10V,Z,Y5V,HD,1608,R/TP
6 C1918 CAP,CHIP,MAKER ECZH0003501 1 uF,6.3V ,K ,X5R ,HD ,1608 ,R/TP
6 C201 CAP,CERAMIC,CHIP ECCH0000117 27 pF,50V,J,NP0,TC,1005,R/TP
6 C202 CAP,CERAMIC,CHIP ECCH0000155 10 nF,16V,K,X7R,HD,1005,R/TP
6 C203 CAP,CERAMIC,CHIP ECCH0000117 27 pF,50V,J,NP0,TC,1005,R/TP
6 C204 CAP,CERAMIC,CHIP ECCH0000147 2.2 nF,50V,K,X7R,HD,1005,R/TP
6 C206 CAP,CERAMIC,CHIP ECCH0000115 22 pF,50V,J,NP0,TC,1005,R/TP
6 C207 CAP,CERAMIC,CHIP ECCH0000115 22 pF,50V,J,NP0,TC,1005,R/TP
6 C208 CAP,CERAMIC,CHIP ECCH0000115 22 pF,50V,J,NP0,TC,1005,R/TP
6 C209 CAP,CERAMIC,CHIP ECCH0000180 3.3 pF,50V ,C ,NP0 ,TC ,1005 ,R/TP
- 259 - 10. EXPLODED VIEW & REPLACEMENT PART LIST
Location Level Description Part Number Specification Color Remark No.
6 C210 CAP,CERAMIC,CHIP ECCH0000180 3.3 pF,50V ,C ,NP0 ,TC ,1005 ,R/TP
6 C211 CAP,CERAMIC,CHIP ECCH0000115 22 pF,50V,J,NP0,TC,1005,R/TP
6 C212 CAP,CERAMIC,CHIP ECCH0000115 22 pF,50V,J,NP0,TC,1005,R/TP
6 C214 CAP,CERAMIC,CHIP ECCH0000167 0.1 uF,6.3V,K,X5R,HD,1005,R/TP
6 C215 CAP,CERAMIC,CHIP ECCH0000115 22 pF,50V,J,NP0,TC,1005,R/TP
6 C216 CAP,CERAMIC,CHIP ECCH0000138 390 pF,50V,K,X7R,HD,1005,R/TP
6 C217 CAP,CERAMIC,CHIP ECCH0000152 5.6 nF,25V,K,X7R,HD,1005,R/TP
6 C218 CAP,CERAMIC,CHIP ECCH0000147 2.2 nF,50V,K,X7R,HD,1005,R/TP
6 C219 CAP,CERAMIC,CHIP ECCH0000155 10 nF,16V,K,X7R,HD,1005,R/TP
6 C220 CAP,CERAMIC,CHIP ECCH0000701 1.2 pF,50V ,C ,NP0 ,TC ,1005 ,R/TP
6 C221 CAP,CERAMIC,CHIP ECCH0000127 82 pF,50V,J,NP0,TC,1005,R/TP
6 C222 CAP,CERAMIC,CHIP ECCH0000147 2.2 nF,50V,K,X7R,HD,1005,R/TP
6 C223 CAP,CERAMIC,CHIP ECCH0000155 10 nF,16V,K,X7R,HD,1005,R/TP
6 C224 CAP,CERAMIC,CHIP ECCH0000155 10 nF,16V,K,X7R,HD,1005,R/TP
6 C225 CAP,CERAMIC,CHIP ECCH0000115 22 pF,50V,J,NP0,TC,1005,R/TP
6 C226 CAP,CERAMIC,CHIP ECCH0000155 10 nF,16V,K,X7R,HD,1005,R/TP
6 C227 CAP,CERAMIC,CHIP ECCH0000155 10 nF,16V,K,X7R,HD,1005,R/TP
6 C228 CAP,CERAMIC,CHIP ECCH0000155 10 nF,16V,K,X7R,HD,1005,R/TP
6 C229 CAP,CERAMIC,CHIP ECCH0000155 10 nF,16V,K,X7R,HD,1005,R/TP
6 C230 CAP,CERAMIC,CHIP ECCH0000137 330 pF,50V ,K ,X7R ,HD ,1005 ,R/TP
6 C231 CAP,CERAMIC,CHIP ECCH0000122 47 pF,50V,J,NP0,TC,1005,R/TP
6 C232 CAP,CERAMIC,CHIP ECCH0000181 4.7 pF,50V ,C ,NP0 ,TC ,1005 ,R/TP
6 C233 CAP,CERAMIC,CHIP ECCH0000124 56 pF,50V,J,NP0,TC,1005,R/TP
6 C234 CAP,CERAMIC,CHIP ECCH0000175 2.7 pF,50V ,B ,NP0 ,TC ,1005 ,R/TP
6 C235 CAP,CERAMIC,CHIP ECCH0000115 22 pF,50V,J,NP0,TC,1005,R/TP
6 C236 CAP,CERAMIC,CHIP ECCH0000115 22 pF,50V,J,NP0,TC,1005,R/TP
6 C237 CAP,CERAMIC,CHIP ECCH0000155 10 nF,16V,K,X7R,HD,1005,R/TP
6 C238 CAP,CERAMIC,CHIP ECCH0000155 10 nF,16V,K,X7R,HD,1005,R/TP
6 C239 CAP,CERAMIC,CHIP ECCH0000115 22 pF,50V,J,NP0,TC,1005,R/TP
6 C240 CAP,CERAMIC,CHIP ECCH0000115 22 pF,50V,J,NP0,TC,1005,R/TP
6 C313 CAP,CERAMIC,CHIP ECCH0000155 10 nF,16V,K,X7R,HD,1005,R/TP
6 C314 CAP,CERAMIC,CHIP ECCH0000155 10 nF,16V,K,X7R,HD,1005,R/TP
6 C315 CAP,CERAMIC,CHIP ECCH0000110 10 pF,50V,D,NP0,TC,1005,R/TP
6 C316 CAP,CERAMIC,CHIP ECCH0000115 22 pF,50V,J,NP0,TC,1005,R/TP
- 260 - 10. EXPLODED VIEW & REPLACEMENT PART LIST
Location Level Description Part Number Specification Color Remark No.
6 C317 CAP,CERAMIC,CHIP ECCH0000115 22 pF,50V,J,NP0,TC,1005,R/TP
6 C318 CAP,CERAMIC,CHIP ECCH0000128 100 pF,50V,J,NP0,TC,1005,R/TP
6 C319 CAP,CERAMIC,CHIP ECCH0000181 4.7 pF,50V ,C ,NP0 ,TC ,1005 ,R/TP
6 C320 CAP,CERAMIC,CHIP ECCH0000186 33 pF,50V ,J ,NP0 ,TC ,1005 ,R/TP
6 C321 CAP,CERAMIC,CHIP ECCH0000186 33 pF,50V ,J ,NP0 ,TC ,1005 ,R/TP
6 C322 CAP,CERAMIC,CHIP ECCH0000155 10 nF,16V,K,X7R,HD,1005,R/TP
6 C323 CAP,CERAMIC,CHIP ECCH0000110 10 pF,50V,D,NP0,TC,1005,R/TP
6 C324 CAP,CERAMIC,CHIP ECCH0000110 10 pF,50V,D,NP0,TC,1005,R/TP
6 C325 CAP,CERAMIC,CHIP ECCH0000155 10 nF,16V,K,X7R,HD,1005,R/TP
6 C326 CAP,CERAMIC,CHIP ECCH0000110 10 pF,50V,D,NP0,TC,1005,R/TP
6 C327 CAP,CERAMIC,CHIP ECCH0000105 4 pF,50V,C,NP0,TC,1005,R/TP
6 C328 CAP,CERAMIC,CHIP ECCH0000122 47 pF,50V,J,NP0,TC,1005,R/TP
6 C330 CAP,CERAMIC,CHIP ECCH0000115 22 pF,50V,J,NP0,TC,1005,R/TP
6 C331 CAP,CERAMIC,CHIP ECCH0000115 22 pF,50V,J,NP0,TC,1005,R/TP
6 C332 CAP,CERAMIC,CHIP ECCH0000155 10 nF,16V,K,X7R,HD,1005,R/TP
6 C333 CAP,CERAMIC,CHIP ECCH0000128 100 pF,50V,J,NP0,TC,1005,R/TP
6 C334 CAP,CERAMIC,CHIP ECCH0000130 150 pF,50V ,J ,SL ,TC ,1005 ,R/TP
6 C335 CAP,CERAMIC,CHIP ECCH0000115 22 pF,50V,J,NP0,TC,1005,R/TP
6 C336 CAP,CERAMIC,CHIP ECCH0000149 3.3 nF,50V,K,X7R,HD,1005,R/TP
6 C337 CAP,CERAMIC,CHIP ECCH0000155 10 nF,16V,K,X7R,HD,1005,R/TP
6 C401 CAP,CERAMIC,CHIP ECCH0000130 150 pF,50V ,J ,SL ,TC ,1005 ,R/TP
6 C402 CAP,CERAMIC,CHIP ECCH0000128 100 pF,50V,J,NP0,TC,1005,R/TP
6 C403 CAP,CERAMIC,CHIP ECCH0000115 22 pF,50V,J,NP0,TC,1005,R/TP
6 C404 CAP,CERAMIC,CHIP ECCH0000115 22 pF,50V,J,NP0,TC,1005,R/TP
6 C405 CAP,CERAMIC,CHIP ECCH0000128 100 pF,50V,J,NP0,TC,1005,R/TP
6 C406 CAP,CERAMIC,CHIP ECCH0000186 33 pF,50V ,J ,NP0 ,TC ,1005 ,R/TP
6 C408 CAP,CERAMIC,CHIP ECCH0000128 100 pF,50V,J,NP0,TC,1005,R/TP
6 C410 CAP,CERAMIC,CHIP ECCH0000186 33 pF,50V ,J ,NP0 ,TC ,1005 ,R/TP
6 C411 INDUCTOR,CHIP ELCH0005001 2.2 nH,S ,1005 ,R/TP ,
6 C412 CAP,CERAMIC,CHIP ECCH0000186 33 pF,50V ,J ,NP0 ,TC ,1005 ,R/TP
6 C420 CAP,CERAMIC,CHIP ECCH0005705 10 uF,6.3V ,K ,X5R ,HD ,2012 ,R/TP
6 C422 CAP,CERAMIC,CHIP ECCH0005705 10 uF,6.3V ,K ,X5R ,HD ,2012 ,R/TP
6 C423 CAP,CERAMIC,CHIP ECCH0000115 22 pF,50V,J,NP0,TC,1005,R/TP
6 C424 CAP,CERAMIC,CHIP ECCH0000155 10 nF,16V,K,X7R,HD,1005,R/TP
- 261 - 10. EXPLODED VIEW & REPLACEMENT PART LIST
Location Level Description Part Number Specification Color Remark No.
6 C507 CAP,CERAMIC,CHIP ECCH0000122 47 pF,50V,J,NP0,TC,1005,R/TP
6 C514 CAP,CERAMIC,CHIP ECCH0000115 22 pF,50V,J,NP0,TC,1005,R/TP
6 C515 CAP,CERAMIC,CHIP ECCH0000122 47 pF,50V,J,NP0,TC,1005,R/TP
6 C516 CAP,CERAMIC,CHIP ECCH0000165 68 nF,6.3V,K,X5R,HD,1005,R/TP
6 C518 CAP,CERAMIC,CHIP ECCH0000165 68 nF,6.3V,K,X5R,HD,1005,R/TP
6 C520 CAP,CERAMIC,CHIP ECCH0000122 47 pF,50V,J,NP0,TC,1005,R/TP
6 C521 CAP,CERAMIC,CHIP ECCH0000115 22 pF,50V,J,NP0,TC,1005,R/TP
6 C522 CAP,TANTAL,CHIP ECTH0002702 1 uF,16V ,M ,STD ,1608 ,R/TP
6 C523 CAP,CERAMIC,CHIP ECCH0000279 0.47 uF,10V ,Z ,Y5V ,HD ,1608 ,R/TP
6 C527 CAP,CHIP,MAKER ECZH0026301 4.7 uF,6.3V ,Z ,Y5V ,HD ,1608 ,R/TP
6 C531 CAP,CERAMIC,CHIP ECCH0000276 1 uF,10V,Z,Y5V,HD,1608,R/TP
6 C532 CAP,CERAMIC,CHIP ECCH0000276 1 uF,10V,Z,Y5V,HD,1608,R/TP
6 C533 CAP,CERAMIC,CHIP ECCH0000276 1 uF,10V,Z,Y5V,HD,1608,R/TP
6 C534 CAP,CERAMIC,CHIP ECCH0000168 0.1 uF,16V,Z,Y5V,HD,1005,R/TP
6 C535 CAP,CERAMIC,CHIP ECCH0000165 68 nF,6.3V,K,X5R,HD,1005,R/TP
6 C536 CAP,CERAMIC,CHIP ECCH0004903 1 uF,6.3V ,Z ,Y5V ,TC ,1005 ,R/TP
6 C537 CAP,CERAMIC,CHIP ECCH0000122 47 pF,50V,J,NP0,TC,1005,R/TP
6 C538 CAP,CERAMIC,CHIP ECCH0000168 0.1 uF,16V,Z,Y5V,HD,1005,R/TP
6 C539 CAP,CERAMIC,CHIP ECCH0000168 0.1 uF,16V,Z,Y5V,HD,1005,R/TP
6 C541 CAP,CERAMIC,CHIP ECCH0000115 22 pF,50V,J,NP0,TC,1005,R/TP
6 C542 CAP,CERAMIC,CHIP ECCH0004903 1 uF,6.3V ,Z ,Y5V ,TC ,1005 ,R/TP
6 C543 CAP,CERAMIC,CHIP ECCH0000115 22 pF,50V,J,NP0,TC,1005,R/TP
6 C544 CAP,CERAMIC,CHIP ECCH0000168 0.1 uF,16V,Z,Y5V,HD,1005,R/TP
6 C545 CAP,CERAMIC,CHIP ECCH0004903 1 uF,6.3V ,Z ,Y5V ,TC ,1005 ,R/TP
6 C546 CAP,CERAMIC,CHIP ECCH0005705 10 uF,6.3V ,K ,X5R ,HD ,2012 ,R/TP
6 C547 CAP,CERAMIC,CHIP ECCH0004903 1 uF,6.3V ,Z ,Y5V ,TC ,1005 ,R/TP
6 C548 CAP,CERAMIC,CHIP ECCH0000110 10 pF,50V,D,NP0,TC,1005,R/TP
6 C549 CAP,CERAMIC,CHIP ECCH0000168 0.1 uF,16V,Z,Y5V,HD,1005,R/TP
6 C550 CAP,CERAMIC,CHIP ECCH0005705 10 uF,6.3V ,K ,X5R ,HD ,2012 ,R/TP
6 C551 CAP,CERAMIC,CHIP ECCH0005705 10 uF,6.3V ,K ,X5R ,HD ,2012 ,R/TP
6 C552 CAP,CERAMIC,CHIP ECCH0000139 470 pF,50V,K,X7R,HD,1005,R/TP
6 C553 CAP,CERAMIC,CHIP ECCH0000276 1 uF,10V,Z,Y5V,HD,1608,R/TP
6 C556 CAP,CERAMIC,CHIP ECCH0000143 1 nF,50V,K,X7R,HD,1005,R/TP
6 C557 CAP,CERAMIC,CHIP ECCH0000115 22 pF,50V,J,NP0,TC,1005,R/TP
- 262 - 10. EXPLODED VIEW & REPLACEMENT PART LIST
Location Level Description Part Number Specification Color Remark No.
6 C576 CAP,CERAMIC,CHIP ECCH0005801 2.2 uF,6.3V ,K ,X5R ,TC ,1608 ,R/TP
6 C588 CAP,CERAMIC,CHIP ECCH0005705 10 uF,6.3V ,K ,X5R ,HD ,2012 ,R/TP
6 C591 CAP,CERAMIC,CHIP ECCH0000168 0.1 uF,16V,Z,Y5V,HD,1005,R/TP
6 C595 CAP,CERAMIC,CHIP ECCH0005705 10 uF,6.3V ,K ,X5R ,HD ,2012 ,R/TP
6 C596 CAP,CERAMIC,CHIP ECCH0000168 0.1 uF,16V,Z,Y5V,HD,1005,R/TP
6 C597 CAP,CERAMIC,CHIP ECCH0000168 0.1 uF,16V,Z,Y5V,HD,1005,R/TP
6 C598 CAP,CERAMIC,CHIP ECCH0000139 470 pF,50V,K,X7R,HD,1005,R/TP
6 C599 CAP,CERAMIC,CHIP ECCH0000110 10 pF,50V,D,NP0,TC,1005,R/TP
6 C600 CAP,CERAMIC,CHIP ECCH0005705 10 uF,6.3V ,K ,X5R ,HD ,2012 ,R/TP
6 C640 CAP,CERAMIC,CHIP ECCH0005705 10 uF,6.3V ,K ,X5R ,HD ,2012 ,R/TP
6 C641 CAP,CERAMIC,CHIP ECCH0000168 0.1 uF,16V,Z,Y5V,HD,1005,R/TP
6 C642 CAP,CERAMIC,CHIP ECCH0000128 100 pF,50V,J,NP0,TC,1005,R/TP
6 C643 CAP,CERAMIC,CHIP ECCH0000128 100 pF,50V,J,NP0,TC,1005,R/TP
6 C645 CAP,CERAMIC,CHIP ECCH0000168 0.1 uF,16V,Z,Y5V,HD,1005,R/TP
6 C646 CAP,CERAMIC,CHIP ECCH0000168 0.1 uF,16V,Z,Y5V,HD,1005,R/TP
6 C647 CAP,CERAMIC,CHIP ECCH0000115 22 pF,50V,J,NP0,TC,1005,R/TP
6 C705 CAP,CERAMIC,CHIP ECCH0000114 20 pF,50V,J,NP0,TC,1005,R/TP
6 C706 CAP,CERAMIC,CHIP ECCH0000114 20 pF,50V,J,NP0,TC,1005,R/TP
6 C708 CAP,CERAMIC,CHIP ECCH0005801 2.2 uF,6.3V ,K ,X5R ,TC ,1608 ,R/TP
6 C709 CAP,CERAMIC,CHIP ECCH0005801 2.2 uF,6.3V ,K ,X5R ,TC ,1608 ,R/TP
6 C710 CAP,CERAMIC,CHIP ECCH0004903 1 uF,6.3V ,Z ,Y5V ,TC ,1005 ,R/TP
6 C711 CAP,CERAMIC,CHIP ECCH0005801 2.2 uF,6.3V ,K ,X5R ,TC ,1608 ,R/TP
6 C712 CAP,CERAMIC,CHIP ECCH0005801 2.2 uF,6.3V ,K ,X5R ,TC ,1608 ,R/TP
6 C713 CAP,CERAMIC,CHIP ECCH0004903 1 uF,6.3V ,Z ,Y5V ,TC ,1005 ,R/TP
6 C714 CAP,CERAMIC,CHIP ECCH0004903 1 uF,6.3V ,Z ,Y5V ,TC ,1005 ,R/TP
6 C715 CAP,CERAMIC,CHIP ECCH0004903 1 uF,6.3V ,Z ,Y5V ,TC ,1005 ,R/TP
6 C716 CAP,CERAMIC,CHIP ECCH0004903 1 uF,6.3V ,Z ,Y5V ,TC ,1005 ,R/TP
6 C717 CAP,CERAMIC,CHIP ECCH0000168 0.1 uF,16V,Z,Y5V,HD,1005,R/TP
6 C718 CAP,CERAMIC,CHIP ECCH0000168 0.1 uF,16V,Z,Y5V,HD,1005,R/TP
6 C719 CAP,CERAMIC,CHIP ECCH0000168 0.1 uF,16V,Z,Y5V,HD,1005,R/TP
6 C720 CAP,CERAMIC,CHIP ECCH0000168 0.1 uF,16V,Z,Y5V,HD,1005,R/TP
6 C721 CAP,CERAMIC,CHIP ECCH0000168 0.1 uF,16V,Z,Y5V,HD,1005,R/TP
6 C722 CAP,CERAMIC,CHIP ECCH0000168 0.1 uF,16V,Z,Y5V,HD,1005,R/TP
6 C723 CAP,CERAMIC,CHIP ECCH0000168 0.1 uF,16V,Z,Y5V,HD,1005,R/TP
- 263 - 10. EXPLODED VIEW & REPLACEMENT PART LIST
Location Level Description Part Number Specification Color Remark No.
6 C724 CAP,CERAMIC,CHIP ECCH0000168 0.1 uF,16V,Z,Y5V,HD,1005,R/TP
6 C725 CAP,CERAMIC,CHIP ECCH0000168 0.1 uF,16V,Z,Y5V,HD,1005,R/TP
6 C726 CAP,CERAMIC,CHIP ECCH0000122 47 pF,50V,J,NP0,TC,1005,R/TP
6 C727 CAP,CERAMIC,CHIP ECCH0000168 0.1 uF,16V,Z,Y5V,HD,1005,R/TP
6 C728 CAP,CERAMIC,CHIP ECCH0000168 0.1 uF,16V,Z,Y5V,HD,1005,R/TP
6 C729 CAP,CERAMIC,CHIP ECCH0000137 330 pF,50V ,K ,X7R ,HD ,1005 ,R/TP
6 C730 CAP,CERAMIC,CHIP ECCH0000168 0.1 uF,16V,Z,Y5V,HD,1005,R/TP
6 C731 CAP,CERAMIC,CHIP ECCH0000168 0.1 uF,16V,Z,Y5V,HD,1005,R/TP
6 C732 CAP,CERAMIC,CHIP ECCH0000168 0.1 uF,16V,Z,Y5V,HD,1005,R/TP
6 C733 CAP,CERAMIC,CHIP ECCH0000168 0.1 uF,16V,Z,Y5V,HD,1005,R/TP
6 C734 CAP,CERAMIC,CHIP ECCH0000168 0.1 uF,16V,Z,Y5V,HD,1005,R/TP
6 C735 CAP,CERAMIC,CHIP ECCH0000168 0.1 uF,16V,Z,Y5V,HD,1005,R/TP
6 C736 CAP,CERAMIC,CHIP ECCH0000168 0.1 uF,16V,Z,Y5V,HD,1005,R/TP
6 C737 CAP,CERAMIC,CHIP ECCH0000168 0.1 uF,16V,Z,Y5V,HD,1005,R/TP
6 C738 CAP,CERAMIC,CHIP ECCH0000168 0.1 uF,16V,Z,Y5V,HD,1005,R/TP
6 C740 CAP,TANTAL,CHIP,MAKER ECTZ0000318 33 uF,10V ,M ,STD ,3216 ,R/TP
6 C741 CAP,CERAMIC,CHIP ECCH0000168 0.1 uF,16V,Z,Y5V,HD,1005,R/TP
6 C742 CAP,CERAMIC,CHIP ECCH0000276 1 uF,10V,Z,Y5V,HD,1608,R/TP
6 C743 CAP,CERAMIC,CHIP ECCH0000155 10 nF,16V,K,X7R,HD,1005,R/TP
6 CN601 CONN,RF SWITCH ENWY0000401 STRAIGHT ,SMD ,0.1 dB,3*3*1.8 / 500 CYCLES
CONNECTOR,BOARD TO 6 CN701 ENBY0022501 50 PIN,0.4 mm,ETC , ,H=0.9, Socket BOARD
CONNECTOR,BOARD TO 6 CN702 ENBY0025501 26 PIN,0.4 mm,ETC , ,H=0.9, Socket BOARD
u181 BGA ,181 PIN,R/TP ,ASIC / WCDMA AIR INTERFACE 6 D701 IC EUSY0135201 / WANDA
6 D703 DIODE,SWITCHING EDSY0009901 ESC ,80 V,300 A,R/TP ,1.6*0.8*0.6(t)
6 FB501 FILTER,BEAD,CHIP SFBH0008901 30 ohm,2012 ,3000mA, BEAD for LARGE CURRENT
6 FB502 FILTER,BEAD,CHIP SFBH0008901 30 ohm,2012 ,3000mA, BEAD for LARGE CURRENT
6 FB503 FILTER,BEAD,CHIP SFBH0008901 30 ohm,2012 ,3000mA, BEAD for LARGE CURRENT
6 FB504 FILTER,BEAD,CHIP SFBH0008901 30 ohm,2012 ,3000mA, BEAD for LARGE CURRENT
6 FB505 FILTER,BEAD,CHIP SFBH0002302 120 ohm,1608 ,CHIP BEAD, 2000mA
, , dB, dB, dB, dB,ETC ,16 PIN / 4.2*3.5*1.4 / GSM-WCDMA 6 FL101 FILTER,SEPERATOR SFAY0004601 SP6T
6 FL201 FILTER,SAW SFSY0024402 2140 MHz,2.0*1.6*0.6 ,SMD ,6pin, Unbal-Bal, 50//200
6 FL301 FILTER,SAW SFSY0024401 1950 MHz,2.0*1.6*0.6 ,SMD ,6pin, Bal-Unbal, 200//50
6 FL401 FILTER,EMI/POWER SFEY0006501 SMD ,3 TERMINAL EMI FILTER
- 264 - 10. EXPLODED VIEW & REPLACEMENT PART LIST
Location Level Description Part Number Specification Color Remark No.
6 FL702 FILTER,EMI/POWER SFEY0006701 SMD ,CSP, 20 Ball 8ch EMI Filter /w ESD,Pb-free
SMD ,4ch(2.0*1.25), 200MHz, 1000Mohm, 10V, 100mA, 6 FL705 FILTER,EMI/POWER SFEY0007801 (29nH,47pF)
SMD ,4ch(2.0*1.25), 200MHz, 1000Mohm, 10V, 100mA, 6 FL706 FILTER,EMI/POWER SFEY0007801 (29nH,47pF)
6 L101 INDUCTOR,CHIP ELCH0005010 1.8 nH,S ,1005 ,R/TP ,
6 L102 INDUCTOR,CHIP ELCH0001030 8.2 nH,J ,1005 ,R/TP ,PB-FREE
6 L103 FILTER,BEAD,CHIP SFBH0007103 75 ohm,1005 ,CHIP BEAD, 300mA
6 L104 FILTER,BEAD,CHIP SFBH0007103 75 ohm,1005 ,CHIP BEAD, 300mA
6 L105 FILTER,BEAD,CHIP SFBH0007103 75 ohm,1005 ,CHIP BEAD, 300mA
6 L201 INDUCTOR,CHIP ELCH0001425 82 nH,J ,1005 ,R/TP ,PBFREE
6 L202 INDUCTOR,CHIP ELCH0001425 82 nH,J ,1005 ,R/TP ,PBFREE
6 L203 INDUCTOR,CHIP ELCH0001407 5.6 nH,S ,1005 ,R/TP ,PBFREE
6 L204 INDUCTOR,CHIP ELCH0005001 2.2 nH,S ,1005 ,R/TP ,
6 L207 INDUCTOR,CHIP ELCH0001511 100 nH,J ,1608 ,R/TP ,PBFREE
6 L208 INDUCTOR,CHIP ELCH0003811 1000 nH,K ,1608 ,R/TP ,COIL TYPE
6 L305 FILTER,BEAD,CHIP SFBH0007103 75 ohm,1005 ,CHIP BEAD, 300mA
6 L307 INDUCTOR,CHIP ELCH0001407 5.6 nH,S ,1005 ,R/TP ,PBFREE
6 L308 INDUCTOR,CHIP ELCH0001001 10 nH,J ,1005 ,R/TP ,Pb Free
6 L309 INDUCTOR,CHIP ELCH0001407 5.6 nH,S ,1005 ,R/TP ,PBFREE
6 L310 INDUCTOR,CHIP ELCH0001401 15 nH,J ,1005 ,R/TP ,Pb Free
6 L311 INDUCTOR,CHIP ELCH0001401 15 nH,J ,1005 ,R/TP ,Pb Free
6 L401 FILTER,BEAD,CHIP SFBH0008101 600 ohm,1005 ,
6 L402 FILTER,BEAD,CHIP SFBH0007103 75 ohm,1005 ,CHIP BEAD, 300mA
6 L501 FILTER,BEAD,CHIP SFBH0007103 75 ohm,1005 ,CHIP BEAD, 300mA
6 L502 FILTER,BEAD,CHIP SFBH0007103 75 ohm,1005 ,CHIP BEAD, 300mA
6 L503 INDUCTOR,SMD,POWER ELCP0009402 22 uH,M ,2.8*2.6*1.0 ,R/TP ,power inductor
6 L601 INDUCTOR,CHIP ELCH0005005 27 nH,J ,1005 ,R/TP ,
6 L602 CAP,CERAMIC,CHIP ECCH0000186 33 pF,50V ,J ,NP0 ,TC ,1005 ,R/TP
SOT323-6L ,6 PIN,R/TP ,EMI FILTER & LINE 6 L701 IC EUSY0163501 TERMINATION for USB
6 L702 FILTER,BEAD,CHIP SFBH0002302 120 ohm,1608 ,CHIP BEAD, 2000mA
6 N101 IC EUSY0122502 LLP-6 ,6 PIN,R/TP ,300mA CMOS LDO / 2.8V, Pb-free
6 N201 IC EUSY0133001 uBGA ,56 PIN,R/TP ,U8000 RF IC
6 N304 IC EUSY0132901 56 ,56 PIN,R/TP ,WCDMA TXIC Wivi
dBm, %, mA, dBc, dB,6*6*1.25 ,SMD ,PAM for TRI- 6 N401 PAM SMPY0007101 BAND(EGSM/GPRS)
- 265 - 10. EXPLODED VIEW & REPLACEMENT PART LIST
Location Level Description Part Number Specification Color Remark No.
u143 BGA ,143 PIN,R/TP ,ASIC / POWER MANAGEMENT 6 N503 IC EUSY0132701 IC / VINCENNE
6 N702 IC EUSY0153001 SOT23-5 ,5 PIN,R/TP ,150 mA LDO REGULATOR / 1.5V
6 PT501 THERMISTOR SETY0005701 NTC ,47000 ohm,SMD ,F, Pb Free
POWERPAK 1212-8 ,0.8 W,20 V,5.4 A,R/TP ,P-CHANNEL 6 Q501 TR,FET,P-CHANNEL EQFP0005601 20V (D-S) MOSFET
SOT-363 ,.27 W,20 V,.66 A,R/TP ,Dual(P- 6 Q502 TR,FET,P-CHANNEL EQFP0003601 channel:PD=0.27W,VDS=-8V,ID=0.57, Pb free
6 Q702 TR,BJT,NPN EQBN0014901 SOT323 ,.2 W,R/TP ,NPN SWITCHING TR, Pb free
6 Q703 TR,BJT,PNP EQBP0003001 UMT6 ,.15 W,R/TP ,
6 R101 RES,CHIP ERHY0000201 0 ohm,1/16W,J,1005,R/TP
6 R102 RES,CHIP ERHY0000201 0 ohm,1/16W,J,1005,R/TP
6 R103 RES,CHIP ERHY0000201 0 ohm,1/16W,J,1005,R/TP
6 R104 RES,CHIP ERHY0000201 0 ohm,1/16W,J,1005,R/TP
6 R105 RES,CHIP ERHY0000201 0 ohm,1/16W,J,1005,R/TP
6 R106 RES,CHIP ERHY0000201 0 ohm,1/16W,J,1005,R/TP
6 R201 RES,CHIP ERHY0000201 0 ohm,1/16W,J,1005,R/TP
6 R202 RES,CHIP ERHY0000250 3.3K ohm,1/16W,J,1005,R/TP
6 R203 FILTER,BEAD,CHIP SFBH0007103 75 ohm,1005 ,CHIP BEAD, 300mA
6 R204 FILTER,BEAD,CHIP SFBH0007103 75 ohm,1005 ,CHIP BEAD, 300mA
6 R205 RES,CHIP ERHY0000201 0 ohm,1/16W,J,1005,R/TP
6 R206 RES,CHIP ERHY0000255 5.6K ohm,1/16W,J,1005,R/TP
6 R207 RES,CHIP ERHY0000201 0 ohm,1/16W,J,1005,R/TP
6 R208 RES,CHIP ERHY0000220 100 ohm,1/16W,J,1005,R/TP
6 R209 RES,CHIP ERHY0000201 0 ohm,1/16W,J,1005,R/TP
6 R210 RES,CHIP ERHY0000201 0 ohm,1/16W,J,1005,R/TP
6 R212 RES,CHIP ERHY0000241 1K ohm,1/16W,J,1005,R/TP
6 R2126 RES,CHIP ERHY0000201 0 ohm,1/16W,J,1005,R/TP
6 R2127 RES,CHIP ERHY0000280 100K ohm,1/16W,J,1005,R/TP
6 R2129 RES,CHIP ERHY0000280 100K ohm,1/16W,J,1005,R/TP
6 R2132 RES,CHIP ERHY0000280 100K ohm,1/16W,J,1005,R/TP
6 R2135 RES,CHIP ERHY0000160 180K ohm,1/16W,F,1005,R/TP
6 R2138 RES,CHIP ERHY0000280 100K ohm,1/16W,J,1005,R/TP
6 R215 RES,CHIP ERHY0000203 10 ohm,1/16W,J,1005,R/TP
6 R2150 RES,CHIP ERHY0000714 .51 ohm,1/4W ,J ,2012 ,R/TP
6 R216 RES,CHIP ERHY0000261 10K ohm,1/16W,J,1005,R/TP
- 266 - 10. EXPLODED VIEW & REPLACEMENT PART LIST
Location Level Description Part Number Specification Color Remark No.
6 R217 RES,CHIP ERHY0000261 10K ohm,1/16W,J,1005,R/TP
6 R2171 RES,CHIP ERHY0000201 0 ohm,1/16W,J,1005,R/TP
6 R2179 FILTER,BEAD,CHIP SFBH0007103 75 ohm,1005 ,CHIP BEAD, 300mA
6 R2186 FILTER,BEAD,CHIP SFBH0007103 75 ohm,1005 ,CHIP BEAD, 300mA
6 R2191 RES,CHIP ERHY0000201 0 ohm,1/16W,J,1005,R/TP
6 R2192 RES,CHIP ERHY0000280 100K ohm,1/16W,J,1005,R/TP
6 R2194 RES,CHIP ERHY0000201 0 ohm,1/16W,J,1005,R/TP
6 R2196 RES,CHIP ERHY0000226 220 ohm,1/16W,J,1005,R/TP
6 R2197 RES,CHIP ERHY0000201 0 ohm,1/16W,J,1005,R/TP
6 R220 RES,CHIP ERHY0000203 10 ohm,1/16W,J,1005,R/TP
6 R2205 RES,CHIP ERHY0000201 0 ohm,1/16W,J,1005,R/TP
6 R221 RES,CHIP ERHY0000203 10 ohm,1/16W,J,1005,R/TP
6 R2225 RES,CHIP ERHY0008701 0.22 ohm,1/4W ,J ,2012 ,R/TP
6 R2236 RES,CHIP ERHY0000201 0 ohm,1/16W,J,1005,R/TP
6 R2237 RES,CHIP ERHY0000201 0 ohm,1/16W,J,1005,R/TP
6 R2238 RES,CHIP ERHY0000201 0 ohm,1/16W,J,1005,R/TP
6 R2239 RES,CHIP ERHY0000261 10K ohm,1/16W,J,1005,R/TP
6 R2251 RES,CHIP ERHY0000201 0 ohm,1/16W,J,1005,R/TP
6 R309 RES,CHIP ERHY0000203 10 ohm,1/16W,J,1005,R/TP
6 R310 RES,CHIP ERHY0000201 0 ohm,1/16W,J,1005,R/TP
6 R311 RES,CHIP ERHY0000201 0 ohm,1/16W,J,1005,R/TP
6 R312 RES,CHIP ERHY0000201 0 ohm,1/16W,J,1005,R/TP
6 R313 RES,CHIP ERHY0000201 0 ohm,1/16W,J,1005,R/TP
6 R314 RES,CHIP ERHY0000111 680 ohm,1/16W,F,1005,R/TP
6 R315 RES,CHIP ERHY0000111 680 ohm,1/16W,F,1005,R/TP
6 R316 RES,CHIP ERHY0000201 0 ohm,1/16W,J,1005,R/TP
6 R317 RES,CHIP ERHY0000201 0 ohm,1/16W,J,1005,R/TP
6 R318 RES,CHIP ERHY0000254 4.7K ohm,1/16W,J,1005,R/TP
6 R319 RES,CHIP ERHY0000201 0 ohm,1/16W,J,1005,R/TP
6 R320 RES,CHIP ERHY0000203 10 ohm,1/16W,J,1005,R/TP
6 R401 RES,CHIP ERHY0000241 1K ohm,1/16W,J,1005,R/TP
6 R402 RES,CHIP,MAKER ERHZ0000459 3 Kohm,1/16W ,J ,1005 ,R/TP
6 R403 RES,CHIP ERHY0000201 0 ohm,1/16W,J,1005,R/TP
6 R407 RES,CHIP ERHY0008601 0.05 ohm,1/4W ,J ,2012 ,R/TP
- 267 - 10. EXPLODED VIEW & REPLACEMENT PART LIST
Location Level Description Part Number Specification Color Remark No.
6 R408 RES,CHIP ERHY0000201 0 ohm,1/16W,J,1005,R/TP
6 R413 RES,CHIP ERHY0000201 0 ohm,1/16W,J,1005,R/TP
6 R503 RES,CHIP ERHY0000201 0 ohm,1/16W,J,1005,R/TP
6 R504 RES,CHIP ERHY0000280 100K ohm,1/16W,J,1005,R/TP
6 R505 RES,CHIP ERHY0000201 0 ohm,1/16W,J,1005,R/TP
6 R506 RES,CHIP ERHY0000201 0 ohm,1/16W,J,1005,R/TP
6 R510 RES,CHIP ERHY0000201 0 ohm,1/16W,J,1005,R/TP
6 R511 RES,CHIP ERHY0000201 0 ohm,1/16W,J,1005,R/TP
6 R512 RES,CHIP ERHY0000201 0 ohm,1/16W,J,1005,R/TP
6 R516 RES,CHIP ERHY0000220 100 ohm,1/16W,J,1005,R/TP
6 R517 RES,CHIP ERHY0000201 0 ohm,1/16W,J,1005,R/TP
6 R518 RES,CHIP ERHY0000201 0 ohm,1/16W,J,1005,R/TP
6 R519 RES,CHIP ERHY0000201 0 ohm,1/16W,J,1005,R/TP
6 R520 RES,CHIP ERHY0000220 100 ohm,1/16W,J,1005,R/TP
6 R521 RES,CHIP ERHY0000266 22K ohm,1/16W,J,1005,R/TP
6 R522 RES,CHIP ERHY0000201 0 ohm,1/16W,J,1005,R/TP
6 R523 RES,CHIP ERHY0000241 1K ohm,1/16W,J,1005,R/TP
6 R526 RES,CHIP ERHY0000201 0 ohm,1/16W,J,1005,R/TP
6 R527 RES,CHIP ERHY0000201 0 ohm,1/16W,J,1005,R/TP
6 R528 RES,CHIP ERHY0000280 100K ohm,1/16W,J,1005,R/TP
6 R535 RES,CHIP ERHY0000241 1K ohm,1/16W,J,1005,R/TP
6 R536 RES,CHIP ERHY0000201 0 ohm,1/16W,J,1005,R/TP
6 R538 RES,CHIP ERHY0000280 100K ohm,1/16W,J,1005,R/TP
6 R540 RES,CHIP ERHY0000201 0 ohm,1/16W,J,1005,R/TP
6 R541 RES,CHIP ERHY0000201 0 ohm,1/16W,J,1005,R/TP
6 R542 RES,CHIP ERHY0000263 15K ohm,1/16W,J,1005,R/TP
6 R543 RES,CHIP ERHY0000213 47 ohm,1/16W,J,1005,R/TP
6 R544 RES,CHIP ERHY0000201 0 ohm,1/16W,J,1005,R/TP
6 R545 RES,CHIP ERHY0000201 0 ohm,1/16W,J,1005,R/TP
6 R546 RES,CHIP ERHY0000261 10K ohm,1/16W,J,1005,R/TP
6 R547 RES,CHIP ERHY0000280 100K ohm,1/16W,J,1005,R/TP
6 R548 RES,CHIP ERHY0000202 4.7 ohm,1/16W,J,1005,R/TP
6 R549 RES,CHIP ERHY0000280 100K ohm,1/16W,J,1005,R/TP
6 R550 RES,CHIP ERHY0000280 100K ohm,1/16W,J,1005,R/TP
- 268 - 10. EXPLODED VIEW & REPLACEMENT PART LIST
Location Level Description Part Number Specification Color Remark No.
6 R551 RES,CHIP ERHY0000201 0 ohm,1/16W,J,1005,R/TP
6 R552 RES,CHIP ERHY0000280 100K ohm,1/16W,J,1005,R/TP
6 R553 RES,CHIP ERHY0000201 0 ohm,1/16W,J,1005,R/TP
6 R554 RES,CHIP ERHY0000201 0 ohm,1/16W,J,1005,R/TP
6 R555 RES,CHIP ERHY0000201 0 ohm,1/16W,J,1005,R/TP
6 R556 RES,CHIP ERHY0000201 0 ohm,1/16W,J,1005,R/TP
6 R557 RES,CHIP ERHY0000280 100K ohm,1/16W,J,1005,R/TP
6 R558 RES,CHIP ERHY0000201 0 ohm,1/16W,J,1005,R/TP
6 R559 RES,CHIP ERHY0000266 22K ohm,1/16W,J,1005,R/TP
6 R560 RES,CHIP ERHY0000201 0 ohm,1/16W,J,1005,R/TP
6 R561 RES,CHIP ERHY0000201 0 ohm,1/16W,J,1005,R/TP
6 R562 RES,CHIP ERHY0000280 100K ohm,1/16W,J,1005,R/TP
6 R563 RES,CHIP ERHY0000201 0 ohm,1/16W,J,1005,R/TP
6 R564 RES,CHIP ERHY0000401 0 ohm,1/16W,J,1608,R/TP
6 R565 RES,CHIP,MAKER ERHZ0000319 8200 ohm,1/16W ,F ,1005 ,R/TP
6 R570 RES,CHIP ERHY0000201 0 ohm,1/16W,J,1005,R/TP
6 R593 RES,CHIP ERHY0008701 0.22 ohm,1/4W ,J ,2012 ,R/TP
6 R599 RES,CHIP ERHY0000201 0 ohm,1/16W,J,1005,R/TP
6 R600 RES,CHIP ERHY0000201 0 ohm,1/16W,J,1005,R/TP
6 R648 RES,CHIP ERHY0001302 1 ohm,1/8W,J,2012,R/TP
6 R650 RES,CHIP ERHY0000266 22K ohm,1/16W,J,1005,R/TP
6 R651 RES,CHIP ERHY0000201 0 ohm,1/16W,J,1005,R/TP
6 R652 RES,CHIP ERHY0000282 120K ohm,1/16W,J,1005,R/TP
6 R656 CAP,CERAMIC,CHIP ECCH0000186 33 pF,50V ,J ,NP0 ,TC ,1005 ,R/TP
6 R701 RES,CHIP ERHY0000201 0 ohm,1/16W,J,1005,R/TP
6 R702 RES,CHIP ERHY0000201 0 ohm,1/16W,J,1005,R/TP
6 R704 RES,CHIP ERHY0000201 0 ohm,1/16W,J,1005,R/TP
6 R706 RES,CHIP ERHY0000201 0 ohm,1/16W,J,1005,R/TP
6 R708 RES,CHIP ERHY0000201 0 ohm,1/16W,J,1005,R/TP
6 R714 RES,CHIP ERHY0000201 0 ohm,1/16W,J,1005,R/TP
6 R715 RES,CHIP ERHY0000201 0 ohm,1/16W,J,1005,R/TP
6 R716 RES,CHIP ERHY0000214 51 ohm,1/16W,J,1005,R/TP
6 R717 RES,CHIP ERHY0000201 0 ohm,1/16W,J,1005,R/TP
6 R718 RES,CHIP ERHY0000214 51 ohm,1/16W,J,1005,R/TP
- 269 - 10. EXPLODED VIEW & REPLACEMENT PART LIST
Location Level Description Part Number Specification Color Remark No.
6 R721 RES,CHIP ERHY0000201 0 ohm,1/16W,J,1005,R/TP
6 R724 RES,CHIP ERHY0000261 10K ohm,1/16W,J,1005,R/TP
6 R725 RES,CHIP ERHY0000201 0 ohm,1/16W,J,1005,R/TP
6 R726 RES,CHIP ERHY0000201 0 ohm,1/16W,J,1005,R/TP
6 R730 RES,CHIP ERHY0000261 10K ohm,1/16W,J,1005,R/TP
6 R731 RES,CHIP ERHY0000201 0 ohm,1/16W,J,1005,R/TP
6 R732 RES,CHIP ERHY0000201 0 ohm,1/16W,J,1005,R/TP
6 R733 RES,CHIP ERHY0000201 0 ohm,1/16W,J,1005,R/TP
6 R735 RES,CHIP ERHY0000262 12K ohm,1/16W,J,1005,R/TP
6 R736 RES,CHIP,MAKER ERHZ0000459 3 Kohm,1/16W ,J ,1005 ,R/TP
6 R737 RES,CHIP ERHY0000201 0 ohm,1/16W,J,1005,R/TP
6 R738 RES,CHIP ERHY0000201 0 ohm,1/16W,J,1005,R/TP
6 R739 RES,CHIP ERHY0000201 0 ohm,1/16W,J,1005,R/TP
6 R740 RES,CHIP ERHY0000201 0 ohm,1/16W,J,1005,R/TP
6 R744 RES,CHIP ERHY0000250 3.3K ohm,1/16W,J,1005,R/TP
6 R745 RES,CHIP ERHY0000249 2.7K ohm,1/16W,J,1005,R/TP
6 R747 RES,CHIP ERHY0000143 43K ohm,1/16W,F,1005,R/TP
6 R748 RES,CHIP ERHY0000280 100K ohm,1/16W,J,1005,R/TP
6 R749 RES,CHIP ERHY0000280 100K ohm,1/16W,J,1005,R/TP
6 R752 RES,CHIP ERHY0000201 0 ohm,1/16W,J,1005,R/TP
6 R753 RES,CHIP ERHY0000201 0 ohm,1/16W,J,1005,R/TP
6 R754 RES,CHIP ERHY0000201 0 ohm,1/16W,J,1005,R/TP
6 R755 RES,CHIP ERHY0000280 100K ohm,1/16W,J,1005,R/TP
6 R756 RES,CHIP ERHY0000201 0 ohm,1/16W,J,1005,R/TP
6 R757 RES,CHIP ERHY0000280 100K ohm,1/16W,J,1005,R/TP
6 R758 RES,CHIP ERHY0000201 0 ohm,1/16W,J,1005,R/TP
6 R843 RES,CHIP ERHY0000280 100K ohm,1/16W,J,1005,R/TP
6 R847 RES,CHIP ERHY0008601 0.05 ohm,1/4W ,J ,2012 ,R/TP
6 R875 RES,CHIP ERHY0008601 0.05 ohm,1/4W ,J ,2012 ,R/TP
6 R878 RES,CHIP ERHY0000280 100K ohm,1/16W,J,1005,R/TP
6 R899 RES,CHIP ERHY0008602 0.1 ohm,1/4W ,J ,2012 ,R/TP
6 U501 IC EUSY0232802 sot 23-5 ,5 PIN,R/TP ,2.8V,150mA LDO
6 U503 IC EUSY0232802 sot 23-5 ,5 PIN,R/TP ,2.8V,150mA LDO
6 U506 IC EUSY0275401 SOT23-5 ,5 PIN,R/TP ,150mA, 2.4V, 80dB, LDO, PBFREE
- 270 - 10. EXPLODED VIEW & REPLACEMENT PART LIST
Location Level Description Part Number Specification Color Remark No.
6 U510 IC EUSY0232815 SOT23-5 ,5 PIN,R/TP ,2.85V,300mA,LDO,PBFREE
HVQFN ,52 PIN,R/TP ,BLUETOOTH RADIO MODULE 6 U604 IC EUSY0212002 WITH BASEBAND CONTROLLER_Pb free
6 U701 IC EUSY0188103 QFN ,24 PIN,R/TP ,MAIN+FLASH UPTO400mAcontinuous
6 V201 DIODE,VARIABLE CAP EDVY0001801 SCD80 ,0.09 pF,R/TP ,
6 V501 DIODE,TVS EDTY0007001 SOT23-6 ,9 V, W,R/TP ,TVS DIODE ARRAY
EMD2 ,30 V,1 A,R/TP ,VF=1.5V(IF=200mA) , 6 V502 DIODE,SWITCHING EDSY0011901 IR=30uA(VR=10V)
EMD2 ,30 V,1 A,R/TP ,VF=1.5V(IF=200mA) , 6 V503 DIODE,SWITCHING EDSY0011901 IR=30uA(VR=10V)
6 V701 DIODE,TVS EDTY0006401 SC70-6L ,5 V,100 W,R/TP ,PB-FREE
6 W101 CONN,RF SWITCH ENWY0003301 ,SMD ,0.4 dB,
8 PIN,ETC ,SMD ,2.54 mm,2.2T UIM CONNECTOR WITH 6 X502 CONN,SOCKET ENSY0009901 BRIDGE
6 X701 CONN,RECEPTACLE ENEY0004101 24 PIN,3 , ,25.3*10*(3+1.5)T
6 Z201 FILTER,SAW SFSY0012502 190 MHz,3.8*3.8*1.2 ,SMD ,6pin, Bal-Bal, 1000//1000
5 SAFD00 PCB ASSY,MAIN,SMT TOP SAFD0064901
6 B301 IC EUSY0067201 MAA05A ,5 PIN,R/TP ,2.4V,10uA, TEMP SENSOR(Pb Free)
.032768 MHz,20 PPM,12.5 pF,65000 ohm,SMD 6 B601 X-TAL EXXY0004602 ,6.9*1.4*1.3 ,
6 C111 CAP,CERAMIC,CHIP ECCH0000115 22 pF,50V,J,NP0,TC,1005,R/TP
6 C115 CAP,CERAMIC,CHIP ECCH0005705 10 uF,6.3V ,K ,X5R ,HD ,2012 ,R/TP
6 C116 CAP,CERAMIC,CHIP ECCH0005705 10 uF,6.3V ,K ,X5R ,HD ,2012 ,R/TP
6 C1930 CAP,CERAMIC,CHIP ECCH0000110 10 pF,50V,D,NP0,TC,1005,R/TP
6 C1931 CAP,CERAMIC,CHIP ECCH0000110 10 pF,50V,D,NP0,TC,1005,R/TP
6 C1932 CAP,CERAMIC,CHIP ECCH0000110 10 pF,50V,D,NP0,TC,1005,R/TP
6 C1933 CAP,CERAMIC,CHIP ECCH0000110 10 pF,50V,D,NP0,TC,1005,R/TP
6 C301 CAP,CERAMIC,CHIP ECCH0000137 330 pF,50V ,K ,X7R ,HD ,1005 ,R/TP
6 C302 CAP,CERAMIC,CHIP ECCH0000115 22 pF,50V,J,NP0,TC,1005,R/TP
6 C303 CAP,CERAMIC,CHIP ECCH0005705 10 uF,6.3V ,K ,X5R ,HD ,2012 ,R/TP
6 C304 CAP,CERAMIC,CHIP ECCH0005705 10 uF,6.3V ,K ,X5R ,HD ,2012 ,R/TP
6 C305 CAP,CERAMIC,CHIP ECCH0005705 10 uF,6.3V ,K ,X5R ,HD ,2012 ,R/TP
6 C306 CAP,CERAMIC,CHIP ECCH0000143 1 nF,50V,K,X7R,HD,1005,R/TP
6 C307 CAP,CERAMIC,CHIP ECCH0000186 33 pF,50V ,J ,NP0 ,TC ,1005 ,R/TP
6 C308 CAP,CERAMIC,CHIP ECCH0000155 10 nF,16V,K,X7R,HD,1005,R/TP
6 C309 CAP,CERAMIC,CHIP ECCH0000115 22 pF,50V,J,NP0,TC,1005,R/TP
- 271 - 10. EXPLODED VIEW & REPLACEMENT PART LIST
Location Level Description Part Number Specification Color Remark No.
6 C310 CAP,CERAMIC,CHIP ECCH0000167 0.1 uF,6.3V,K,X5R,HD,1005,R/TP
6 C311 CAP,CERAMIC,CHIP ECCH0000110 10 pF,50V,D,NP0,TC,1005,R/TP
6 C312 CAP,CERAMIC,CHIP ECCH0000115 22 pF,50V,J,NP0,TC,1005,R/TP
6 C413 CAP,CERAMIC,CHIP ECCH0000165 68 nF,6.3V,K,X5R,HD,1005,R/TP
6 C414 CAP,CERAMIC,CHIP ECCH0000155 10 nF,16V,K,X7R,HD,1005,R/TP
6 C415 CAP,CERAMIC,CHIP ECCH0000165 68 nF,6.3V,K,X5R,HD,1005,R/TP
6 C416 CAP,CERAMIC,CHIP ECCH0000165 68 nF,6.3V,K,X5R,HD,1005,R/TP
6 C417 CAP,CERAMIC,CHIP ECCH0000165 68 nF,6.3V,K,X5R,HD,1005,R/TP
6 C418 CAP,CERAMIC,CHIP ECCH0000165 68 nF,6.3V,K,X5R,HD,1005,R/TP
6 C419 CAP,CERAMIC,CHIP ECCH0000155 10 nF,16V,K,X7R,HD,1005,R/TP
6 C425 CAP,CERAMIC,CHIP ECCH0000115 22 pF,50V,J,NP0,TC,1005,R/TP
6 C426 CAP,CERAMIC,CHIP ECCH0000115 22 pF,50V,J,NP0,TC,1005,R/TP
6 C427 CAP,CERAMIC,CHIP ECCH0000115 22 pF,50V,J,NP0,TC,1005,R/TP
6 C428 CAP,CERAMIC,CHIP ECCH0000111 12 pF,50V,J,NP0,TC,1005,R/TP
6 C429 CAP,CERAMIC,CHIP ECCH0000186 33 pF,50V ,J ,NP0 ,TC ,1005 ,R/TP
6 C430 CAP,CERAMIC,CHIP ECCH0000901 2.2 pF,50V ,C ,NP0 ,TC ,1005 ,R/TP
6 C431 CAP,CERAMIC,CHIP ECCH0000186 33 pF,50V ,J ,NP0 ,TC ,1005 ,R/TP
6 C432 CAP,CERAMIC,CHIP ECCH0000901 2.2 pF,50V ,C ,NP0 ,TC ,1005 ,R/TP
6 C433 CAP,CERAMIC,CHIP ECCH0000115 22 pF,50V,J,NP0,TC,1005,R/TP
6 C434 CAP,CERAMIC,CHIP ECCH0000110 10 pF,50V,D,NP0,TC,1005,R/TP
6 C435 CAP,CERAMIC,CHIP ECCH0000175 2.7 pF,50V ,B ,NP0 ,TC ,1005 ,R/TP
6 C436 CAP,CERAMIC,CHIP ECCH0000175 2.7 pF,50V ,B ,NP0 ,TC ,1005 ,R/TP
6 C437 INDUCTOR,CHIP ELCH0001033 1.5 nH,S ,1005 ,R/TP ,PBFREE
6 C438 CAP,CERAMIC,CHIP ECCH0000110 10 pF,50V,D,NP0,TC,1005,R/TP
6 C439 CAP,CERAMIC,CHIP ECCH0000155 10 nF,16V,K,X7R,HD,1005,R/TP
6 C440 CAP,CERAMIC,CHIP ECCH0000115 22 pF,50V,J,NP0,TC,1005,R/TP
6 C441 CAP,CERAMIC,CHIP ECCH0000143 1 nF,50V,K,X7R,HD,1005,R/TP
6 C442 CAP,CERAMIC,CHIP ECCH0000143 1 nF,50V,K,X7R,HD,1005,R/TP
6 C443 CAP,CERAMIC,CHIP ECCH0000155 10 nF,16V,K,X7R,HD,1005,R/TP
6 C444 CAP,CERAMIC,CHIP ECCH0000146 1.8 nF,50V,K,X7R,HD,1005,R/TP
6 C445 CAP,CERAMIC,CHIP ECCH0000144 1.2 nF,50V,K,X7R,HD,1005,R/TP
6 C447 CAP,CERAMIC,CHIP ECCH0000140 560 pF,50V,K,X7R,HD,1005,R/TP
6 C448 CAP,CERAMIC,CHIP ECCH0000137 330 pF,50V ,K ,X7R ,HD ,1005 ,R/TP
6 C449 CAP,CERAMIC,CHIP ECCH0000155 10 nF,16V,K,X7R,HD,1005,R/TP
- 272 - 10. EXPLODED VIEW & REPLACEMENT PART LIST
Location Level Description Part Number Specification Color Remark No.
6 C450 CAP,CERAMIC,CHIP ECCH0000115 22 pF,50V,J,NP0,TC,1005,R/TP
6 C451 CAP,CERAMIC,CHIP ECCH0000115 22 pF,50V,J,NP0,TC,1005,R/TP
6 C452 CAP,CERAMIC,CHIP ECCH0000155 10 nF,16V,K,X7R,HD,1005,R/TP
6 C453 CAP,CERAMIC,CHIP ECCH0000186 33 pF,50V ,J ,NP0 ,TC ,1005 ,R/TP
6 C454 CAP,CERAMIC,CHIP ECCH0000186 33 pF,50V ,J ,NP0 ,TC ,1005 ,R/TP
6 C501 CAP,TANTAL,CHIP ECTH0002702 1 uF,16V ,M ,STD ,1608 ,R/TP
6 C502 CAP,TANTAL,CHIP ECTH0002702 1 uF,16V ,M ,STD ,1608 ,R/TP
6 C503 CAP,CERAMIC,CHIP ECCH0000279 0.47 uF,10V ,Z ,Y5V ,HD ,1608 ,R/TP
6 C504 CAP,CERAMIC,CHIP ECCH0005801 2.2 uF,6.3V ,K ,X5R ,TC ,1608 ,R/TP
6 C508 CAP,CERAMIC,CHIP ECCH0006201 4.7 uF,6.3V ,K ,X5R ,TC ,1608 ,R/TP
6 C509 CAP,CERAMIC,CHIP ECCH0000128 100 pF,50V,J,NP0,TC,1005,R/TP
6 C510 CAP,CERAMIC,CHIP ECCH0005801 2.2 uF,6.3V ,K ,X5R ,TC ,1608 ,R/TP
6 C511 CAP,CERAMIC,CHIP ECCH0000155 10 nF,16V,K,X7R,HD,1005,R/TP
6 C512 CAP,CERAMIC,CHIP ECCH0000276 1 uF,10V,Z,Y5V,HD,1608,R/TP
6 C513 CAP,CHIP,MAKER ECZH0003501 1 uF,6.3V ,K ,X5R ,HD ,1608 ,R/TP
6 C517 CAP,CERAMIC,CHIP ECCH0004903 1 uF,6.3V ,Z ,Y5V ,TC ,1005 ,R/TP
6 C519 CAP,CERAMIC,CHIP ECCH0004903 1 uF,6.3V ,Z ,Y5V ,TC ,1005 ,R/TP
6 C524 CAP,CERAMIC,CHIP ECCH0002003 33 nF,16V ,K ,B ,TC ,1005 ,R/TP
6 C525 CAP,CERAMIC,CHIP ECCH0000126 68 pF,50V,J,NP0,TC,1005,R/TP
6 C526 CAP,CERAMIC,CHIP ECCH0002003 33 nF,16V ,K ,B ,TC ,1005 ,R/TP
6 C528 CAP,CERAMIC,CHIP ECCH0002003 33 nF,16V ,K ,B ,TC ,1005 ,R/TP
6 C529 CAP,CERAMIC,CHIP ECCH0000126 68 pF,50V,J,NP0,TC,1005,R/TP
6 C554 CAP,CERAMIC,CHIP ECCH0004903 1 uF,6.3V ,Z ,Y5V ,TC ,1005 ,R/TP
6 C555 CAP,CERAMIC,CHIP ECCH0000110 10 pF,50V,D,NP0,TC,1005,R/TP
6 C558 CAP,CERAMIC,CHIP ECCH0000122 47 pF,50V,J,NP0,TC,1005,R/TP
6 C559 CAP,CERAMIC,CHIP ECCH0000122 47 pF,50V,J,NP0,TC,1005,R/TP
6 C560 CAP,CERAMIC,CHIP ECCH0002003 33 nF,16V ,K ,B ,TC ,1005 ,R/TP
6 C561 CAP,CERAMIC,CHIP ECCH0000168 0.1 uF,16V,Z,Y5V,HD,1005,R/TP
6 C562 CAP,CERAMIC,CHIP ECCH0004903 1 uF,6.3V ,Z ,Y5V ,TC ,1005 ,R/TP
6 C563 CAP,CERAMIC,CHIP ECCH0005705 10 uF,6.3V ,K ,X5R ,HD ,2012 ,R/TP
6 C564 CAP,CERAMIC,CHIP ECCH0005705 10 uF,6.3V ,K ,X5R ,HD ,2012 ,R/TP
6 C566 CAP,CERAMIC,CHIP ECCH0000115 22 pF,50V,J,NP0,TC,1005,R/TP
6 C567 CAP,CERAMIC,CHIP ECCH0000165 68 nF,6.3V,K,X5R,HD,1005,R/TP
6 C568 CAP,CERAMIC,CHIP ECCH0000165 68 nF,6.3V,K,X5R,HD,1005,R/TP
- 273 - 10. EXPLODED VIEW & REPLACEMENT PART LIST
Location Level Description Part Number Specification Color Remark No.
6 C570 CAP,CERAMIC,CHIP ECCH0000126 68 pF,50V,J,NP0,TC,1005,R/TP
6 C571 CAP,CERAMIC,CHIP ECCH0000126 68 pF,50V,J,NP0,TC,1005,R/TP
6 C572 CAP,TANTAL,CHIP ECTH0002702 1 uF,16V ,M ,STD ,1608 ,R/TP
6 C573 CAP,TANTAL,CHIP ECTH0002702 1 uF,16V ,M ,STD ,1608 ,R/TP
6 C574 CAP,CERAMIC,CHIP ECCH0000276 1 uF,10V,Z,Y5V,HD,1608,R/TP
6 C575 CAP,CERAMIC,CHIP ECCH0004903 1 uF,6.3V ,Z ,Y5V ,TC ,1005 ,R/TP
6 C577 CAP,CERAMIC,CHIP ECCH0004903 1 uF,6.3V ,Z ,Y5V ,TC ,1005 ,R/TP
6 C578 CAP,CERAMIC,CHIP ECCH0000148 2.7 nF,50V,K,X7R,HD,1005,R/TP
6 C579 CAP,CERAMIC,CHIP ECCH0000149 3.3 nF,50V,K,X7R,HD,1005,R/TP
6 C580 CAP,CHIP,MAKER ECZH0003501 1 uF,6.3V ,K ,X5R ,HD ,1608 ,R/TP
6 C581 CAP,CERAMIC,CHIP ECCH0000122 47 pF,50V,J,NP0,TC,1005,R/TP
6 C582 CAP,CERAMIC,CHIP ECCH0000151 4.7 nF,25V,K,X7R,HD,1005,R/TP
6 C584 CAP,TANTAL,CHIP,MAKER ECTZ0005501 100 uF,6.3V ,M ,STD ,ETC ,R/TP
6 C585 CAP,TANTAL,CHIP,MAKER ECTZ0005501 100 uF,6.3V ,M ,STD ,ETC ,R/TP
6 C587 CAP,CERAMIC,CHIP ECCH0000149 3.3 nF,50V,K,X7R,HD,1005,R/TP
6 C589 CAP,CERAMIC,CHIP ECCH0000151 4.7 nF,25V,K,X7R,HD,1005,R/TP
6 C590 CAP,CERAMIC,CHIP ECCH0005705 10 uF,6.3V ,K ,X5R ,HD ,2012 ,R/TP
6 C592 CAP,TANTAL,CHIP,MAKER ECTZ0005501 100 uF,6.3V ,M ,STD ,ETC ,R/TP
6 C593 CAP,TANTAL,CHIP,MAKER ECTZ0005501 100 uF,6.3V ,M ,STD ,ETC ,R/TP
6 C601 CAP,CERAMIC,CHIP ECCH0000168 0.1 uF,16V,Z,Y5V,HD,1005,R/TP
6 C602 CAP,CERAMIC,CHIP ECCH0000168 0.1 uF,16V,Z,Y5V,HD,1005,R/TP
6 C603 CAP,CERAMIC,CHIP ECCH0000168 0.1 uF,16V,Z,Y5V,HD,1005,R/TP
6 C604 CAP,CERAMIC,CHIP ECCH0000168 0.1 uF,16V,Z,Y5V,HD,1005,R/TP
6 C605 CAP,CERAMIC,CHIP ECCH0000168 0.1 uF,16V,Z,Y5V,HD,1005,R/TP
6 C606 CAP,CERAMIC,CHIP ECCH0000137 330 pF,50V ,K ,X7R ,HD ,1005 ,R/TP
6 C607 CAP,CERAMIC,CHIP ECCH0000115 22 pF,50V,J,NP0,TC,1005,R/TP
6 C608 CAP,CERAMIC,CHIP ECCH0000115 22 pF,50V,J,NP0,TC,1005,R/TP
6 C609 CAP,CERAMIC,CHIP ECCH0000168 0.1 uF,16V,Z,Y5V,HD,1005,R/TP
6 C610 CAP,CERAMIC,CHIP ECCH0000168 0.1 uF,16V,Z,Y5V,HD,1005,R/TP
6 C611 CAP,CERAMIC,CHIP ECCH0000168 0.1 uF,16V,Z,Y5V,HD,1005,R/TP
6 C612 CAP,CERAMIC,CHIP ECCH0000168 0.1 uF,16V,Z,Y5V,HD,1005,R/TP
6 C613 CAP,CERAMIC,CHIP ECCH0000143 1 nF,50V,K,X7R,HD,1005,R/TP
6 C614 CAP,CERAMIC,CHIP ECCH0000168 0.1 uF,16V,Z,Y5V,HD,1005,R/TP
6 C615 CAP,CERAMIC,CHIP ECCH0000168 0.1 uF,16V,Z,Y5V,HD,1005,R/TP
- 274 - 10. EXPLODED VIEW & REPLACEMENT PART LIST
Location Level Description Part Number Specification Color Remark No.
6 C616 CAP,CERAMIC,CHIP ECCH0000182 0.1 uF,10V ,K ,X5R ,HD ,1005 ,R/TP
6 C617 CAP,CERAMIC,CHIP ECCH0000182 0.1 uF,10V ,K ,X5R ,HD ,1005 ,R/TP
6 C618 CAP,CERAMIC,CHIP ECCH0000168 0.1 uF,16V,Z,Y5V,HD,1005,R/TP
6 C619 CAP,CERAMIC,CHIP ECCH0000168 0.1 uF,16V,Z,Y5V,HD,1005,R/TP
6 C620 CAP,CERAMIC,CHIP ECCH0000168 0.1 uF,16V,Z,Y5V,HD,1005,R/TP
6 C621 CAP,CERAMIC,CHIP ECCH0000168 0.1 uF,16V,Z,Y5V,HD,1005,R/TP
6 C622 CAP,CERAMIC,CHIP ECCH0000168 0.1 uF,16V,Z,Y5V,HD,1005,R/TP
6 C623 CAP,CERAMIC,CHIP ECCH0000168 0.1 uF,16V,Z,Y5V,HD,1005,R/TP
6 C624 CAP,CERAMIC,CHIP ECCH0000168 0.1 uF,16V,Z,Y5V,HD,1005,R/TP
6 C625 CAP,CERAMIC,CHIP ECCH0000168 0.1 uF,16V,Z,Y5V,HD,1005,R/TP
6 C626 CAP,CERAMIC,CHIP ECCH0000168 0.1 uF,16V,Z,Y5V,HD,1005,R/TP
6 C627 CAP,CERAMIC,CHIP ECCH0000168 0.1 uF,16V,Z,Y5V,HD,1005,R/TP
6 C628 CAP,CERAMIC,CHIP ECCH0000168 0.1 uF,16V,Z,Y5V,HD,1005,R/TP
6 C629 CAP,CERAMIC,CHIP ECCH0000168 0.1 uF,16V,Z,Y5V,HD,1005,R/TP
6 C630 CAP,CERAMIC,CHIP ECCH0000168 0.1 uF,16V,Z,Y5V,HD,1005,R/TP
6 C631 CAP,CERAMIC,CHIP ECCH0000168 0.1 uF,16V,Z,Y5V,HD,1005,R/TP
6 C632 CAP,CERAMIC,CHIP ECCH0000168 0.1 uF,16V,Z,Y5V,HD,1005,R/TP
6 C633 CAP,CERAMIC,CHIP ECCH0000168 0.1 uF,16V,Z,Y5V,HD,1005,R/TP
6 C634 CAP,CERAMIC,CHIP ECCH0000168 0.1 uF,16V,Z,Y5V,HD,1005,R/TP
6 C635 CAP,CERAMIC,CHIP ECCH0000168 0.1 uF,16V,Z,Y5V,HD,1005,R/TP
6 C636 CAP,CERAMIC,CHIP ECCH0000276 1 uF,10V,Z,Y5V,HD,1608,R/TP
6 C637 CAP,CERAMIC,CHIP ECCH0000168 0.1 uF,16V,Z,Y5V,HD,1005,R/TP
6 C638 CAP,CERAMIC,CHIP ECCH0000168 0.1 uF,16V,Z,Y5V,HD,1005,R/TP
6 C639 CAP,CERAMIC,CHIP ECCH0000168 0.1 uF,16V,Z,Y5V,HD,1005,R/TP
6 C644 CAP,CERAMIC,CHIP ECCH0000168 0.1 uF,16V,Z,Y5V,HD,1005,R/TP
6 C739 CAP,CERAMIC,CHIP ECCH0000168 0.1 uF,16V,Z,Y5V,HD,1005,R/TP
CONN,JACK/PLUG,EARPHO 6 CN502 ENJE0003603 12 ,12 PIN,MMIC CONN.12P NE
CONNECTOR,BOARD TO 6 CN703 ENBY0002103 24 PIN,.5 mm,STRAIGHT ,SILVER , BOARD
EMD2 ,30 V,1 A,R/TP ,VF=1.5V(IF=200mA) , 6 D501 DIODE,SWITCHING EDSY0011901 IR=30uA(VR=10V)
u289 BGA ,289 PIN,R/TP ,ASIC / BASEBAND 6 D601 IC EUSY0135001 CONTROLLER / MARITA
6 D702 DIODE,TVS EDTY0006401 SC70-6L ,5 V,100 W,R/TP ,PB-FREE
6 FB701 RES,CHIP,MAKER ERHZ0000608 10 ohm,1/10W ,F ,1608 ,R/TP
6 FB702 FILTER,BEAD,CHIP SFBH0002302 120 ohm,1608 ,CHIP BEAD, 2000mA
- 275 - 10. EXPLODED VIEW & REPLACEMENT PART LIST
Location Level Description Part Number Specification Color Remark No.
1950 MHz,2140 MHz,1.45 dB,1.60 dB,41 dB,50 6 FL102 DUPLEXER,IMT SDMY0000701 dB,5.4*5.0*1.6 ,SMD ,
6 FL402 FILTER,SAW SFSY0024302 1842.5 MHz,1.4*1.1*0.6 ,SMD ,5pin, Unbal-Bal, 50//150
6 FL403 FILTER,SAW SFSY0024303 1960 MHz,1.4*1.1*0.6 ,SMD ,5pin, Unbal-Bal, 50//150
6 FL701 VARISTOR SEVY0005501 18 V, ,SMD ,4ch. R-Varistor Array(100Ohm,15pF)
6 FL703 VARISTOR SEVY0005501 18 V, ,SMD ,4ch. R-Varistor Array(100Ohm,15pF)
6 FL704 VARISTOR SEVY0005501 18 V, ,SMD ,4ch. R-Varistor Array(100Ohm,15pF)
6 L199 INDUCTOR,CHIP ELCH0005009 100 nH,J ,1005 ,R/TP ,
6 L301 FILTER,BEAD,CHIP SFBH0002302 120 ohm,1608 ,CHIP BEAD, 2000mA
6 L302 FILTER,BEAD,CHIP SFBH0002302 120 ohm,1608 ,CHIP BEAD, 2000mA
6 L303 FILTER,BEAD,CHIP SFBH0002302 120 ohm,1608 ,CHIP BEAD, 2000mA
6 L304 INDUCTOR,SMD,POWER ELCP0009401 4.7 uH,M ,2.8*2.6*1.0 ,R/TP ,
6 L403 FILTER,BEAD,CHIP SFBH0007103 75 ohm,1005 ,CHIP BEAD, 300mA
6 L404 FILTER,BEAD,CHIP SFBH0007103 75 ohm,1005 ,CHIP BEAD, 300mA
6 L405 INDUCTOR,CHIP ELCH0001413 22 nH,J ,1005 ,R/TP ,PBFREE
6 L406 INDUCTOR,CHIP ELCH0005006 33 nH,J ,1005 ,R/TP ,
6 L407 INDUCTOR,CHIP ELCH0005013 4.7 nH,S ,1005 ,R/TP ,
6 L408 INDUCTOR,CHIP ELCH0001408 6.8 nH,J ,1005 ,R/TP ,Pb Free
6 L409 INDUCTOR,CHIP ELCH0005013 4.7 nH,S ,1005 ,R/TP ,
6 L410 INDUCTOR,CHIP ELCH0001401 15 nH,J ,1005 ,R/TP ,Pb Free
6 L411 FILTER,BEAD,CHIP SFBH0007103 75 ohm,1005 ,CHIP BEAD, 300mA
6 L412 INDUCTOR,CHIP ELCH0007404 5.6 uH,K ,1608 ,R/TP ,
6 L413 INDUCTOR,CHIP ELCH0007403 100 uH,K ,2012 ,R/TP ,
6 L414 FILTER,BEAD,CHIP SFBH0007103 75 ohm,1005 ,CHIP BEAD, 300mA
6 L415 INDUCTOR,CHIP ELCH0001402 18 nH,J ,1005 ,R/TP ,Pb Free
6 L416 FILTER,BEAD,CHIP SFBH0007103 75 ohm,1005 ,CHIP BEAD, 300mA
3 X 4 UCSP ,10 PIN,R/TP ,600 mA BUCK REGULATORS / 6 N301 IC EUSY0136001 DYNAMIC OUTPUT VOLTAGE,PBFREE
6 N302 PAM SMPY0002801 26 dBm,40 %,83 A,-58 dBc,23.5 dB,8.0*6.0*1.4 ,SMD ,
6 N303 ISOLATOR,IMT SQMY0001001 1950 MHz,3.2*3.2*1.5 ,SMD ,1920~1980MHz
BGA ,64 PIN,R/TP ,6*6 mm, lead-free, Analog Baseband 6 N402 IC EUSY0133103 ASIC
6 N403 TRANSFORMER,MATCHING STMY0018401 6 PIN,SMD ,DCS TX BALUN
6 N404 TRANSFORMER,MATCHING STMY0018402 6 PIN,SMD ,GSM Tx Balun
6 N405 IC EUSY0132801 56 ball ,56 PIN,R/TP ,RFIC
- 276 - 10. EXPLODED VIEW & REPLACEMENT PART LIST
Location Level Description Part Number Specification Color Remark No.
6 N501 IC EUSY0171302 SOT-23 ,5 PIN,R/TP ,150mA 3.3V LDO, Pb-free
6 N502 IC EUSY0153001 SOT23-5 ,5 PIN,R/TP ,150 mA LDO REGULATOR / 1.5V
CSP ,25 PIN,R/TP ,6 CHANNEL ESD FILTER, EMP 6 N504 IC EUSY0171201 SOLUTION, Pb-free
CSP ,20 PIN,R/TP ,7 CHANNEL ESD FILTER ARRAY, 6 N701 IC EUSY0171401 KNATTE, Pb-free
6 Q601 TR,BJT,NPN EQBN0014901 SOT323 ,.2 W,R/TP ,NPN SWITCHING TR, Pb free
6 Q602 TR,BJT,NPN EQBN0013301 2-2H1A ,.1 W,R/TP ,VEBO=6V, Pb free
6 Q701 TR,BJT,NPN EQBN0013701 EMT6 ,150 mW,R/TP ,DUAL TRANSISTORS
6 R2130 RES,CHIP ERHY0000201 0 ohm,1/16W,J,1005,R/TP
6 R2131 RES,CHIP ERHY0000201 0 ohm,1/16W,J,1005,R/TP
6 R2241 RES,CHIP ERHY0000201 0 ohm,1/16W,J,1005,R/TP
6 R2248 RES,CHIP ERHY0000216 68 ohm,1/16W,J,1005,R/TP
6 R2249 RES,CHIP ERHY0000216 68 ohm,1/16W,J,1005,R/TP
6 R2250 RES,CHIP ERHY0000201 0 ohm,1/16W,J,1005,R/TP
6 R2252 RES,CHIP ERHY0000261 10K ohm,1/16W,J,1005,R/TP
6 R2253 RES,CHIP ERHY0000261 10K ohm,1/16W,J,1005,R/TP
6 R301 RES,CHIP ERHY0000138 33K ohm,1/16W,F,1005,R/TP
6 R302 RES,CHIP ERHY0000280 100K ohm,1/16W,J,1005,R/TP
6 R303 RES,CHIP ERHY0000271 39K ohm,1/16W,J,1005,R/TP
6 R306 RES,CHIP ERHY0000201 0 ohm,1/16W,J,1005,R/TP
6 R307 RES,CHIP ERHY0000201 0 ohm,1/16W,J,1005,R/TP
6 R308 RES,CHIP ERHY0000201 0 ohm,1/16W,J,1005,R/TP
6 R404 RES,CHIP ERHY0000201 0 ohm,1/16W,J,1005,R/TP
6 R405 RES,CHIP ERHY0000280 100K ohm,1/16W,J,1005,R/TP
6 R406 RES,CHIP ERHY0000201 0 ohm,1/16W,J,1005,R/TP
6 R409 RES,CHIP ERHY0000201 0 ohm,1/16W,J,1005,R/TP
6 R410 RES,CHIP ERHY0000220 100 ohm,1/16W,J,1005,R/TP
6 R411 RES,CHIP ERHY0000220 100 ohm,1/16W,J,1005,R/TP
6 R412 RES,CHIP ERHY0000201 0 ohm,1/16W,J,1005,R/TP
6 R414 RES,CHIP ERHY0000206 18 ohm,1/16W,J,1005,R/TP
6 R415 RES,CHIP ERHY0000228 270 ohm,1/16W,J,1005,R/TP
6 R416 RES,CHIP ERHY0000228 270 ohm,1/16W,J,1005,R/TP
6 R417 RES,CHIP ERHY0000201 0 ohm,1/16W,J,1005,R/TP
6 R418 RES,CHIP ERHY0000201 0 ohm,1/16W,J,1005,R/TP
- 277 - 10. EXPLODED VIEW & REPLACEMENT PART LIST
Location Level Description Part Number Specification Color Remark No.
6 R420 INDUCTOR,CHIP ELCH0005015 6.8 nH,S ,1005 ,R/TP ,
6 R421 RES,CHIP ERHY0000201 0 ohm,1/16W,J,1005,R/TP
6 R422 INDUCTOR,CHIP ELCH0005015 6.8 nH,S ,1005 ,R/TP ,
6 R423 RES,CHIP ERHY0000220 100 ohm,1/16W,J,1005,R/TP
6 R424 RES,CHIP ERHY0000220 100 ohm,1/16W,J,1005,R/TP
6 R425 RES,CHIP ERHY0000235 560 ohm,1/16W,J,1005,R/TP
6 R426 RES,CHIP ERHY0000222 120 ohm,1/16W,J,1005,R/TP
6 R427 RES,CHIP ERHY0000231 390 ohm,1/16W,J,1005,R/TP
6 R428 RES,CHIP ERHY0000201 0 ohm,1/16W,J,1005,R/TP
6 R429 RES,CHIP ERHY0000201 0 ohm,1/16W,J,1005,R/TP
6 R430 RES,CHIP ERHY0000201 0 ohm,1/16W,J,1005,R/TP
6 R431 RES,CHIP ERHY0000201 0 ohm,1/16W,J,1005,R/TP
6 R501 RES,CHIP ERHY0000201 0 ohm,1/16W,J,1005,R/TP
6 R502 RES,CHIP ERHY0000201 0 ohm,1/16W,J,1005,R/TP
6 R507 RES,CHIP ERHY0000280 100K ohm,1/16W,J,1005,R/TP
6 R508 RES,CHIP ERHY0000201 0 ohm,1/16W,J,1005,R/TP
6 R509 RES,CHIP ERHY0000241 1K ohm,1/16W,J,1005,R/TP
6 R513 RES,CHIP ERHY0000274 51K ohm,1/16W,J,1005,R/TP
6 R514 RES,CHIP ERHY0000261 10K ohm,1/16W,J,1005,R/TP
6 R515 RES,CHIP ERHY0000261 10K ohm,1/16W,J,1005,R/TP
6 R524 RES,CHIP ERHY0000241 1K ohm,1/16W,J,1005,R/TP
6 R525 RES,CHIP ERHY0000241 1K ohm,1/16W,J,1005,R/TP
6 R529 RES,CHIP ERHY0000280 100K ohm,1/16W,J,1005,R/TP
6 R530 RES,CHIP ERHY0000201 0 ohm,1/16W,J,1005,R/TP
6 R531 RES,CHIP ERHY0000264 18K ohm,1/16W,J,1005,R/TP
6 R532 RES,CHIP ERHY0000264 18K ohm,1/16W,J,1005,R/TP
6 R533 RES,CHIP ERHY0000201 0 ohm,1/16W,J,1005,R/TP
6 R534 RES,CHIP ERHY0000264 18K ohm,1/16W,J,1005,R/TP
6 R537 RES,CHIP ERHY0000264 18K ohm,1/16W,J,1005,R/TP
6 R539 RES,CHIP ERHY0000201 0 ohm,1/16W,J,1005,R/TP
6 R566 RES,CHIP ERHY0000201 0 ohm,1/16W,J,1005,R/TP
6 R567 RES,CHIP ERHY0000280 100K ohm,1/16W,J,1005,R/TP
6 R569 RES,CHIP ERHY0000201 0 ohm,1/16W,J,1005,R/TP
6 R572 RES,CHIP ERHY0000236 620 ohm,1/16W,J,1005,R/TP
- 278 - 10. EXPLODED VIEW & REPLACEMENT PART LIST
Location Level Description Part Number Specification Color Remark No.
6 R573 RES,CHIP ERHY0000201 0 ohm,1/16W,J,1005,R/TP
6 R574 RES,CHIP ERHY0000236 620 ohm,1/16W,J,1005,R/TP
6 R576 RES,CHIP ERHY0000201 0 ohm,1/16W,J,1005,R/TP
6 R577 RES,CHIP ERHY0000201 0 ohm,1/16W,J,1005,R/TP
6 R578 RES,CHIP ERHY0000201 0 ohm,1/16W,J,1005,R/TP
6 R579 RES,CHIP ERHY0000201 0 ohm,1/16W,J,1005,R/TP
6 R580 CAP,CERAMIC,CHIP ECCH0002003 33 nF,16V ,K ,B ,TC ,1005 ,R/TP
6 R581 RES,CHIP ERHY0000201 0 ohm,1/16W,J,1005,R/TP
6 R582 RES,CHIP ERHY0000201 0 ohm,1/16W,J,1005,R/TP
6 R583 CAP,CERAMIC,CHIP ECCH0002003 33 nF,16V ,K ,B ,TC ,1005 ,R/TP
6 R584 RES,CHIP ERHY0000201 0 ohm,1/16W,J,1005,R/TP
6 R585 RES,CHIP ERHY0000201 0 ohm,1/16W,J,1005,R/TP
6 R586 RES,CHIP ERHY0000280 100K ohm,1/16W,J,1005,R/TP
6 R587 RES,CHIP ERHY0000201 0 ohm,1/16W,J,1005,R/TP
6 R588 RES,CHIP ERHY0000201 0 ohm,1/16W,J,1005,R/TP
6 R589 RES,CHIP ERHY0000280 100K ohm,1/16W,J,1005,R/TP
6 R590 RES,CHIP ERHY0000259 8.2K ohm,1/16W,J,1005,R/TP
6 R591 RES,CHIP ERHY0000282 120K ohm,1/16W,J,1005,R/TP
6 R592 RES,CHIP ERHY0000282 120K ohm,1/16W,J,1005,R/TP
6 R594 RES,CHIP ERHY0000254 4.7K ohm,1/16W,J,1005,R/TP
6 R595 RES,CHIP ERHY0000261 10K ohm,1/16W,J,1005,R/TP
6 R596 RES,CHIP ERHY0000282 120K ohm,1/16W,J,1005,R/TP
6 R597 RES,CHIP ERHY0000282 120K ohm,1/16W,J,1005,R/TP
6 R598 RES,CHIP ERHY0000254 4.7K ohm,1/16W,J,1005,R/TP
6 R601 RES,CHIP ERHY0000254 4.7K ohm,1/16W,J,1005,R/TP
6 R602 RES,CHIP ERHY0000280 100K ohm,1/16W,J,1005,R/TP
6 R604 RES,CHIP ERHY0000201 0 ohm,1/16W,J,1005,R/TP
6 R606 RES,CHIP ERHY0000213 47 ohm,1/16W,J,1005,R/TP
6 R608 RES,CHIP ERHY0000250 3.3K ohm,1/16W,J,1005,R/TP
6 R609 RES,CHIP ERHY0000250 3.3K ohm,1/16W,J,1005,R/TP
6 R610 RES,CHIP ERHY0000243 1.2K ohm,1/16W,J,1005,R/TP
6 R613 RES,CHIP ERHY0000280 100K ohm,1/16W,J,1005,R/TP
6 R614 RES,CHIP ERHY0000233 470 ohm,1/16W,J,1005,R/TP
6 R615 RES,CHIP ERHY0000283 130K ohm,1/16W,J,1005,R/TP
- 279 - 10. EXPLODED VIEW & REPLACEMENT PART LIST
Location Level Description Part Number Specification Color Remark No.
6 R616 RES,CHIP ERHY0000213 47 ohm,1/16W,J,1005,R/TP
6 R617 RES,CHIP ERHY0000275 56K ohm,1/16W,J,1005,R/TP
6 R618 RES,CHIP ERHY0000280 100K ohm,1/16W,J,1005,R/TP
6 R619 RES,CHIP ERHY0000280 100K ohm,1/16W,J,1005,R/TP
6 R620 RES,CHIP ERHY0000275 56K ohm,1/16W,J,1005,R/TP
6 R621 RES,CHIP ERHY0000280 100K ohm,1/16W,J,1005,R/TP
6 R626 RES,CHIP ERHY0000241 1K ohm,1/16W,J,1005,R/TP
6 R627 RES,CHIP ERHY0000201 0 ohm,1/16W,J,1005,R/TP
6 R628 RES,CHIP ERHY0000280 100K ohm,1/16W,J,1005,R/TP
6 R629 RES,CHIP ERHY0000201 0 ohm,1/16W,J,1005,R/TP
6 R630 RES,CHIP ERHY0000250 3.3K ohm,1/16W,J,1005,R/TP
6 R631 RES,CHIP ERHY0000220 100 ohm,1/16W,J,1005,R/TP
6 R634 RES,CHIP ERHY0000282 120K ohm,1/16W,J,1005,R/TP
6 R636 RES,CHIP ERHY0000280 100K ohm,1/16W,J,1005,R/TP
6 R641 RES,CHIP ERHY0000280 100K ohm,1/16W,J,1005,R/TP
6 R653 RES,CHIP ERHY0000292 470K ohm,1/16W,J,1005,R/TP
6 R654 RES,CHIP ERHY0000280 100K ohm,1/16W,J,1005,R/TP
6 R655 RES,CHIP ERHY0000280 100K ohm,1/16W,J,1005,R/TP
6 R727 RES,CHIP ERHY0000204 12 ohm,1/16W,J,1005,R/TP
6 R741 RES,CHIP ERHY0000249 2.7K ohm,1/16W,J,1005,R/TP
6 R742 RES,CHIP ERHY0000204 12 ohm,1/16W,J,1005,R/TP
6 S601 CONN,SOCKET ENSY0014101 8 PIN,ETC , ,1.1 mm,T-Flash Memory Socket
6 U502 IC EUSY0232807 sot 23-5 ,5 PIN,R/TP ,1.8V,150mA LDO
MicroStar Junior ,15 PIN,R/TP ,1.1W Class-D Mono Audio 6 U504 IC EUSY0160001 AMP
MicroStar Junior ,15 PIN,R/TP ,1.1W Class-D Mono Audio 6 U505 IC EUSY0160001 AMP
FFP16 ,16 PIN,R/TP ,3D SURROUND AUDIO 6 U507 IC EUSY0175001 PROCESSOR
MICROBUMP ,10 PIN,R/TP ,Dual SPDT Analog switch(Pb 6 U508 IC EUSY0188601 Free)
6 U509 IC EUSY0142501 LLP ,8 PIN,R/TP ,Dual 105mW Headphone Amplifier
uCSP ,10 PIN,R/TP ,Dual Analog Switch, 300MHz 6 U601 IC EUSY0163901 Bandwidth
uCSP ,10 PIN,R/TP ,Dual Analog Switch, 300MHz 6 U602 IC EUSY0163901 Bandwidth
SCSP ,88 PIN,ETC ,512M(256*2) MLC NOR +128M (64*2) 6 U603 IC EUSY0211101 PS/ 1.8V/ PB FREE
- 280 - 10. EXPLODED VIEW & REPLACEMENT PART LIST
Location Level Description Part Number Specification Color Remark No.
6 Z401 FILTER,SAW SFSY0024301 942.5 MHz,1.4*1.1*0.6 ,SMD ,5pin, Unbal-Bal, 50//150
5 SPFY PCB,MAIN SPFY0106301 FR-4 ,0.8 mm,STAGGERED-8 ,
3 SUMY00 MICROPHONE SUMY0010702 UNIT ,44 dB,4*1.5 ,spring type
- 281 - 10. EXPLODED VIEW & REPLACEMENT PART LIST
10.3 Accessory Note: This Chapter is used for reference, Part order is ordered by SBOM standard on GCSC
Location Level Description Part Number Specification Color Remark No.
3 MHBY00 HANDSTRAP MHBY0000404 Hand Strap 135mm Black
3.7 V,1400 mAh,1 CELL,PRISMATIC ,U8130 BATTERY(Li- 3 SBPL00 BATTERY PACK,LI-ION SBPL0072221 Silver Polymer) 1400mA(Typical)
3 SGDY00 DATA CABLE SGDY0005601 DK-40G ,K8000 24PIN I/O + USB A TYPE
3 SGEY00 EAR PHONE/EAR MIKE SET SGEY0003707 U880,8550 ,GRAY-AIR CAP,2.0TMMI12P 49
3 SSAD00 ADAPTOR,AC-DC SSAD0007848 FREE ,50 Hz,4.6 V,0.8 A,CE ,3G
- 282 -