Highly Efficient Dynamic Supply Modulator for

Mobile Communication Systems

A Dissertation Presented to The Academic Faculty

By

Eung Jung Kim

In Partial Fulfillment of the Requirements for the Degree Doctor of Philosophy in the School of Electrical and Computer Engineering

Georgia Institute of Technology Atlanta, GA 30332

August, 2011

Highly Efficient Dynamic Supply Modulator for

Mobile Communication Systems

Approved by:

Dr. Kevin Kornegay, Advisor Dr. Shyh-Chiang Shen School of Electrical and Computer School of Electrical and Computer Engineering Engineering Georgia Institute of Technology Georgia Institute of Technology

Dr. Jong-Man Kim Dr. Jun-Hee Heu School of Electrical and Computer School of Electrical Engineering Engineering Seoul National University Georgia Institute of Technology

Dr. Chang-Ho Lee Samsung Design Center Date Approved : April, 2011

Acknowledgements

First of all, I would like to acknowledge his great support and supervision of my research advisor, Professor Kevin Kornegay. I am also grateful to all the committee members, Professor Jongman Kim, Professor Shyh-Chiang Shen, Professor Chang-

Ho Lee, and Dr. Jun-Hee Hue for their time and effort in reviewing my dissertation and serving as my defense committee members. I would like to specially express my gratitude to Dr. Joy Laskar and Dr. Chang-Ho Lee for their great support and guidance throughout this research.

I would also like to thank Dr. Changhyuk Cho and Dr. Woonyun Kim for their technical guidance and assistance. I am thankful to my colleague members in

Microwave Application Group for their invaluable support and technical discussion.

Most of all, I am especially grateful to my parents and wife for their unconditional love and support. All the credits for whatever I have accomplished go to my parents for their endless support, insurmountable belief in my abilities. Without their support,

I would not have been keeping me motivated and focused. I cannot express my love and gratitude enough to my wife for her never-end support throughout my life.

Without her encouragement and support, I would not be able to complete this work.

At the same token, I wish to thank all the other family members and friends whose prayers and blessings have always helped me overcome many hurdles during the course of this graduate research.

III Table of Contents

Acknowledgements ...... III

List of Tables ...... VIII

List of Figures ...... IX

Glossary ...... XIV

Summary ...... XVI

Chapter 1

Introduction ...... 1

1.1 Background ...... 1

1.2 Motivations...... 4

Chapter 2

Efficient RF Transmitter Design ...... 7

2.1 Challenges in Efficient Transmitter Design ...... 7

2.1.1 Limiting Factors to the Efficient RF Transmitter Design ...... 7

2.2 Limiting Factors in a Static Power Supply...... 12

2.2.1 Linear Regulators ...... 12

2.2.2 Switching Regulators ...... 13

IV 2.3 Efficiency Improvement Techniques for Linear Transmitters ...... 15

2.3.1 Adaptive Gate-Bias Voltage Control ...... 15

2.3.2 Envelope-Tracking Systems ...... 16

2.3.3 Average Power Tracking System ...... 18

2.3.4 Envelope Elimination and Restoration and Polar Modulation ...... 19

2.3.5 Various Topologies for a Dynamic Supply Modulator ...... 21

2.4 Conclusion ...... 22

Chapter 3

Designing Synchronous Step-down Converter in Voltage-mode PWM

Control ...... 23

3.1 Pulse Width Modulation (PWM) in Voltage Mode Control ...... 23

3.1.1 Steady-State Analysis and Small Signal Model ...... 27

3.2 Selection of Power Inductor and Load Capacitor ...... 35

3.3 Circuit Topology and Operation ...... 36

3.3.1 Dead-time Control ...... 36

3.3.2 Gate Driving Circuit and Power Transistor...... 37

3.3.3 Reference Generation ...... 40

3.3.4 Error Amplifier Design ...... 46

3.3.5 PWM Comparator ...... 48

3.3.6 Adjustable Triangular Ramp Signal Generator ...... 52

V Chapter 4

Switching-Frequency Modulation for Spurious-noise Reduction in a DC-

to-DC Converter for RF Power Amplifier ...... 55

4.1 Overview ...... 56

4.2 Analysis ...... 58

4.3 Achieving Spread Spectrum ...... 62

4.4 Experimental Results...... 68

Chapter 5

Average Inductor-Current-Sensing Circuit ...... 73

5.1 Overview ...... 73

5.2 Simulation Results...... 77

5.3 Conclusion ...... 79

Chapter 6

Parallel Connected Dual Switching Converter ...... 80

6.1 Overview ...... 80

6.2 Circuit Implementation ...... 84

6.2.1 Design Voltage Mode Control Loop ...... 84

6.2.2 Floor Plan ...... 86

6.2.3 Layout...... 90

6.2.4 PCB Design ...... 92

VI 6.3 Simulation Results...... 93

6.4 Experimental Results...... 98

6.5 Conclusions ...... 102

Chapter 7

Conclusions ...... 104

7.1 Challenges ...... 104

7.2 Technical Contributions and Impacts of the Dissertation ...... 105

7.3 Future Work ...... 106

References ...... 107

Vita…...... 114

VII List of Tables

Table 1. Modulation standards used in mobile communication devices [1] ...... 2

Table 2. Comparison of published envelope amplifiers ...... 22

Table 3. Error amplifier specifications compliance matrix...... 47

Table 4. PWM comparator specifications compliance matrix...... 50

Table 5. Frequency changes in the frequency of the triangular ramp signal...... 54

Table 6. Switching frequency and output current of the fast and slow converter ...... 82

Table 7. Summary of the integrated dual converter’s experimental results...... 103

VIII List of Figures

Figure 1. Evolution of wireless communication Systems...... 1

Figure 2. Comparison of linear operation with a fixed-gain for envelope varying

signals and compressed operation with a variable gain for constant envelope

signals...... 4

Figure 3. Variation of efficiency with output power for various amplifier

configurations and the output power probability distribution for CDMA signals. 8

Figure 4. Illustration of an amplitude-modulated waveform in a time domain...... 10

Figure 5. Output power distribution for CDMA modulation under short and long time

variations...... 11

Figure 6. Schematic of a typical linear regulator...... 12

Figure 7. Schematic of a typical step-down switching regulator...... 14

Figure 8. Simplified PA model with adaptive gate biasing control...... 16

Figure 9. Schematic of a typical envelope tracking system...... 17

Figure 10. Schematic of (a) an envelope elimination and restoration (EER) system

and (b) a polar modulation transmitter...... 20

Figure 11. Voltage-mode PWM controlled, step-down DC-to-DC converter...... 23

Figure 12. Cross-sectional view of a NMOS transistor (a) in a standard CMOS

process (b) in a triple-well CMOS process with a deep n-well layer...... 25

Figure 13. Voltage and current waveforms of a voltage-mode PWM controlled, step-

down DC-to-DC converter...... 26

IX Figure 14. Diagram for a voltage-mode PWM controlled, step-down DC-to-DC

converter...... 28

Figure 15. Different types of loop filter for phase boosting...... 30

Figure 16. (a) Type-III loop filter and its Transfer function (b) frequency locations of

poles and zeros for type-III Loop Filter...... 30

Figure 17. Frequency response of a type-III loop filter...... 31

Figure 18. Ripple voltage with a finite capacitance at the output LC-filter...... 34

Figure 19. Dead-time control logic circuit...... 37

Figure 20. Schematic of the power transistors and their gate driving circuits...... 38

Figure 21. Waveform of the gate voltage in NMOS and PMOS power transistors with

dead-time control...... 40

Figure 22. Conceptual schematic for a bandgap reference circuit...... 41

Figure 23. Block diagram of the proposed reference generation circuit...... 44

Figure 24. Simulated results for (a) start-up of the reference generation circuit (b)

characteristics of the bandgap reference voltage and the 3.0 volt regulated

voltage output...... 45

Figure 25. Schematic of the error amplifier...... 47

Figure 26. Open-loop gain and phase of the error amplifier when the input common

level is varied from 0.1 V to 2.5 V ...... 48

Figure 27. Schematic of a high-gain, open-loop comparator with internal positive

feedback for hysteresis transfer curve...... 50

Figure 28. (a) Comparator transfer curve and transient response to a noisy input (b)

simulated comparator transfer curve indicating trip points with hysteresis...... 51

X Figure 29. Complete schematic of the triangular ramp signal generator...... 53

Figure 30. Schematic of the current multiplier...... 53

Figure 31. Spectrum spreading effect in the switching noise spurs at the output of a

switching power supply from the proposed PWM ramp signal modulation...... 58

Figure 32. Pulse-width-modulated square wave output from a linearly modulated

triangular PWM ramp signal...... 60

Figure 33. Calculated spurious noise peak for different number of frequency steps and

for different frequency ranges...... 61

Figure 34. Time mismatch between on-time and off-time in linearly modulated PWM

signal...... 62

Figure 35. Conceptual diagram of the DC-to-DC converter with the switching

frequency modulator...... 63

Figure 36. Block diagram of the digital current modulator...... 64

Figure 37. Block diagram of (a) 6-bit Current Steering DAC (b) digital PWM ramp-

signal modulator...... 66

Figure 38. Conceptual diagram illustrating (a) the proposed linear frequency

modulation of the triangular PWM ramp signal using monotonically increasing

bits (b) the proposed pseudo-random frequency modulation of the ramp signal

using the linear feedback shift register...... 67

Figure 39. Micro-photograph of the step-down DC-to-DC converter with a digital

PWM ramp signal modulator...... 68

Figure 40. Calculated power spectrum density of VCLK...... 70

XI Figure 41. Calculated spurious noise peak for different number of frequency steps and

for different frequency ranges...... 70

Figure 42. (a) Triangular ramp signal at a constant frequency (b) randomly modulated

triangular ramp signal (c) linear modulated triangular ramp signal...... 71

Figure 43. (a) Output spectrum of the DC-to-DC converter using a fixed 2 MHz

switching frequency and the proposed random frequency modulation (b) output

spectrum of the DC-to-DC converter with monotonic frequency modulation with

various frequency steps...... 72

Figure 44. Proposed average inductor current sensing circuit...... 74

Figure 45. Switching operation of the proposed current-sensing circuit (a) for a turn-

on state (b) for a turn-off state...... 76

Figure 46. Simulated waveforms for output voltage, inductor current, and sensed

voltage output...... 77

Figure 47. Simulated waveforms (a) for 600kHz sine wave with 4 Ω load (b) for 100

kHz rectangular wave with 4 Ω load...... 78

Figure 48. Proposed dual switching converter...... 82

Figure 49. Frequency response of the output LC-filter (L2 = 250nH, ResrL = 250mΩ

including metal resistance, Cload = 150nF, ResrC = 10mΩ, and Rload = 5Ω). . 84

Figure 50. Gain and phase plot of the type-III frequency compensation error amplifier

and power filter...... 86

Figure 51. Power tree of the dual converter...... 87

Figure 52. Floor plan for the proposed dual converter...... 88

Figure 52. Complete block diagram of the dual converter...... 89

XII Figure 53. Screen capture of the layout for the parallel connected dual converter. .... 90

Figure 54. Layout of the top two metal layers to connect the power transistors to the

output pins...... 91

Figure 55. (a) Fast converter current path (b) slow converter current path...... 93

Figure 56. Simulated waveforms for voltage steps (a) voltage outputs (b) current

outputs (c) voltage and current ripples...... 95

Figure 57. Simulated waveforms for (a) Vramp and Vout (b) output Currents...... 96

Figure 58. Simulated waveforms for (a) Vramp and Vout (b) output currents...... 97

Figure 59. Efficiency of the proposed dual converter (Rload = 4 Ω)...... 98

Figure 60. Duty ratio change in the slow converter...... 99

Figure 61. Phase node voltage changes in the fast converter and the slow converter

...... 100

Figure 62. Output transient response (a) to a 100 kHz saw-shape input signal (b) to a

100 kHz square wave signal (c) to a 100kHz sine wave (Rload = 4 Ω)...... 101

XIII Glossary

2G/3G Second Generation/Third Generation ACPR Adjacent Channel Power Ratio ACLR Adjacent Channel Leakage Power Ratio BER Bit Error Rate BW Bandwidth CDMA Code Division Multiple Access DAC Digital-to-Analog Converter DCM Discontinuous Conduction Mode EDGE Enhanced Data Rate for GSM Evolution EER Envelope Elimination and Restoration ESL Equivalent Series Inductance ESR Equivalent Series Resistance EVM Error Vector Magnitude GaAs Gallium Arsenide GSM Global System for Mobile Communications HPSK Hybrid Phase Shift Keying IC Integrated Circuit ICMR Input Common Mode Range IF Intermediate Frequency LAN Local Area Network LDMOS Laterally Diffused Metal Oxide Semiconductor LDO Low Dropout LHP Left-half Plane OFDM Orthogonal Frequency Division Multiplexing MOSFET Metal Oxide Semiconductor Field Effect Transistor NPR Noise Power Ratio OCQPSK Orthogonal Complex Quadrature Phase Shift

XIV Keying PA Power Amplifier PAE Power Added Efficiency PAR Peak-to-Average Ratio PCB Printed Circuit Board PDF Probability Density Fuction PH Phase Margin PTAT Proportional to Absolute Temperature QPSK Quadrature Phase Shift Keying RF Radio Frequency RHP Right-half plane RX Receiver SOP Silicon-on-Package SIP Silicon-in-Package SOC Silicon-on-Chip TX Transmitter UGF Unity-gain Frequency VCO Voltage Controlled Oscillator VGA Variable Gain Amplifier VLSI Very Large Scale Integration WCDMA Wideband Code Division Multiple Access WiMAX Worldwide Interoperability for Microwave Access WLAN Wireless Local Area Network

XV Summary

There is no single answer to how to improve the efficiency of wireless transmitter while maintaining its linearity and satisfying all other design specifications. More realistic approach to this problem should be thinking about how to combine similar elements in a right proportion to maximize the overall performance.

The conflicting requirements of high linearity and high efficiency impose an enormous challenge for the RF transmitter design. In this research, switching modulation technique is investigated, and the experimental results shows that the spurious noise from the switching converter can be reduced more than 53 dBm by periodically or randomly modulating the switching frequency of the switching converter.

To improve the efficiency of the switching converter without degrading its closed-loop transient response speed, the dual switching converter that incorporates two different types of switching converters is designed. Simulation and experimental results show that the dual switching converter topology has high performance without large hardware penalties.

The proposed current-sensing circuit can sense the average current out of the fast converter with a high switching frequency (> 30MHz), and the sensed voltage output effectively control the output current of the slow converter. Experimental results shows that, when a wide bandwidth triangular pulse, sine wave, and saw-shaped signal are applied to the dual converter, the fast converter effectively provides the

XVI high frequency part of the output current and the slow converter provides the low frequency part of the output current. The large ripples from the slow converter are effectively absorbed by the fast converter, so the actual ripple voltage was less than

50mV with 150nF load capacitor. The dual converter is fabricated in a standard 0.18

µm CMOS process.

XVII

Chapter 1

Introduction

1.1 Background

Figure 1. Evolution of wireless communication Systems.

The explosive growth of wireless technology around the late 1990s has changed the fundamental basis of our life. People now have easy access to the unlimited amount of information at anytime from anywhere in the world via their mobile communication devices. Mobile communication devices can transmit or receive data without permanent connection to a power grid or a wired-line network. With advances in battery technology and semiconductor processing, multiple wide-area and local-area wireless systems are now deployed in various places around the world. A true ubiquitous coverage of mobile communication systems is now possible.

Table 1. Modulation standards used in mobile communication devices [1]

Peak-Minimum Power Bandwidth Peak-Average Antenna Modulation Power Ratio Control System (MHz) Power Ratio (dB) Power (dB) Range

AMPS 0.03 FM 0 0 28 25 GPRS 0.20 GMSK 0 0 33 30 GSM 0.20 GMSK 0 0 33 30 EDGE 0.20 3p/8 - 8PSK 3.2 17 27 30 UMTS 3.84 HPSK 3.5 - 7 infinite 24 80 WCDMA 3.84 HPSK 3.5 - 7 infinite 24 80 CDMA 1.23 HPSK 4 - 9 infinite 24 80 2000 802.11b 11.0 QPSK 3 infinite 20 ― 802.11a/g 18.0 OFDM 6 - 17 infinite 20 ―

Many of the currently available mobile system are outlined in Table 1. Characteristics of these systems are widely spanned with a broad combination of constant-envelope and envelope-varying signals, time-division (half-duplex) and code-division (full-duplex) multiplexing, and high to very low output powers. As a result, a market for RF (Radio

Frequency) power amplifiers (PAs) that can operate in multi-modes and multi-bands has been grown.

While much of the commercial growth of mobile technology in recent decades can be attributed to mobility, there is much room left for innovation in the radio architecture and circuit design. For a mobile terminal, the overall system cost must not only be low, but

2 the energy source of the terminal should last long enough to ensure the reliability of the services to the terminal’s users. The efficiency of a conventional RF PA is at maximum when the RF PA is operating in its saturation region, and the output power of the PA does not depend on the input power. Therefore, output-power control is achieved by varying the supply voltage of the power-stage transistors. However, if the input RF signal is amplitude modulated, the saturated RF PA will act as a hard limiter and cut off the amplitude of the varying envelope above the supply voltage. To amplify the envelope- varying input signal without distortion, the RF PA must be operated linearly.

As shown in Figure 2, to achieve a high efficiency, the PA should be operated in the saturation region as a variable gain device, but, to achieve high signal fidelity, the PA needs to be in the linear region with a fixed gain. Because the gain compression of the PA gradually increases as the output-power level approaches to the saturation level, the PA encounters more distortion as the output power increases.

To avoid signal-distortion problem, an RF PA is operated at the backoff region by limiting the peak output-power level in the linear mode below the maximum output power in the saturation mode, but output-power backoff is undesirable because it reduces the efficiency of PAs. To keep the battery lifetime high, more output-signal distortion is often allowed as a trade-off for a higher efficiency, but as the modulation schemes get even more complex, the allowance for the signal distortion is very limited.

These problems have been issued over many years, and many researchers have investigated extensively and came up with many possible solutions such as gate/base modulation, envelope-elimination-and-restoration (EER) [2-6], envelope tracking (ET)

3 [7-11], pre-distortion, feedback, feed-forward, doherty [12], linear-amplification-with- nonlinear-control (LINC), and gate dynamic biasing.

Figure 2. Comparison of linear operation with a fixed-gain for envelope varying signals and compressed operation with a variable gain for constant envelope signals.

1.2 Motivations

An RF power amplifier is the final block in a wireless transmitter. The role of an RF

PA is to accurately and efficiently amplify the input RF signal by providing power gain and minimum distortion to the load. The most important design concerns for RF PAs are efficiency and linearity. In a typical RF PA these two design parameters are in an inverse relationship as discussed in [13]. The maximum output power and power gain of an RF

PA is defined as

4

Maximum Output Power : $ , (1) 00 L  Ŷ 0 "

Power Gain : , (2) IH 6  C

where is the transformed antenna impedance. The efficiency of the PA can be defined

" in two different ways, drain efficiency and Power Added Efficiency (PAE), as

Drain Efficiency : , (3) IH ô>  0/

Power Added Efficiency (PAE) : , (4) IH . C ô6-1  0/

where is the DC power from the power supply. The PAE more accurately describes 0/ the performance of the PA because the PAE includes the loss due to the input power and is a function of the power gain. From (2) and (4), the PAE can be defined as

Power Added Efficiency : ŵ . (5) IHŵ .  6 ô6-1  0/

(5) shows the dependence of the PAE on the power gain that the PAE approaches the drain efficiency as the power gain goes to infinity. For the following sections, the drain efficiency will be used to describe the challenges in efficient RF PA design rather than ô> the PAE that is more complicated and process dependent.

5 If a power management system can dynamically ad aptively change the supply of the

RF power amplifier and extend the linear operation region, then the power amplifier can operate with less power backoff.

6 Chapter 2

Efficient RF Transmitter Design

2.1 Challenges in Efficient Transmitter Design

2.1.1 Limiting Factors to the Efficient RF Transmitter Design

In portable radio devices a highly efficient PA is desirable because a PA typically has dominant power consumption. There are several reasons why an RF PA cannot be operated at its maximum possible efficiency. The first is the modulation of an RF signal.

As a consequence of the high data-rates requirement from modern digital-communication standards, the amplitude and phase of RF signals are modulated to maximize spectral usage in a frequency band. The linearity of RF PAs becomes very critical. A traditional approach of increasing the linearity of an RF PA is to backoff its output-power level and minimize the compression of the peak envelope excursions until the distortion is reduced to an acceptable level [8, 14]. In PA design there exists an inherent trade-off between linearity and efficiency, and power backoff inevitably leads to significant reduction in output power and efficiency.

To reduce the distortion from non-linear characteristics such as the gain compression of RF PAs, PAs are operated in Class-A or Class-AB mode, but Class-A and Class-AB operation modes inherently have lower efficiency than their maximum output power.

According to [15], the efficiency of a Class-A PA decreases with RF output power in proportion to Pout/Pout_max because the DC-current-and-voltage bias is kept constant as the output power varies. Similarly, the efficiency of a Class-B PA varies in proportion to

7 1/2 (Pout/Pout_max) because the DC-current bias varies according to the RF output current and changes in proportion to the square root of the output power. The output-power variation of a Class-AB PA is intermediate between the output-power variation of a

Class-A PA and a Class-B PA as shown in Figure 3.

Figure 3. Variation of efficiency with output power for various amplifier configurations and the output power probability distribution for CDMA signals.

Even if an RF PA has very high output power, the actual probability for the RF PA to operate at this high output-power level is very low. As shown in Figure 3, the most probable output-power level is between -5 dBm and 5 dBm, but the efficiency at this output-power level is only a fraction of the peak efficiency at the maximum output-power level. Therefore, the peak efficiency is not adequate to describe the realistic power transfer of the PA. To derive a more realistic figure-of-merit for the actual operation efficiency of the PA, the efficiency should be averaged over various output power levels,

8 which takes the statistical characteristics of the output power into account. In [16], this average quantity is defined as

* , (6) !> %+* Y 2 Ñ 2V 2 ôJ?   * GI##!M %+* Y 2 Ñ GI##!M 2V 2 where is the long-term average efficiency of the transmitter, is the energy ôJ? !> delivered to the load, and is the energy taken from the supply. GI##!M In code-division-multiple-access (CDMA) systems an active power control with a system-level-feedback loop exists between a mobile terminal and a base station. The RF output-power level of the portable transmitter is adjusted to accommodate the time- varying distance between the portable device and the base station, to limit the interference effects, and to extend the battery lifetime. This is known as near-far effect, which is a decrease of signal-to-noise ratio in the system when any user broadcasts with unnecessary power [17]. In conventional wireless LAN applications such as 802.11a/b/g, the range of power control is very small or does not exist, but future WLAN systems like

802.11n are expected to have more sophisticated power control to enhance the signal quality and to improve the efficiency.

The large peak-to-average ratio of a transmitted RF signal also acts as a limiting factor to the efficiency of an RF PA. To increase the data rates in many advanced wireless systems, the RF signal carrying information is modulated with both a frequency and an amplitude. For example, frequency-division-multiplexing systems employing either multiple carriers or single-side-band signals, and digitally modulated systems like

9 quadrature-amplitude-modulation (QAM) have highly time-varying envelopes, so they exhibit a large PAR value [18]. The PAR measure is defined as

$ , (7) WS0- [cW^ 5 ,  -  - $ ,bW^SYW- [cW^  -

where is the amplitude of the carrier signal and is the root-mean-square (RMS) of 5  the output voltage. An amplitude-modulated RF signal in a time domain is illustrated in

Figure 4.

Figure 4. Illustration of an amplitude-modulated waveform in a time domain.

As the PAR value is increased, the power amplifier operates at a lower efficiency because the voltage difference between the peak and the average of the output signal gets larger. At the valley of the envelope signal, the output power is in a backoff region. This type of power backoff is different from the power control between a base station and a mobile terminal because the power backoff from a large PAR value happens at a much

10 higher frequency. This high frequency power variation requires faster adjustment to optimize the performance of the transmitter.

3 Long Short 2.5

2

1.5

Probability(%) 1

0.5

0 -25 -15 -5 5 15 25 Power (dBm)

Figure 5. Output power distribution for CDMA modulation under short and long time variations.

As shown in Figure 5, the probability of RF envelope power is distributed over a wide range in a time scale for both short and long time variation, and the occurrence of these variations are independent of each other. Considering system level circumstances, PAs may operate at moderate to greatly reduced power levels, and the average carrier voltage can be further driven below the supply voltage. Therefore, the efficiency and linearity of

RF PAs need to be considered over a broad range of the output power level [15, 19].

11

Figure 6. Schematic of a typical linear regulator.

2.2 Limiting Factors in a Static Power Supply

2.2.1 Linear Regulators

A linear regulator uses a feedback control of sensing the resistive voltage drop to regulate the output voltage as shown in Figure 6. The power loss in the linear regulator mainly comes from the voltage drop across the resistive element in the pass transistor.

The maximum efficiency of a linear regulator is defined as

η , (8) IH72> IH  9 IH72> - 00 . IH 0 72> 00

where is the output voltage and is the supply voltage [20]. IH 00 With regard to the efficiency of a PA that is transmitting an amplitude-modulated RF signal, using a linear regulator is no better than using a fixed DC voltage source because

12 the efficiency is significantly reduced in either case because of the large voltage drop at the valley of the envelope signal. However, a linear regulator does not consume a large die area because of its design simplicity, and the closed-loop transient response of a linear regulator is very fast. Therefore, if the primary concern in a dynamic supply design is not the efficiency but the bandwidth of the dynamic supply, then a linear regulator may provide a simple and low cost solution to adaptively modulate the drain voltage of the PA.

2.2.2 Switching Regulators

Switching regulators are favored for portable applications because of their high efficiency and large power handling capability, but the primary design limitations in the switching converter are switching noise, large electromagnetic interference (EMI) emission, and a large size due to the use of external components. Switching regulators can achieve a higher efficiency than linear regulators because they use only switching devices and energy storage elements (all of which are ideally lossless) to converter and filter voltages. A typical step-down switching converter is shown in Figure 7.

In the feed-back loop, a switching regulator usually has an analog or digital control block that determines the switching timing for proper regulation of the output voltage.

Although the theoretical maximum efficiency of a switching regulator is closed to 100%, the actual efficiency is degraded by its conduction loss and switching loss.

Many conventional switching regulators with a fixed switching frequency inherently generate switching noise of which the spectral components are mostly confined at the fundamental switching frequency and its harmonics [2]. This confined spectral energy of

13 the switching noise appears as high-level spurs at the output of the switching regulators, and the spectral shape and the peak of the switching noise are determined depending on the modulation scheme used in the switching regulator. If a switching regulator is used to supply power to an RF PA, these large spurs will be mixed with the RF input signal in the

PA. From this frequency mixing, a large spurious noise is generated, and it can cause a failure for spectral emission specifications [21]. Therefore, to use a switching regulator with an RF PA, its switching noise must be controlled and minimized so as not to deteriorate the performance of the RF transmitter.

Figure 7. Schematic of a typical step-down switching regulator.

In some case, a large LC-filter does not filter out enough switching noise so that even a higher order LC-filter with more external components or surface mount devices inside of multi-layer laminates are used to enhance the filtering, but the number and the size of external components should be minimized for less overall system size and cost [6, 22, 23].

14 For a switching regulator to be used as a dynamic power supply for RF PAs, fast transient response with an wide closed-loop bandwidth is the key factor to modulate the supply voltage. Generally, the bandwidth and the transient response are proportional to the switching frequency, but increasing the switching frequency inevitably increases the switching loss and degrades the efficiency. On the other hand, a high switching frequency can reduce the size of the external filter components, but having a too small inductor can increase the peak-to-peak value of the inductor current and the power-stage RMS current.

Design optimization is very critical in switching regulator design because all the design parameters are in trade-off relationship to each other.

2.3 Efficiency Improvement Techniques for Linear

Transmitters

2.3.1 Adaptive Gate-Bias Voltage Control

Adaptively controlling the gate-bias voltage corresponding to the envelope of the input RF signal is proposed to enhance the efficiency in a Class-A PA [18]. While maintaining the drain-bias voltage, lowering the gate-bias voltage at the valley of the envelope reduces the drain-bias current, and the power added efficiency (PAE) can be improved by reducing the power drawn from the supply. However, a nearly constant gain over a wide range of the gate-bias voltage is required to maintain the linearity, and this characteristic requires the use of specially shaped channel-doping profiles. While adjusting the DC current can reduce the power drawn from the power supply, the

15 fundamental limit of this proposed technique is that the efficiency still falls off when the carrier amplitude is decreased under the supply voltage as long as the drain-bias voltage is kept constant. The linear relationship between the gate-bias voltage and the drain-bias current is heavily dependent on the specially shaped channel-doping profile, too.

Figure 8. Simplified PA model with adaptive gate biasing control.

2.3.2 Envelope-Tracking Systems

In an envelope-tracking (ET) system, the supply voltage of a saturated PA is adjusted to track the envelope of the amplitude modulated RF input signal. This reduces the power loss from the voltage drop between the supply and the drain, and the saturated PA can achieve a higher efficiency. The more accurately the ET system tracks the envelope of the input RF signal, the higher efficiency the system can achieve. Therefore, fast transient

16 response with a wide closed-loop bandwidth is a critical design aspect for such a dynamic power supply in the ET system. Figure 9 shows an example for a typical ET system.

It was described in [7] that a step-down switching converter with 16 MHz switching frequency, 85 % instantaneous efficiency at 1.25 V output voltage, and 95 mA load current could track an 2 MHz envelope. Sliding–mode hysteric control scheme with large off-chip components for frequency compensation was used, but the average efficiency was not reported.

Figure 9. Schematic of a typical envelope tracking system.

An ET system for WLAN 802.11g was designed with the combination of a switching regulator and a linear regulator in [8]. The total drain efficiency of the transmitter was claimed to be 30 % with the supply modulator of which the efficiency was 50 – 60 %.

An ET system for a CDMA transmitter was proposed in [15]. The supply voltage to a gallium-arsenide (GaAs) metal-semiconductor-field-effect-transistor (MESFET) PA was

17 dynamically varied by tracking the envelope of the carrier signal, and the average efficiency was reported to be increased from 3.89 % to 6.38 %.

2.3.3 Average Power Tracking System

Average power tracking system tracks the average transmitted power. Average power tracking can substantially enhance the average efficiency when the power-control range of the system is wide and the peak-to-average power ratio is low. In [9], the proposed power supply was designed to track the long-term RMS value of a CDMA signal envelope, and it was claimed that the average efficiency was increased from 2.2 % to

11 %.

An average power tracking buck-boost converter for CDMA application was proposed in [10]. The buck-boost converter could adjust output voltage between 0.5 V to

3.6 V from a 3.0 V supply, and the bandwidth of the system was approximately 2 kHz.

The average efficiency of the system was claimed to be increased from 1.53 % to 6.78 %.

An asynchronous nonlinear power-tracking supply was proposed in [24]. The power supply was comprised of a low-power but fast-responding voltage regulator and a nonlinear clamping circuit in parallel. Systematic simulation showed that, with a silicon- germanium (SiGe) hetero-junction bipolar transistor (HBT) Class-A PA, the proposed system consumed 10 - 15 % less power and achieved 1.5 % better overall efficiency with the same error-vector-magnitude (EVM) performance for 802.11g signal.

18 2.3.4 Envelope Elimination and Restoration and Polar Modulation

F. H. Raab in [4] proposed the use of the envelope elimination and restoration (EER) system that was proposed by L. R. Kahn in [3]. EER system is based on the idea that the amplitude modulation of a nonlinear PA can be done by modulating the supply voltage of the PA. In the EER system, as shown in Figure 10 (a), the amplitude information of the input RF signal is extracted by an envelope detector, and a hard limiter eliminates the amplitude information and transfers only the phase information of the input RF signal.

The amplitude and phase information of the input RF signal are separated, and the data is encoded in a polar form.

The input RF signal can be described by the base-band components, in-phase I(t) and quadrature Q(t), as

. (9) 8;  7` Ñ U[_Ă=` - ` Ñ _BZ-Ă=` The input signal can also be presented in a polar coordinate as

(10) 8;  ,` Ñ U[_-Ă=` - ` where the RF signal’s amplitude A(t) and phase PM(t) are

(11) $ $ ,`  E7` - ` and

. (12) +# 7`

`  `SZ   `

19 The amplitude and the phase information of the input RF signal are calculated from

(11) and (12) using a cartesian-to-polar converter in a base-band digital-signal-processing

(DSP) unit [2, 25, 26].

As shown in Figure 10 (b), a base-band DSP unit calculates the amplitude and the phase information in a digital domain, and then the amplitude and the phase information are independently converted to analog signals through a digital-to-analog converter (DAC) without using a coupler or a hard-limiter. By eliminating those elements in the signal path, the stringent requirements for the linearity of the envelope detector and the distortion level of the limiter could be circumvented.

(a)

(b)

Figure 10. Schematic of (a) an envelope elimination and restoration (EER) system and (b) a polar modulation transmitter.

20 2.3.5 Various Topologies for a Dynamic Supply Modulator

Multiple switching and/or linear regulators are often cascaded in series or connected in parallel to form a single power supply of which the performance is enhanced over a single switching or linear regulator [27]. For example, an interleaved parallel–connected voltage regulator was proposed in [28] for faster transient response and higher power density. To control the parallel-connected converters, a current-sharing technique was used so that the output load currents from multiple switching regulators are balanced.

However, if the output of the regulator is modulated at the frequency bandwidth of the envelope of the input RF signal, this interleaved parallel-connection topology can hardly balance its output currents so that it would be hard to secure enough phase margin for stable operation.

A parallel-connected switching converter that was composed of a linear regulator

(National Semiconductor LMH6639 Op-Amp) and a buck switching converter (Fairchild

Semiconductor FDV302P digital FET for the p-MOSFET switch and a Zetex ZLLS400

Schottky diode) was proposed in [29] to be used as a supply modulator in an EER system for WLAN 802.11g application. The proposed supply modulator used a hysteretic current-feedback control scheme with a current-sensing resistor, but the power dissipation across this current-sensing resistor degraded the efficiency of the supply modulator. It was claimed that the supply modulator could operate at 20MHz bandwidth with 60% average efficiency.

21 Table 2. Comparison of published envelope amplifiers

Efficiency Envelope Amp Application Signal Bandwidth (RF PA not included) 1 MHz 65 – 74 % (Peak) [15] Envelope Tracking CDMA 2 MHz 88 % (Peak) [6] Hybrid EER EDGE - 89 % (Peak) [11] EER EDGE 1.23 MHz 85 % (Peak) [7] Envelope Tracking CDMA 10 MHz 82 % (Peak) [30] Hybrid EER CDMA 20 MHz 60 % (Average) [8] Hybrid EER WLAN OFDM

2.4 Conclusion

While there have been many design examples for a dynamic supply modulator in the literature, an RF transmitter with one simple linearization technique is unlikely to meet all the requirements for near-future mobile terminals. It is very challenging simultaneously achieving a high efficiency for longer battery lifetime and multi-mode operation for a high spectral efficiency. It is important to generalize all the requirements for a dynamic supply modulator as the envelope bandwidth of the carrier signal approaches above tens of MHz for such as WCDMA/HSDPA and 802.11a/g/n standards.

To obtain all the benefits that would accrue from supply modulation, a supply modulator itself must be very highly efficient and do not add any noise to the original amplitude signal.

22 Chapter 3

Designing Synchronous Step-down Converter in

Voltage-mode PWM Control

3.1 Pulse Width Modulation (PWM) in Voltage Mode Control

Figure 11 shows a typical voltage-mode PWM controlled, step-down DC-to-DC converter. The error-amplifier and PWM functions are contained in PWM control block as shown in Figure 11. The PWM control block provide many other functions, but for understanding the stability problem in the negative feedback loop, only the error amplifier and pulse-width modulator need to be considered [31].

Figure 11. Voltage-mode PWM controlled, step-down DC-to-DC converter.

23 Any variation of the output voltage due to either line-input or load changes should be sensed by the inverting input of the error amplifier via the feedback network and compared to the Vramp input. This will generate an error signal at the output of the error amplifier, and the level of this error signal determines the duty ratio of the rectangular pulse. The width of the rectangular pulse is equal to the time from the start of the triangle t0 to t1, where t1 is the time the triangle crosses the error signal. This pulse width determines the on-time (ton) of the power transistor.

During the period ton, the switches are turned on, and the input voltage, Vbat, is applied across the inductor L. During the period toff, the switches are turned off, and the stored energy in the inductor is transferred to the output. The duty ratio (D) can be defined as

, (13)   G-  -- --  --  - @@ HH!

where Ttotal is the switching time period of the DC-to-DC converter. By changing the ratio between ton and toff, the rate of the energy transfer over a finite time period of Ttotal can be adjusted. As the duty ratio is increased, more energy is transferred to the output, and therefore the output voltage will be increased.

Figure 13 shows the voltage and current waveforms of a voltage-mode PWM controlled DC-to-DC converter in a continuous-conduction mode. The intermediate node between PMOS and NMOS is switched between PVDD and ground as PMOS and

NMOS switch. To prevent the shoot-through current from PVDD to ground, PMOS and

24 NMOS should never be turned on at the same time. PMOS should be turned off before

NMOS is fully turned on, and NMOS should also be turned off before PMOS is fully turned on. By introducing a proper time delay in the gate driving signals at PMOS and

NMOS switches, which is known as dead-time, unnecessary power loss could be prevented.

Since the inductor current cannot instantaneously go to zero, during the dead-time, body diodes in the switches provide alternative current paths. Maintaining low voltage drop across the body diodes and the parasitic resistance is important to prevent excessive power loss during the dead-time.

If a triple-well CMOS process is available, then a deep n-well layer could be used as a barrier to prevent noise injection from the body to the substrate. As shown in Figure 12, the deep n-well, p-well, and p-sub form a back-to-back diodes. As long as the deep n-well contact is tied to an equal or higher potential than the body and the substrate, the diodes are reverse biased and no current can flow through.

(a)

(b) Figure 12. Cross-sectional view of a NMOS transistor (a) in a standard CMOS process (b) in a triple-well CMOS process with a deep n-well layer.

25

Figure 13. Voltage and current waveforms of a voltage-mode PWM controlled, step- down DC-to-DC converter.

26 3.1.1 Steady-State Analysis and Small Signal Model

One end of the inductor is connected to PVDD over a period of ton, and the other end of the inductor is connected to the output voltage over a period of toff. Under steady-state operating condition, the inductor can be treated as a short circuit. Therefore, the average voltages of each end of the inductor are equal. This relationship can be expressed as

, (13) GG- Ñ ˮKL -  -[a`- Ñ ˮNKNOP

, (14) GG- Ñ G- Ñ-ˮNKNOP -  -[a`- Ñ ˮNKNOP

, (15) [a`-  - GG- Ñ G

where D is the duty ratio. From (15) the output voltage has a linear relationship with the duty ratio.

Basic voltage-mode PWM controlled DC-to-DC converter circuits are relatively simple and consist of a few power components, and a feedback control loop is required to regulate the output voltage and/or current. Although a switching converter is a non-linear and time-varying system because of modulators and switches in the system, the small signal transfer function concept can still be used to analyze the control loop.

A step-down DC-to-DC converter with PWM control can be modeled as a second- order system, and this simplification allows us to predict the frequency domain and time domain performance. LC-filter at the output of the voltage-mode converters contributes -

180º degree of phase shift at its resonant frequency, and, because of the double poles at the resonance frequency of the LC-filter, the converters are inherently unstable without

27 the presence of phase boost at this frequency. Figure 14 shows a typical diagram for a voltage-mode PWM controlled, step-down DC-to-DC converter. To analyze the small signal transfer function of the overall system, the control loop of the converter can be divided into three major sections, and those are output LC-filter, error amplifier with a loop filter, and PWM control block. A type-III loop filter can be implemented around the error amplifier and provides the required phase boost.

Figure 14. Diagram for a voltage-mode PWM controlled, step-down DC-to-DC converter.

The transfer function from the output of the error amplifier to the Vout can be expressed as

28

. (13) ˢR˯ˮT TS` ŵ - T Ñ ˞U Ñ ˕ -  -- Ñ-Y ] T Ñ \ $ ˢUT \cX ŵ - - T Ñ \ Ñ ˕ ˞

Vpwm : peak-to-peak voltage of PWM triangular wave L : Output filter inductor C : Output filter capacitor Rc : Output filter capacitor’s ESR R : Output load

The first part of the transfer function is defined by the PWM modulation block, and the second part is defined by the external LC output filter and the output load.

Figure 15 shows three different types of the loop filter design for phase boosting.

Type-I filter is a simple integrator type. R1/Rbias can be changed to set a desired DC response. Type-II filter has one zero and one pole, and the maximum phase boosting is

90º degree. Type-III filter has two zeros and two poles, and the maximum phase boosting is 180º degree.

Figure 16 shows a type-III loop filter and its transfer function. To have a desired DC response, Rbias can be added, and DC-gain can be defined such that VSET sets the voltage across Rbias from VIN because there is no DC path in Z2 network. By placing

Rbias, DC-response can be defined without adding a separate resistor divider.

29 Type-I Type-II Type-III

Figure 15. Different types of loop filter for phase boosting.

sVout )( + + + CRRsCsR ]3)31(1)[121( = sVin )( ++ + + CCCCsRCsRCCsR )]21/21(21)[331)(21(1

(a) 1 1 1 fp1 1 fpo CCR )21(2 CCR )21(12 2 CR 222 fp2 CC 21 CR 332 Pole at origin Pole #1 Pole #2

1 1 1 fz1 fz2 CR 122 3)31(2 CRCRR 312

Zero #1 Zero #2 (b)

Figure 16. (a) Type-III loop filter and its Transfer function (b) frequency locations of poles and zeros for type-III Loop Filter.

30 Figure 17 shows the frequency response of a type-III loop filter that has double pole and zero pairs. By placing a zero pair before the unity gain frequency, the phase is boosted to achieve more phase margin. In Figure 17, two poles and zeros are located in pair, but in fact each pole and zero can be located in different frequency. However, by placing poles and zeros as a pair, the frequency range where the phase is boosted can be defined in respect to the distance between the pole and zero pairs with placing the desired unity gain frequency at the center.

This phase boosting is very desirable because the dynamic response of the overall control loop can be improved with increasing the unity gain frequency. However, the finite unity gain bandwidth product (UGBW) limits the overall frequency response.

100 100 90 80 70 Phase Boost 60 50 40 30 20 10 fp0 0 10 20 Mag LFMag( fi )() 30 40 fz1=fz2 fp1=fp2 Ph LF( fi )() 50 60 Phase 70 80 90 100 110 120 130 140 150 160 − 180 170 180 3 4 5 6 7 8 9 1 10 100 1 .10 1 .10 1 .10 1 .10 1 .10 1 .10 1 .10 0 9 1⋅ 10 freqfi 1⋅ 10

Figure 17. Frequency response of a type-III loop filter.

31 3.1.2 Transient Response

It takes finite time for a DC-to-DC converter to adjust its output voltage from one level to another level with the change in the input reference voltage. Within the slew-rate limitation, the closed-loop bandwidth of the DC-to-DC converter determines how fast the output voltage would track the reference input level with a finite closed-loop gain.

However, if the DC-to-DC converter operates beyond a slew rate limitation, the operating points of many transistors in the control loop fall into triode region or deep triode region.

Therefore, the transient response of the converter is no longer determined by the small signal transfer function, but the large signal response.

The bandwidth of the closed-loop transfer function of a DC-to-DC converter is inherently limited by the resonant frequency of the output LC-filter, where the resonant frequency is defined as 1/ . Because the output LC-filter has double poles at the ^\˕ resonant frequency, the gain falls in -40 dB/decade and the phase is shifted by 180 degree.

To achieve a certain phase margin in the overall closed-loop transient response, the phase must be boosted around the resonant frequency to compensate this 180 degree phase shift.

Therefore, the unity gain frequency of the overall closed-loop response cannot be much higher than the resonant frequency of the output LC-filter. To increase the bandwidth, the resonant frequency must be moved to a higher frequency.

However, as the resonant frequency of the output LC-filter moves to a higher frequency, the switching ripple at the output is not sufficiently filtered because the gain will decrease in -40 dB/decade only after the resonant frequency. To keep the ripple level the same with a higher resonant frequency, the switching frequency of the converter

32 should be increased since the peak-to-peak voltage of the output ripple of a step-down switch converter is determined as

, (13) ˢcON Ñ ŵ . G Ñ ˖ ˢ_`aaPb - -- $ where e Ñ f Ñ g Ñ ˦

: Input voltage ˢcON L : Output filter inductor C : Output filter capacitor f : Switching frequency D : Duty ratio .

This ripple voltage can be easily derived from Figure 18. Because a faster switching frequency will increase the switching loss of the converter, the overall efficiency will be degraded as the switching frequency is increased.

33

VV )( ⋅− DT I =∆ sbat L L

1 V ∆⋅= Q ripple C C

2 )( ⋅− DVVT Q =∆ sb at C 8L

Figure 18. Ripple voltage with a finite capacitance at the output LC-filter.

34 3.2 Selection of Power Inductor and Load Capacitor

In switching converter design, a power inductor and a load capacitor play very important roles. The inductor will be placed between the input voltage and the output voltage, therefore, for a given output voltage, the inductor determines how the output current changes with time. The energy is drawn from the source and stored in the inductor during a portion of the switching period, and the stored energy is dumped into the load capacitor during the rest of the switching period assuming a constant switching period.

The law of inductance says that it is not possible to instantly break the current flowing in an inductor because an infinite voltage would be required to make it happen.

This principle is what causes the arcing across the contacts used in switches that are in circuits with highly inductive loads. The law of capacitor says that the voltage across a capacitor cannot be instantaneously changed because it requires an infinite current flowing into or out of the capacitor.

However, the actual inductance is not always the same, but it varies with a frequency and an inductor current. When the input supply voltage and load current are varied very widely, the actual inductance must be always maintained in a limited range to avoid unexpected malfunctioning. For example, since the inductor current slope is defined by the voltage across the inductor and the inductance, if the inductance becomes very low in a high frequency range, the inductor current slope will become much higher than the nominal value when the same voltage is applied across the inductor. This larger current ripple will degrade the overall efficiency and generate excessive heat, and it can damage the PMOS and NMOS switches.

35 The current ripple from the inductor will charge or discharge the load capacitor, and this AC current will generate additional voltage ripples across the equivalent series resistance (ESR) of the capacitor. These ripples are not in phase with the inductor current ripples, but it will increase the peak-to-peak value of the overall ripples.

3.3 Circuit Topology and Operation

This section discusses the circuit design of a fully integrated prototype of the proposed synchronous buck converter in 0.18-µm CMOS process. Fundamental design consideration in synchronous buck converter in voltage mode control is discussed, and this prototype buck converter design is implemented as a basic building block for the proposed switching converters that will be discussed in the following chapters.

3.3.1 Dead-time Control

Transitions of the gate-driving signals at the PMOS/NMOS switching transistors need to be controlled to prevent a shoot-through current because this shoot-through current can cause excessive power loss. Time delays are inserted between the gate voltage transition of the PMOS/NMOS to prevent shorting between the supply and the ground. Figure 19 shows a simple logic circuit for dead-time control.

A SR-latch is used to characterize the switch signal as binary states so that the voltage level of the switch signal can stay only either end of the supply rail. The gate voltages of the PMOS and NMOS are fed back to the logic circuit and used to interpret whether the

PMOS or NMOS transistors are turned on or off.

36 Dead-time control is indispensable to avoid a shoot-through current, nonetheless, the duration of the dead-time needs to be as short as possible since both NMOS and PMOS will be turned off during the dead-time. Because the inductor current cannot stop instantaneously, the body diodes should take over the inductor current from either the

PMOS or NMOS and keep conducting. These body diodes have much higher impedance than the channel resistance of the switch, the conduction time should be minimized.

Figure 19. Dead-time control logic circuit.

3.3.2 Gate Driving Circuit and Power Transistor

The gate driving circuit is essentially a cascaded inverter chain that can charge or discharge the large gate capacitance of the PMOS/NMOS switching transistors. Each stage of the cascaded inverters is sized differently so that the size of a driving stage is smaller than the size of a loading stage. In theory, the optimum multiplication factor to size each stage of the inverter chain is 2.723. However, to balance power consumption, die

37 area, and the propagation delay, the multiplication needs to be much larger than 2.723 for the last stages.

Figure 20 shows the schematic of the power transistors and their gate driving circuits. The multiplication factor of 3 is used for the inverter chain, and the size of the last stage in the inverter chain is about 1/10 of the switching power transistors.

(All dimensions are in µm)

Figure 20. Schematic of the power transistors and their gate driving circuits.

Figure 21 shows the waveforms for the gate voltage at the NMOS and

PMOS switching transistor with the dead-time control circuit. When both

NMOS and PMOS are turned off, the phase node voltage will be dropped

38 below the ground potential because the current has to be drawn from the ground to the output via the body diode.

The power transistor with a gate driving circuit in Figure 20 is used as a unit cell for the power train in the DC-to-DC converter, and multiple of this unit cells can be connected in parallel to have a desired channel resistance in the power transistor.

When either NMOS or PMOS power transistor is turned on, the power transistor will operate in the triode region because the gate-to-source voltage will be the supply voltage and the source-to-drain voltage is very small. The channel resistance of the switch devices in the triode region can be estimated as

ŵ , (13) ˞ijOLLbP -  -- ˣ k Ñ Ñ mˢno . ˢNjp Ñ ˢqo \

where

: Drain-to-source voltage ˢqo : Gate-to-source voltage ˢno : Transconductance parameter

k W : With of the device L : Length of the device : Threshold of the device. ˢNj

However, the real channel resistance is hard to be measured because of the resistance of the metal interconnection and the bond wire, and the Rchannel also depends on temperature and process variation.

39

Phase node

PMOS PMOS

NMOS NMOS

NMOS / PMOS gate

Figure 21. Waveform of the gate voltage in NMOS and PMOS power transistors with dead-time control.

3.3.3 Reference Generation

Accurate reference voltages and bias currents are indispensable for analog control circuits to operate correctly under different supply voltages and temperatures. Bandgap reference circuits are widely used in various analog circuits to generate temperature independent reference voltage. Figure 22 shows an example for a conceptual schematic for a bandgap reference circuit.

40

Figure 22. Conceptual schematic for a bandgap reference circuit.

In Figure 22 the size of Q3 and Q4 are n-times larger than Q1 and Q2 (The reverse saturation current of Q3 and Q4 are n-times larger than Q1 and Q2), then the amplifier will regulate the current mirror output such that VBE1+VBE2 = VBE4+VBE3 + Iref · R1.

Because [VBE1+VBE2 – (VBE4+VBE3)] will be positively proportional to absolute temperature (PTAT), Iref will also be a PTAT current. Iref will have a current value of

VT·ln(n)/R1. By canceling the positive proportionality of the PTAT current with the negative proportionality of , the voltage output Vbg will be independent to rˢstÈ r tempearture change.

If the circuit in Figure 22 is investigated further, it can be seen that the positive input node of the amplifier V1 will be negatively proportional to absolute temperature, and V2 will be positively proportional to absolute temperature. By setting up a threshold for the

41 voltage difference between V1 and V2, an over-temperature warning signal can be triggered when the voltage difference becomes less than the threshould. If the warning signal is used as a shut-down signal to the overal system, an over-temperature shut-down operation could be implemented.

In a standard CMOS process, a floating diode is not usually available. A pn-junction is realized with p-substrate, n-well, and p+ diffusion layers, and p-substrate and n-well are connected to the ground. A lateral pnp-device can also be realized with a parasitic pnp-junction in PMOS transistor in a standard CMOS process. However, this lateral device does not have a good characteristic because the base doping is too light (high resistivity) and base width is limited to the minimum lithographic resolution between two p+ regions.

If BiCMOS process is available, the vertical npn-device could be impelented using an additional deep n-well layer. This vertical npn-device has a better performance than the lateral pnp device because the base width can be thinner by defining it from the difference in the junction depth between n+ region and p-base region.

Figure 23 shows the block diagram of the reference generation circuit. The bandgap circuit generates a temperature independent bandgap voltage and a negatively proportional to absolute temperature (NTAT) voltage. A local voltage regulator uses the bandgap voltage and regulates its output voltage at 3.0 volt. By voltage dividing the regulated voltage with a series of resistors, a 2.5 volt reference voltage for the triangular

PWM ramp generator can be achieved. The voltage regualtor can drive up to 16mA into

5pF load from Vbat of 3.5 volt. By increasing the size of the pass transistor in the local

42 voltage regulator, the drop-out voltage can be further reduced. The reference current generation block is powered by the regulated output voltage at 3.0 volt.

Even though the bandgap voltage is independent of the temperature, as the supply voltage is changed, the operating conditions of a regulation amplifier and current mirrors are changed. Therefore, the reference current or voltage will be vulnerable to the supply voltage change. However, in the proposed reference generation circuit, because the supply voltage of the current generator is independently localized and always regulated in

3.0 volt, the output reference current could be more robust to the supply voltage change.

43

Figure 23. Block diagram of the proposed reference generation circuit.

44 Figure 24 (a) shows the simulated bandgap reference voltage and 3.0 volt regulated voltage output at start-up, and Figure 24 (b) shows the characterisitics of the bandgap reference voltage variation for different temperatures. By setting the maximum point of the bandgap voltage at room temperature, the deviation can be minimized.

(a)

1.1900 bandgap voltage 2.956 1.1895 regulated voltage 2.955 (Volt)Regulated Voltage

1.1890 2.954

1.1885 2.953

2.952 1.1880 2.951 1.1875 2.950 1.1870 2.949

1.1865 2.948 Bandgap Voltage (Volt) Voltage Bandgap 1.1860 2.947 -40 -20 0 20 40 60 80 100 Temperature

Figure 24. Simulated results for (a) start-up of the reference generation circuit (b) characteristics of the bandgap reference voltage and the 3.0 volt regulated voltage output.

45 3.3.4 Error Amplifier Design

The input common-mode range (ICMR) of the error amplifier should be sufficient to cover the required voltage range for the reference input. If a DC-to-DC converter has a voltage gain of A, then the reference input should be varied between Vout(max)/A and

Vout(min)/A. To avoid the input common-mode range (ICMR) limitation in low voltage range, the error amplifier has a PMOS input differential pair, and the output stage has a relatively high current output to drive the output load quickly enough not to degrade the transient response of the control loop. A class-AB output stage is implemented for the error amplifier so that the output stage can quickly source or sink a current from the output without burning too much quiescent current. Figure 25 shows the schematic of the error amplifier.

The error amplifier has an average gain of about 75 dB for ICMR between 0.3 and 2.5 volt. As shown in Figure 26, the gain is degraded as the common-mode input voltage gets lower than 0.3 volt. To maintain high accuracy at the output voltage of the DC-to-DC converter for a desired output dynamic range, the ICMR of the error amplifier needs to be kept higher than 0.3 volt. For a desired DC output dynamic range of 0.6 ~ 3.0 volt, the overall DC voltage gain in the DC-to-DC converter needs to be higher than 2.0.

46

Figure 25. Schematic of the error amplifier.

Table 3. Error amplifier specifications compliance matrix.

Parameters Target Simulation Power Supply 3.5 V– 4.5 V 3.5 V– 4.5 V ICMR 0.3 V – 1.5 V 0.1 V – 2.5 V Output Swing 0.1 V – 3.0 V 0.1 V – 3.3 V UGBW 10 MHz 50 MHz Phase Margin > 45 º > 80 º DC gain > 60 dB > 70 dB Input-Referred Offset < ± 20mV < ± 10mV (Supply voltage = 3.5 volt)

47

Gain Phase

Figure 26. Open-loop gain and phase of the error amplifier when the input common level is varied from 0.1 V to 2.5 V

3.3.5 PWM Comparator

PWM comparator will compare the output of the error amplifier with the triangular ramp signal and generate a series of square pulses that has a controlled duty-ratio. The output voltage of the DC-to-DC converter will depends on this duty-ratio. The ICMR of the PWM comparator needs to cover from the minimum voltage to the maximum voltage of the triangular ramp signal to ensure maximum operational ranges for the duty-ratio because the output dynamic range of the converter itself totally depends upon how much range of variation the duty-ratio can have.

Figure 27 shows the schematic of a comparator with internal hysteresis. Hysteresis in the output transition is desired because of the noisy supply rail in the switching converter.

48 The Internal positive feedback is used to accomplish the hysteresis. In this comparator there exist two paths of feedback. The first is current-series feedback through the common-source node of M1 and M2. This feedback is negative. The second path is the voltage-shunt feedback though the gate-drain connections of M4 and M5. This path is positive. If the positive-feedback factor is less than the negative-feedback factor, then the overall feedback will be negative and no hysteresis will results. If the positive-feedback factor becomes greater, the overall feedback will be positive, which will give rise to hysteresis in the voltage-transfer curve [32].

The positive trip point is yielded when IDS of M1 gets larger than IDS of M5, and the negative trip point is when IDS of M2 becomes larger than IDS of M4. The size ratio between (W/L)M4 and M5 and (W/L)M3 and M6 will determine the size of the hysteresis window. In this design, M4 and M5 are sized 2 times larger than M3 and M6 to accomplish a hysteresis window.

Even though the output of the comparator has very high gain, it needs to be buffered for a fast transient response because the comparator itself has a limited current driving capability. Typically a series of inverters are followed after the comparator to boost the transient response speed.

49

Figure 27. Schematic of a high-gain, open-loop comparator with internal positive feedback for hysteresis transfer curve.

Table 4. PWM comparator specifications compliance matrix.

Parameters Target Simulation Power Supply 3.5 V– 4.5 V 3.5 V– 4.5 V ICMR 0.1 V – 2.0 V 0.01 V – 2.1 V Load Capacitance n/a 10 fF ±50% Propagation Delay < 10 nSec < 5 nSec Hysteresis Window 100mV 100 mV Input Offset < ± 20mV < ± 10mV (Supply voltage = 3.5 volt)

50

(a)

DC sweep condition : POS volt is varied between 0.5 volt to 1.5 volt, and NEG volt is fixed at 1.0 volt (b)

Figure 28. (a) Comparator transfer curve and transient response to a noisy input (b) simulated comparator transfer curve indicating trip points with hysteresis.

51 3.3.6 Adjustable Triangular Ramp Signal Generator

Figure 29 shows the complete schematic of the triangular ramp signal genrator.

The reference genration block provides a 2.5 volt reference voltage and a reference current of 50uA to the triangular ramp signal genrator.

The Vhigh and Vlow will determine the upper limit and lower limit of the triangular wave signal. To accomplish Vhigh and Vlow, the 2.5 volt reference voltage is divided across R5, R6, and R7. In case 2.5 volt is not adequate to accomplish desired Vhigh and

Vlow, an external refrence voltage (Vref) can be used. An analog MUX is used to select a prefered reference input.

If ‘select’ = 0, then the internal 2.5 volt is connected, or if ‘select’ = 1, then the external Vref is connected. Because the internal 2.5 volt reference is supplied from the voltage regulation circuit in the reference generation block, R5, R6, and R7 should be large enough not to load the voltage regulation circuit too much.

The 50uA reference current from the reference generation block can be adjusted based on the 5-bits input of S<5:1>. The output current Iref will be 50uA

·(1·S1+1/4·S2+1/2·S3+1/2·S4+1/4·S5). As a default value, S1, S2, and S3 are equal to 1, and all other bits are 0, and the frequency of the triangular ramp signal is 2MHz. The schematic of the current multiplier is shown in Figure 30.

Because C·di/dt = Vc, the charging and discharging time of the load capacitor is linearly proportional to the reference current input. By changing S<5:1> bits the current output can be varied by maximum ±42% from the default 2MHz. Table 6 summaries the amount of frequency changes. The amplitude and the period of the triangular wave can be adjusted by varying Vref and S<5:1> bits.

52

Figure 29. Complete schematic of the triangular ramp signal generator.

Figure 30. Schematic of the current multiplier.

53

Table 5. Frequency changes in the frequency of the triangular ramp signal.

Bit Frequency Simulated Note S1 S2 S3 S4 S5 Change Frequency Default 1 1 1 0 0 0 % 2 MHz Value

1 1 1 1 0 28 % 2.28 MHz Positive 1 1 1 0 1 14 % 2.56 MHz deviation 1 1 1 1 1 42 % 2.84 MHz

1 0 1 0 0 -14% 1.72 MHz Negative 1 1 0 0 0 -28% 1.44 MHz deviation 1 0 0 0 0 -42% 1.16 MHz

54 Chapter 4

Switching-Frequency Modulation for Spurious-noise

Reduction in a DC-to-DC Converter for RF Power

Amplifier

To make an efficient supply modulator, a switching converter is favored because of its high efficiency and versatility. However, a switching converter inevitably generates large switching noise to its output, and such large switching noise can degrade the fidelity of the original amplitude information. Therefore, the feasibility of the extending the simple idea of spread-spectrum effect into circuit implementation is investigated to reduce the spurious noise peak.

It is very difficult to design a switching converter with fast transient response because of the large second-order LC-filter that has low-frequency poles for noise filtering.

Effectively increasing the bandwidth of the switching converter without degrading the efficiency is researched. A dual switching converter that is composed of a small DC-to-

DC converter with a high switching frequency and a large DC-to-DC converter with a low switching frequency will be proposed. To realize such a dual converter, the average inductor current of the fast converter needs to be sensed to control the output current of the slow converter. The feasibility of such an average inductor-current-sensing circuit is verified, and the more detailed explanation about implementing the dual switching converter will be followed in the following chapters.

55 4.1 Overview

As a consequence of the increasing data rate and the limited wireless frequency bands, wireless transmitters utilize various linear modulation schemes. A linear transmitter often requires a linear RF PA because both phase and amplitude modulation are used to transmit a signal. In a wireless transmitter, a PA consumes the largest portion of the overall power, so maintaining the efficiency of the PA high throughout all the operating points is very critical.

To overcome the low operating efficiency of a linear PA at backoff power, a switching power supply is widely used because of its higher efficiency over a conventional linear regulator [22]. Pulse-width modulation (PWM) with a constant frequency ramp signal makes it easy to predict where the switching noise would appear in a frequency domain. Therefore, PWM control is widely used as a control scheme for DC- to-DC converters that are used to supply power to an RF PA.

However, the conventional PWM control scheme with a constant frequency ramp signal inherently generates switching noise of which the spectral components are mostly confined in the fundamental switching frequency and its harmonics [2]. This confined spectral energy of the switching noise creates high-level spurs in the output of the DC-to-

DC converter.

These large spurs will be mixed with the input RF signal in the PA. From this frequency mixing, a large spurious noise is generated, and it can cause a failure for the spectral emission specification [21]. Therefore, to use a DC-to-DC converter with a PA, its switching noise must be minimized so as not to deteriorate the performance of the RF transmitter.

56 In some cases, a large LC-filter does not filter enough switching noise so that even a higher order LC-filter with more external components or surface-mount devices inside of a multi-layered laminate are used to enhance the filtering, but the number and the size of the external components in use should be minimized for less overall system size and cost

[6, 22, 23].

This chapter presents a frequency-modulation technique to reduce and broaden the frequency components of the switching noise in a step-down DC-to-DC converter. In

Figure 31, a conceptual block diagram of a step-down DC-to-DC converter with a PWM ramp signal modulator is illustrated. By modulating the frequency of the triangular PWM ramp signal of which the frequency is controlled by the proposed digital PWM ramp signal modulator, the spurious noise can be effectively spread over a wider frequency range, and the peak of the spurious noise can be reduced.

To minimize the imbalance of the inductor current at the output LC-filter due to varying switching frequency, small frequency steps are used, and the oscillator is designed to generate a triangular PWM ramp signal that has an equal rise and fall time in each period throughout the switch frequency modulation.

In 4.2, it is mathematically analyzed how to calculate the spectral energy of switching noise when monotonic switching-frequency stepping is applied to the PWM ramp signal of the DC-to-DC converter. Circuit implementation of a step-down DC-to-DC converter with the proposed digital PWM ramp signal modulator is described in 4.3. Experimental results are shown in 4.3.

57

Figure 31. Spectrum spreading effect in the switching noise spurs at the output of a switching power supply from the proposed PWM ramp signal modulation.

4.2 Analysis

A modern wireless communication system is highly affected by deterministic interferences such as periodic switching noise. Therefore, if the peak energy-density spectrum of switching noise could be spread over a wider frequency range with a lower peak value, then the noise would consist of less deterministic frequency components [22].

58 From Parseval’s theorem, the energy-density spectrum of a discrete signal that determines how the energy is distributed in the frequency domain can be found. The total energy contained in a signal, summed across a period, is equal to the total energy of the signals’ Fourier transform, summed for all of its frequency components.

Common PWM schemes use a periodic triangular or saw-shaped signal with a fixed frequency to control the output voltage of a DC-to-DC converter. Repetitive switching at a fixed frequency generates a large switching noise of which all the energy–density spectrum is confined within the fundamental switching frequency and its harmonics.

With monotonic switching-frequency stepping, the switching period is increased or decreased between Tmin and Tmax with a time step of ∆T. If there are N steps between Tmin and Tmax, the integration over Ttotal (Ttotal = Tmin + (Tmin + ∆T) + (Tmin + 2·∆T) + ··· + (Tmin

+ N·∆T) + Tmax + (Tmin + N·∆T) + (Tmin + (N-1)·∆T) + ··· + (Tmin + ∆T)) can be divided into 2N+2 parts. Any switching period between Tmin and Tmax can be generalized with an index, K, by using Trise,k and Tfall,k, and the fact that the periodic square-wave signal has only two states, zero or Vbat, as shown in Figure 32.

The Fourier series coefficient in the square wave can be simplified and calculated as

:D€E‚ƒ= $4‰# , (13) <H +$D{ Z v  x y W | F `-V` HH! HH!  E(" : 9>>ƒ= 

which presents the spectral energy of the switching noise in a frequency domain.

59 DC-DC converter is in steady-state

VHI

VERR Signal PWM Ramp Ramp PWM

VLO 0 Tmin TMin+∆T TMin+2∆T TMin+k∆TTMax = TMin+(N+1)∆T TMin+∆T Tmin Ttotal

Trise,k Tfall,k Trise,N+1 Tfall,N+1 Vbat Output Comparator Comparator

0 n=0 n=1 n=2 n=k n=N+1 n=2N+1 Duty-ratio is constant

Figure 32. Pulse-width-modulated square wave output from a linearly modulated triangular PWM ramp signal.

Using (13), the spectral switching noise power is calculated with a different number of frequency steps and a different set of Tmin and Tmax assuming Vbat = 3.6 V, duty cycle = 0.5, L = 2.2 µH, C = 1.0 µF, and Load = 5 Ω.

Figure 33 shows that, as the number of switching step, which is N in (1), is doubled, the spurious switching noise peak is decreased by 20·log(2) ≈ 6 dB. Increasing the range of the switching-frequency modulation also reduces the peak of noise spur, but these results are based on the assumption that all the LC components at the output filter and the switches are ideal, and the imbalance of the inductor current due to the time-varying switching frequency is not considered.

60

-35 Tmin=2.4MHz / Tmax=3.0MHz -40 Tmin=2.4MHz / Tmax=4.8MHz -45 -50 -55 -60

-65 -70 -75 -80 -85 Spurious Spurious Switching Noise Peak[dBm] 20 21 22 23 24 25 26 27 Number of Frequency Steps

Figure 33. Calculated spurious noise peak for different number of frequency steps and for different frequency ranges.

If the switching period is increased by ∆T in every one cycle until it gets to Tmax, assuming the duty cycle is constant at d1, turn-on time is increased by in the next V # Ñ Œ cycle, but turn-off time is increased by in the next cycle. When , ŵ . V# ь V #  ŴŽŶŹ the mismatch between the turn-on time and the turn-off time in the next cycle is . ŴŽŹ Ñ Œ Figure 33 illustrates the time mismatch between turn-on time and turn-off time when triangular PWM ramp signal is modulated.

Even though the timing mismatch is resolved as the switching period is decreased from Tmax to Tmin, the cumulated imbalance of the inductor current can go over the tolerance limit when is too large. Therefore, the size of the frequency step and the Πrange of frequency stepping should be carefully chosen to avoid a device failure and undesired transient and frequency components [33].

61

DC-DC converter is in steady-state

+(∆T·d) +(∆T·d)

Time mismatch between on-time and off-time = ∆T·(2d-1)

+∆T·(1-d) +∆T·(1-d)

Duty-ratio is constant

Figure 34. Time mismatch between on-time and off-time in linearly modulated PWM signal.

4.3 Achieving Spread Spectrum

To modulate the frequency of the triangular PWM ramp signal, an up/down counter , pseudo-random sequence generator, and a current-steering DAC are implemented. The up/down counter is designed to monotonically increase or decrease its output bits between the minimum and the maximum in every input clock cycle. A linear feedback shift register (LFSR) is implemented to generate a pseudo random sequence of bits.

The output of the up/down counter and the random sequence generator will steer the current output of the DAC. Each bit of the DAC is weighted differently from the least

62 significant bit to the most significant bit to increase the actual resolution of the current output. Figure 35 shows the conceptual diagram of the proposed PWM ramp signal modulated switching converter.

Figure 35. Conceptual diagram of the DC-to-DC converter with the switching frequency modulator.

In Figure 36, the output current of DAC, IDAC, is combined with a DC bias current and generates a modulated current, Imod. The level of Imod determines the charging time and the discharging time at the load capacitor in the digital PWM ramp signal modulator.

63

Figure 36. Block diagram of the digital current modulator.

For PWM control, a triangular signal or a saw-shaped signal are commonly used, but to keep the inductor current under control and preserve the duty-cycle constant throughout the switching frequency modulation, triangular PWM ramp signal should be always shaped to have the same rise and fall time. If the PWM ramp signal is saw-shaped,

64 then the mismatch between turn-on time and turn-off time cannot be resolved as described in 4.2.

The digital PWM ramp-signal modulator changes the charging and discharging time by the same amount because the top and bottom current mirrors are referencing the same current, Imod. By utilizing the digital PWM ramp-signal modulator, the switching frequency is modulated without severely disturbing the inductor current at the LC-filter, but this scheme still has a low frequency pattern. These low frequency components could be appeared at the switching noise spectrum. Randomizing the modulation of the switching frequency can eliminate this low frequency noise [34]. In Figure 37 the current steering DAC and the ramp signal modulator are illustrated.

However, when the frequency of the PWM ramp signal is changed in a true random fashion, the switching frequency can be abruptly changed from the minimum to the maximum in the next cycle. This can cause an adverse side-effect as analyzed in 4.2, and, as a result, the actual noise-power spectrum may not decrease but increase. The output bits from the linear feedback shift register is tapped from the consecutive stages in the shift registers, therefore, as shown in Figure 38 (b), the one less significant bit is just a one clock shifted version of the present bit output.

By making each bit output as a shifted version of the one less significant bit, when each bit is multiplied by the designated weighting number and added together for every clock cycle, the difference between each consecutive sum will be reduced. As the pseudo-random bit change become smoother, the abrupt change in the inductor current will be mitigated.

65 (a)

(b)

Figure 37. Block diagram of (a) 6-bit Current Steering DAC (b) digital PWM ramp- signal modulator.

66

(a)

(b)

Figure 38. Conceptual diagram illustrating (a) the proposed linear frequency modulation of the triangular PWM ramp signal using monotonically increasing bits (b) the proposed pseudo-random frequency modulation of the ramp signal using the linear feedback shift register.

67

Figure 39. Micro-photograph of the step-down DC-to-DC converter with a digital PWM ramp signal modulator.

4.4 Experimental Results

The implemented DC-to-DC converter with the proposed digital PWM ramp-signal modulator is shown in Figure 39. The DC-to-DC converter was implemented using a standard CMOS 0.18-µm process, and the total area is 1300 × 1000 µm2, and the area of digital PWM ramp signal modulator is 250 × 250 µm2. The digital PWM ramp-signal modulator consumes less than 5 % of the total area including wire-bonding pads.

68 A 3GHz digital oscilloscope was used to sample the output signal of the DC-to-DC converter in the time domain, and the internal FFT function of the digital oscilloscope was used to calculate and plot the frequency spectrum of the switching-noise power.

Measurements were performed at Vbat = 3.5 V, duty cycle = 0.5, and Vout = 1.75 V.

When the switching frequency of the DC-to-DC converter is fixed at 2 MHz, the peak switching noise at the fundamental switching frequency is about -34 dBm as shown in

Figure 42(a). when the random frequency modulation is turned on, the switching frequency varied between 2 MHz and 4 MHz in a pseudo-random pattern. The spurious noise peak is reduced from -34 dBm to -56 dBm from the random modulation.

When the digital PWM ramp-signal modulator with a 6-bit up/down converter is turned on and the switching frequency steps 64 times between 2 MHz and 4 MHz with a frequency-step size of about 35 kHz, the peak noise is reduced by 19 dB from -34 dBm to

-53 dBm.

A 4.7µH inductor and a 1.0µF capacitor are used for the output LC-filter, and a 30 Ω load was used to measure the noise spectrum. The results show that the proposed PWM ramp signal modulator can significantly reduce the peak of spectral-noise power. The maximum efficiency of the DC-to-DC converter was 92%.

69

Figure 40. Calculated power spectrum density of VCLK.

1-to-6bit LSFR (500n base / 2n step) 1-to-6bit LSFR (500n base / 4n step)

fixedat2MHz fixedat2MHz LFSR1bit -5 LFSR1bit -5 10 LFSR2bits 10 LFSR2bits LFSR3bits LFSR3bits LFSR4bits LFSR4bits LFSR5bits LFSR5bits 10-6 LFSR6bits 10-6 LFSR6bits

10-7 10-7 Power Spectral Density Spectral Power PowerDensitySpectral

10-8 10-8

0 1M 2M 3M 4M 5M 6M 7M 8M 0 1M 2M 3M 4M 5M 6M 7M 8M Frequency Frequency

1-to-6bit LSFR (500n base / 6n step)

fixedat2MHz LFSR1bit 10-5 LFSR2bits LFSR3bits LFSR4bits LFSR5bits LFSR6bits 10-6

10-7 Power SpectralPower Density

10-8

0 1M 2M 3M 4M 5M 6M 7M 8M Frequency

Figure 41. Calculated spurious noise peak for different number of frequency steps and for different frequency ranges.

70

(a)

(b)

(c)

Figure 42. (a) Triangular ramp signal at a constant frequency (b) randomly modulated triangular ramp signal (c) linear modulated triangular ramp signal.

71 No Freq Modulation Random Freq Modulation -34 dBm

2MHz 2MHz -56 dBm

(a)

8 Steps 16 Steps

-38 dBm -43 dBm

2MHz 2MHz

32 Steps 64 Steps

-48 dBm -52 dBm 2MHz 2MHz

(b)

Figure 43. (a) Output spectrum of the DC-to-DC converter using a fixed 2 MHz switching frequency and the proposed random frequency modulation (b) output spectrum of the DC-to-DC converter with monotonic frequency modulation with various frequency steps.

72 Chapter 5

Average Inductor-Current-Sensing Circuit

5.1 Overview

Many different current-sensing schemes have been developed and implemented, and the most common way to sense the output current of a switching converter is using an external resistor in series with the inductor or the power transistor [35]. However, this approach reduces the power efficiency because of the voltage drop across the series resistor, and the extra off-chip resistor could increase the size of the module.

By sensing the drain-source voltage of the power MOSFET, the output current can be estimated if the turn-on resistance Ron is known. This approach does not require an off- chip resistor, but the sensing accuracy is low because the turn-on resistance easily suffers from process variation. If Ron is too small, the sensed signal could be too small to be used.

On the other hand, a large turn-on resistor causes large voltage drop across it, and the efficiency of the switching converter would be degraded from the conduction loss at the resistor.

To overcome these limitations, there have been many on-chip current-sensing circuits

[36-40]. In [40], a high-accuracy on-chip current-sensing circuit was proposed. This proposed current-sensing circuit uses several switches to solve the current-source cutoff problem [38]. Because there is no cascaded MOSFET and OP-amplifier, the sensing circuit can operate at a low input voltage, and the measurement results showed that the circuit can operate for switching frequencies between 0.7 MHz and 1.4 MHz with the maximum accuracy of 99 % at Iload = 400mA.

73

Figure 44. Proposed average inductor current sensing circuit.

The proposed average inductor-current-sensing circuit is illustrated in Figure 44.

Similar to the previously proposed current-sensing circuit in [40], this proposed current- sensing circuit also uses several switches to circumvent current-source cutoff problem.

However, the main purpose of this current sensing circuit is to measure the average inductor-current at fast switching frequency, not to measure the instantaneous inductor- current. Therefore, instead of using a sensing resistor, a switching capacitor circuit, which is consist of C1, Mn5, and Mn6, is used to convert a current input to a voltage output.

C1 is charged by the time-varying input current through Mp2, Mn2, and Mn5 when Q is low. When Q is high, the charge in C1 is discharged through Mn6. The duty ratio of

PWM control signal will determine the ratio between the charging and the discharging

74 time. To reduce the dependence of Vsens on Vout change, the bias current Ibias is varied.

When the duty ratio is increased, Ibias is increased to leak more current via Mp7 from the mirrored-current at Mp5. If the duty ratio is decreased, Ibias is decreased to leak less current. The size of C1, Mn5, and Mn6 are carefully determined so that the averaged output voltage from the switch capacitor circuit is generated within the output dynamic range.

The switch capacitor circuit is followed by a source follower stage, Mn7 and Mn8, which has high input impedance and low output impedance. The differential output voltage, Vs+ and Vs-, is converted to a single-end output by using a differential amplifier.

High frequency switching noise will be filtered by a low-pass filter at the end of the differential amplifier. To eliminate the common-mode switching noise, the proposed current-sensing circuit is consist of two symmetric parts and operates in a differential mode. Vs+ and V- contains the common-mode switching noise, therefore, by taking the difference between Vs+ and V-, the common-mode noise can be eliminated. By changing the resistor values of R1 and R2, the gain of the differential amplifier can be adjusted as below

. (17) $ _WZ_  | F 0 \[_- . ZWY #

Switching operation of the proposed current-sensing circuit and Ibias control are illustrated in Figure 45.

75

(a)

(b) Figure 45. Switching operation of the proposed current-sensing circuit (a) for a turn-on state (b) for a turn-off state.

76

Figure 46. Simulated waveforms for output voltage, inductor current, and sensed voltage output.

5.2 Simulation Results

To evaluate the performance of the proposed current-sensing circuit, a DC-to-DC converter with a switching frequency over 25 MHz is designed and simulated with the proposed current-sensing circuit.

In Figure 46, the waveforms of the Vsens, the inductor current, and the output voltage, which shows the operation of the current sensing circuit, are plotted. The output voltage is regulated to 2.0 V with a varying current load. The output current is stepped from 50 to

800 mA with 150 mA current steps, and the Vsens was changed from 0.25 to 2.8 V. When

800 kHz sine-wave input and 100 kHz rectangular-wave input are applied, the output voltage, output current, and Vsens are plotted in Figure 46.

77

(a)

(b)

Figure 47. Simulated waveforms (a) for 600kHz sine wave with 4 Ω load (b) for 100 kHz rectangular wave with 4 Ω load.

78 5.3 Conclusion

In this preliminary research, a new switching frequency modulation scheme and an average inductor-current sensing circuit in a DC-to-DC converter were presented. The proposed digital ramp signal modulator was implemented in standard CMOS 0.18um process, and digital circuits are used to realize the modulator. Because of the highly reconfigurable characteristic of the digital circuit in the proposed ramp signal modulator, the switching frequency could be adaptively changed if the spurious noise level in a specific frequency range needs to be minimized. The presented digitally controlled switching frequency modulation scheme can be a good model of a small size and low power frequency modulator in a DC-to-DC converter.

Experimental results showed that the frequency modulator effectively reduce the spurious noise peak by spreading the noise over a wide frequency range. The maximum

19 dBc of the spurious noise peak reduction was achieved with 64 frequency steps between 2.2 MHz and 4.4 MHz.

An inductor-current sensing circuit in a fast switching DC-to-DC converter is designed and its functionality was verified from the simulation results. The simulation results show that the proposed current sensing circuit effectively senses the output inductor current when the prototyped DC-to-DC converter switches at 25 MHz. The sensed current value is transformed into a voltage to be used in the proposed dual switching converter. The more detailed explanation about the proposed dual switching converter will be followed in the next chapter.

79 Chapter 6

Parallel Connected Dual Switching Converter

6.1 Overview

As discussed in the prior arts, there have been many efficiency enhancement techniques to enhance the efficiency of RF PAs. In a conventional RF PA, the efficiency and the linearity are inversely proportional to each other because the PA has to be deeply backoff from the maximum output power level to acquire more linearity.

To modulate the supply voltage of the RF PA, a low-dropout (LDO) regulator has been widely used because of its wide-bandwidth operation and simple design. However,

LDOs suffer from its low light-load efficiency because the voltage drop across the pass transistor becomes larger as the output voltage is decreased from its maximum.

To overcome the efficiency limit, DC-to-DC switching converter is employed. But as shown in the preliminary research, a conventional DC-to-DC switching converter has inherent large switching noise that can cause a failure for spectral emission specification.

All the design parameters, such as switching frequency, inductor size, and pass-transistor size, have to be carefully chosen.

Considering the stringent performance requirements for current RF transmitter, there seems no single answer about how to improve the efficiency of wireless transmitter while maintaining all the remaining performance parameters. More realistic approach to overcome the bottleneck of efficiency limit in RF transmitters should be understanding the strength and weakness of various design approaches and finding a way to combine similar elements in a right proportion to maximize the overall performance.

80 A dual switching converter consisting of a fast switching converter and a slow switching converter is proposed so that high efficiency, wide bandwidth, and low output spurious noise can be achieved.

Figure 48 shows the conceptual diagram of the proposed converter that combines a fast switching converter acting as an independent voltage source and a slow switching converter acting as a dependent current source. This concept is similar to the hybrid converter structure in [26]. The output current I3 is the sum of I1 and I2, and the current equation can be given as

(14) ŵ 7%  7# - 7$  ŵ - ‘$ Ñ 7#   - ŵ Ñ 7$ ‘$

where β2 is the current gain of the slow switching converter loop. If β2 is sufficiently large, the output current I3 will be mostly supplied from I2 and I1 can be controlled reasonably small.

In the proposed converter, the linear amplifier is replaced by a fast switching converter. The fast switching converter operates in PWM mode with a fixed switching frequency over 30 MHz, and, as a result of the high switching frequency, low output voltage ripples can be attained and the predictable switching frequency ripple can be reduced further by a notch filter [11]. I2 contains a ripple current that is determined by the size of L1. This excessive ripple current will be absorbed by the fast converter because the fast converter regulates the output voltage with the wide bandwidth of β1. Comparing to the fast converter, the slow converter has a much lower switching frequency.

81 Slow Converter

Dead Time Control & 2 ~ 4MHz Driving

β2

L1 I to V I2 = I1 x β2

I3 Err Dead Time Control Vref & Vout Driving L2 I1

Cload load

30MHz R β1

Fast Converter

Figure 48. Proposed dual switching converter.

Table 6. Switching frequency and output current of the fast and slow converter

Switching Frequency Output Current

Fast F converter 7 ’ Slow I converter “ ,

Because of the low switching frequency, the switching loss becomes much less, and higher efficiency can be achieved. The fast converter controls the output voltage, and the slow converter efficiently supplies most of the output current by sensing the output

82 current of the fast converter. Large switches can be used in the slow converter for high current driving capability.

When the switching frequency and output current of the fast converter and the slow converter are set as Table 6, similar to [11], the power losses between the proposed dual converter and the conventional converter can be defined as

. (15) 2GG\^[\[_WV ŵ ŵ  - 2GGU[ZbWZ_`B[ZS” ^, ’

A is determined by the choice of the switching frequency, but B is determined by the loop gain of in Figure 48. The loop needs to be large to make the power loss small, ‘$ ‘$ but the phase margin of the loop must be kept large enough for stable closed-loop ‘$ operation. Because of the inverse relationship between the loop gain and the phase ‘$ margin, has to be kept small for wide bandwidth operation [11]. ‘$

83 6.2 Circuit Implementation

6.2.1 Design Voltage Mode Control Loop

The frequency response of the output LC-filter is plotted in Figure 49. Transfer function of the LC-filter can be defined as (16), and the location of the double poles and the zero can be extracted.

20 20 10 Gain 0 Phase − 10 − 20 − 30 − 40 − 50 − 60 Mag PF( fi )() − 70 − 80 Ph PF( f )() i − 90 − 100 − 110 − 120 − 130 − 140 − 150 − 160 − 180 − 170 − 180 3 4 5 6 7 8 9 10 11 10 100 1× 10 1× 10 1× 10 1× 10 1× 10 1× 10 1× 10 1× 10 1× 10 9 10 fi 100⋅ 10

Figure 49. Frequency response of the output LC-filter (L2 = 250nH, ResrL = 250mΩ including metal resistance, Cload = 150nF, ResrC = 10mΩ, and Rload = 5Ω).

ŵ Ӛ2>--ÉÉ-ӘW_^g - әӛ (16) _g!> _  ŵ Ӛ2>--ÉÉ-ӘW_^g - әӛ --_fŶ - W_^f _g!>

84

2 poles : ŵ = 821 kHz Ŷš Ñ EfŶ Ñ g!> 1 Zero : = 106 MHz ŵ Ŷš Ñ W_^g Ñ g!>

Damping Factor : = 6.45 fŶ 2>› g!>

A type-3 error amplifier can be used to compensate the frequency response of the fast converter. The transfer function is defined as (17). The gain and phase of the type-3 error amplifier is plotted in Figure 50. As shown in Figure 50, the unity gain bandwidth of the frequency response including the error amplifier and the output LC-filter is about 1.2

MHz, and the phase margin is about 60 degree. The transfer function of the type-3 error amplifier configuration and its poles and zeroes are shown as

(17) ŵ - _Ŷgŵœŵ - _ŵ - ŷgŷž _  _ŵgŵ - gŶŵ - _ŷgŷœŵ - _ŶgŵgŶÈgŵ - gŶž

1 zero : = 620 kHz ŵ Ŷš Ñ Ŷgŵ 2 Zero : = 620 kHz ŵ Ŷš Ñ ŵ - ŷgŷ 1 pole : = 87 Hz gŵ - gŶ Ŷš Ñ ŵgŵ - gŶ Ñ SBZ-[X-  2 pole : = 40 MHz ŵ Ŷš Ñ ŷgŷ

85 3 pole : = 40 MHz . gŵ - gŶ Ŷš Ñ ŶgŵgŶ

80 70 60 50 40 30 20 10 Mag PF( fi )() 0 − 10 Mag() LF_ERR_PF() fi − 20 − 30 Mag OpAmp f ()()i − 40 − 50 Ph() LF_ERR_PF() fi − 60 − 70 − 80 − 90 − 100 − 110 − 120 − 130 − 140 3 4 5 6 7 10 100 1× 10 1× 10 1× 10 1× 10 1× 10 1×10

fi Gain of Power Filter Gain of Err Amp + Power Filter Gain of Err Amp Phase of Err Amp + Power Filter

Figure 50. Gain and phase plot of the type-III frequency compensation error amplifier and power filter.

6.2.2 Floor Plan

The proposed dual switching converter is integrated with other analog blocks in a standard CMOS process. To minimize noise coupling into the noise-sensitive blocks like a bandgap circuit and a reference current/voltage generation block, the locations of

86 individual design blocks need to be carefully considered. Guard ring can be used to prevent noise coupling into sensitive analog blocks through the substrate, and the switching components can be isolated using N+ and P+ diffusion layers that connected to supply and ground voltage, respectively. However, these supply and ground connection should not be connected to other noisy blocks. It is always better to have separate quite supply and ground pins for connecting guard rings

There are three separate supply voltage domains in the dual converter, AVDD,

DVDD, and PVDD, and each block is connected to the designated supply rail as shown in Figure 51.

Figure 51. Power tree of the dual converter.

87 Because it takes micro-seconds to start up the bandgap circuit and stabilize the reference voltage and current output, a RC delay circuit was implemented to keep other blocks in ‘disabled state’ until the bandgap and reference generation blocks are initialized and become stable.

Figure 52 shows the floor plan for the dual converter. As a metal trace for interconnection becomes longer in physical dimension, the transmitted signal is more susceptive to noise. Therefore, at one corner of the die, the bandgap reference circuit is located close to the reference generation circuits and away from the switching components. To block substrate noise from the switching blocks and digital block to the analog block, guard rings using P+ and N+ substrate contacts are inserted.

Figure 52. Floor plan for the proposed dual converter.

88

R load load C L2 L1 LXS LXF PVDD PGND & Control I to V I Dead Time Gate Driver & Control DeadTime Gate DriverGate FB 30MHz Error 4MHz 2 2 Slow Converter Fast Converter

Vclk_test 2.5v reference voltage AGND Vramp Generator Reference Current/Voltage Tri_test B1_test Regulated at 3.0V Counter / Pseudo- random Sequence Generator Vbg EN Circuit Bandgap Digital SPI Reference Genration Block DIN CLK STB AVDD DVDD DGND RESET

Figure 53. Complete block diagram of the dual converter.

89 6.2.3 Layout

In switching power supply design, layout effort is very important portion of the design. For high current carrying path multiple output pins and bonding wires are used to minimize series resistance and bond-wire inductance. Figure 53 shows the top layout and output pins of the dual converter.

Figure 54. Screen capture of the layout for the parallel connected dual converter.

Input differential pairs and current mirrors are laid out in cross-coupled common- centroid geometry with dummy devices to minimize mismatch. Over-drive voltage of the current mirror needs to be sufficiently large (≈ 200mV) to minimize errors from threshold voltage mismatch between devices if enough headroom can be achieved. To reduce the conduction loss at the body diode in NMOS switch transistor, the substrate contact is tied to the source node.

90 The metal trace from the power transistors to the output pins should be carefully laid out because of the high current density in the trace. To minimize the voltage drop from metal resistance in the trace, the top two metal layers are laid out like Figure 54.

The current density for a unit cross-section in the metal trace increases because current from each branche is cummulated. Therefore, the current density far from the output pins is much smaller than the current density close to the pins. The width of current path needs to be increased toward the output pins to accommodate the increasing current denstiy.

Figure 55. Layout of the top two metal layers to connect the power transistors to the output pins.

91 6.2.4 PCB Design

A faster switching frequency can reduce the overall size of the converter, but there is more to understand about the impact of faster switching frequency than size. At high frequency a large capacitor, such as input capacitor at the supply and ground, looks like a

DC voltage source. Similarly, the large output inductor looks like a DC current source.

Magnetic flux is changed as the switches are turned on and off, and the current loop are rapidly changed although the input and output currents are roughly DC. This total loop area change introduces ground bounce along the return wire.

The PCB layout for the dual converter is shown in Figure 55. To minimize the ground bounce, the changing-loop area must be minimized and isolated from the ground return.

Becaues the dual converter incorporates two separate switching converters in one system the ground bounce and return current paths are considred for each current path.

92 load load R R

(a) (b)

Figure 56. (a) Fast converter current path (b) slow converter current path.

6.3 Simulation Results

The dual converter with the proposed current sensing circuit is simulated with input voltage steps to check the stability of the proposed converter, and the output voltage, output currents, voltage ripples, and current ripples are plotted in Figure 56. Figure 56 (b) shows that, as the input voltage Vramp is stepped upward, the output current of the fast converter quickly changes to follow the input change. As the output current of the fast

93 converter increases, the sensed voltage output from the inductor-current sensing circuit increases, and more current is drawn from the slow converter. As shown in Figure 56 (c), the large current ripples from the slow converter are effectively canceled by the fast converter, and only about 15 mV voltage ripples are remained.

When 1 MHz sine wave is applied to the input of the proposed dual converter, the dual converter’s output voltage effectively follows the 1 MHz input sine wave without distortion as shown in Figure 57 (a). Figure 57 (b) shows that the output current of the dual converter consists of two independent current outputs. The first current is the output current from the fast converter that quickly follows the input sine wave without distortion, and the second current is the output current from the slow converter that slowly increases and settles at a certain level.

When 100 kHz square wave is applied to the input of the dual converter, the output voltage of the dual converter is follows the input waveform as shown in Figure 58.

Figure 58 (b) shows that the output current of the fast converter is peaking at both the rising edge and the falling edge to quickly change the output voltage. The maximum achievable efficiency of the proposed dual converter is 85 % when Vout is 3.0 V with a load impedance of 4 Ω, and the efficiency at the various conditions is plotted in Figure 59.

94 Vramp

Vout

Vsens (Output voltage of the current sensor)

(a)

Iout of fast converter

Iout of slow converter

Total current output

(b)

Vout

Iout of slow converter

Iout of fast converter

Total current output

(c) Figure 57. Simulated waveforms for voltage steps (a) voltage outputs (b) current outputs (c) voltage and current ripples.

95 Vramp

Vout

(a)

Ifast

Islow

Total current output

(b) (1MHz sine wave with 2.2 Ω load)

Figure 58. Simulated waveforms for (a) Vramp and Vout (b) output Currents.

96 Vramp

Vout

(a)

Ifast

Islow

Total current output

(b) (100 kHz Rectangular Wave with 5 Ω Load)

Figure 59. Simulated waveforms for (a) Vramp and Vout (b) output currents.

97

100 95 90 85 80 75

70

Efficiency 65 60 55 50 0.5 1.0 1.5 2.0 2.5 3.0 Vout

Figure 60. Efficiency of the proposed dual converter (Rload = 4 Ω).

6.4 Experimental Results

The integrated dual switching converter’s experimental results are summarized in table 7. The measured data is slightly different from the simulated data mostly because of the effective series inductance (ESL) in the output capacitor and parasitic inductance in the current path in the metal layers and the PCB board.

Figure 60 shows the phase node of the slow converter for different output voltage.

The output current of the fast converter is sensed, and the slow converter adaptively changes its output current according to the sensed voltage. It is clearly shown that, when

Vout is 0.6 V, the duty ratio of the converter is small, and as the output voltage moves to

2.0 V, the duty ratio is increases.

98 Vout = 0.6 Volt

Vout = 2.0 Volt

Figure 61. Duty ratio change in the slow converter.

Figure 61 shows the voltage changes in the phase nodes in the fast and slow converter.

Because of the parasitic capacitance and inductance in the probe of the oscilloscope, the measured waveform is not very well defined, but it is clearly shown that as the output voltage the duty ratio of the fast converter gets larger, and both the fast converter and the slow converter are sharing the output load current. Because the fast converter is absorbing the current ripple from the slow converter, the overall ripple voltage becomes less than 50 mV even though the output load capacitor is only 150nF.

Figure 62 shows the transient response of the dual converter to 100 kHz a saw-shape, square, and sine input signal. Because of the RC delay in the current sensor, for the square wave input, the output has about 100 nSec delay. In Figure 62 (c) the output is driven out of the output dynamic range (0.6 – 3.0 V), the sine wave form is clipped at the maximum output of 3.0 V.

99

Vout = 0.9 Volt

Vout = 1.8 Volt

(Rload = 4 Ω).

Figure 62. Phase node voltage changes in the fast converter and the slow converter

100

(a)

(b)

(c)

Figure 63. Output transient response (a) to a 100 kHz saw-shape input signal (b) to a 100 kHz square wave signal (c) to a 100kHz sine wave (Rload = 4 Ω).

101 6.5 Conclusions

There is no single answer to how to improve the efficiency of wireless transmitter while maintaining its linearity and satisfying all other design specifications. More realistic approach to this problem should be thinking about how to combine similar elements in a right proportion to maximize the overall performance.

The dual switching converter that consists of two different switching converters is designed to maximize the efficiency and closed-loop bandwidth at the same time.

Simulation results show that the dual switching converter topology has high performance without large hardware penalties. The simulation results show that the proposed current- sensing circuit can sense the average current out of the fast converter with a high switching frequency (> 30MHz), and the sensed voltage output effectively control the output current of the slow converter.

The dual converter is fabricated in a standard 0.18 µm CMOS process. Experimental results shows that, when a wide bandwidth triangular pulse, sine wave, and saw-shaped signal are applied to the dual converter, the fast converter effectively provides the high frequency part of the output current and the slow converter provides the low frequency part of the output current. The large ripples from the slow converter are effectively absorbed by the fast converter, so the actual ripple voltage was less than 50mV with

150nF load capacitor.

102

Table 7. Summary of the integrated dual converter’s experimental results.

Unit experiment Control voltage range Volt 0.3 – 1.5 Output voltage range Volt 0.6 – 3.0 Load current range A < 1.2 Output voltage error % < 5

2 – 4 (slow conv) Switching frequency MHz 30 (fast conv)

Efficiency (peak load) % 85 Size µm2 1700 x 1000 Process IBM CMRF7SF 0.18 µm Standard CMOS

103 Chapter 7

Conclusions

7.1 Challenges

The primary research object was to design an efficient supply modulator for RF transmitter targeted for EDGE/WCDMA mobile communication systems. Improving battery lifetime for multi-functioning future hand-held devices was the main motivation of the research.

In cellular system, preserving in-channel fidelity and minimizing out-of-band spectral re-growth is the key to a functional cellular system. However, linearity and efficiency are inversely related to each other in RF transmitters. Moreover, varying the transmitter power over a large dynamic range complicates the problem even further because the RF transmitter needs to be more backoff from its maximum power transmission to accomplish the required linearity.

The design of a dynamically adaptive supply modulator requires quick transient response with very accurate voltage regulation. For a given inductor value and subsequent inductor ripple current, a large capacitor is desired to reduce the peak-to-peak value of the output ripple. Even though a large capacitor is beneficial for more stable output voltage at load transient response, the bandwidth of the overall transfer function is degraded because of the low frequency pole associated with the large load capacitor.

104 7.2 Technical Contributions and Impacts of the Dissertation

The original contributions of this research are in the area of efficient linear RF transmitter design in mobile communication systems where only limited power source is available. However, the concepts and techniques used in the proposed supply modulator can be utilized in other general purpose power management systems.

The contributions can be categorized into three sections: (1) developing frequency modulation techniques to reduce the spurious noise in switching converters and experimentally proving the effectiveness, (2) design of an average inductor current sensing circuit in a fast switching converter (switching frequency > 30 MHz), (3) design of a dual switching converter that combines wide bandwidth operation and higher efficiency at light-load condition.

Operational amplifier used as an error amplifier in the PWM modulation is developed to have a large ICMR, and a very efficient class-AB output stage is implemented to have a good current driving while mitigating losses from a large quiescent current.

This research also contribute in the successfully realizing an integrated switching converter using a standard CMOS technology based on the intuitive approach to small- signal modeling and analysis without complex mathematical formulations. This simplified approach is much more useful for analog circuit design in power management

IC design.

105 7.3 Future Work

To improve the light-load efficiency of the switch converter, pulse-frequency modulation (PFM) control can be used. In PFM control, the switching frequency is lower than a fixed frequency pulse-width modulation.

A constant on-time PFM control can be a good cadidate because it does not require complicated current sensing or estimation. However, in a constant on-time PFM control, the peak inductor current vaies with the supply voltage chagne. For a PFM controlled switchig converter to be used as a dynamic supply modulator for RF transmitter, the ripple voltage must be well defined and controlled because state-of-the-art portable batteries exhibit a wide variation in its output voltage (e.g., single-cell Li-ion:4.2 – 2.7 V

/ NiMH/NiCd: 1.8 – 0.9 V).

It is critical for a general power management system to operate in a low voltage range while withstanding a high breakdown voltage. Unfortunately, in a typical standard

CMOS technology, transistors with relatively high breakdown voltage uses a thicker gate oxide, which give larger threshold voltages in the order of 0.7 – 0.95 V. Therefore, low voltage circuit design techniques need to be employed to make the system functional at this low voltage range.

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112 Publications

[1] Eung Jung Kim; Chang-Hyuk Cho; Woonyun Kim; Chang-Ho Lee; Laskar, J.;

"Spurious noise reduction by modulating switching frequency in DC-to-DC converter for

RF power amplifier," Radio Frequency Integrated Circuits Symposium (RFIC), 2010

IEEE , vol., no., pp.43-46, 23-25 May 2010

[2] Eung Jung Kim; Chang-Hyuk Cho; Woonyun Kim; Chang-Ho Lee; “Switching

Frequency Modulated DC-to-DC Converter with Reduced Spurious Noise for RF Power

Amplifier,” to be submitted to IEEE, Transaction on Microwave Theory and Techniques

[3] Eung Jung Kim; Chang-Hyuk Cho; Woonyun Kim; Chang-Ho Lee; “Inductor

Current Sensing Techniques for Fast Switching Converters,” to be submitted to IEEE,

Power Electronics Letter

113 Vita

Eung Jung Kim was born in Seoul, Korea, in 1977. He received the B.S. degree and the M.S. degree in electrical engineering from Georgia Institute of Technology in 2004 and 2007, respectively.

In 2006 and 2008, he worked as an intern in RF Micro Devices, Greensboro, NC where he was involved in the development of power management circuits for GSM,

EDGE, and WCDMA transmitters. Especially, he worked on the development of low power DC-to-DC converters using CMOS technologies. Currently, he is working toward the Ph.D. degree in electrical and computer engineering at Georgia Institute of

Technology, where his research interests include integrated CMOS power management circuit for multi-standard wireless communications including GSM, EDGE, and

WCDMA applications.

114