65 nm Press Release August 2004

Intel's 65 nm Logic Technology

Mark Bohr

Intel Senior Fellow Director of Process Architecture & Integration

8/25/04 IntelIntel 1 Scaling Gets Tougher at Smaller Dimensions

1 1000 0.8 0.5 0.35 0.25 Lithography 0.18 Challenges 0.13 micron 0.1 90 Dimension 100 nm 65 Control Performance Mask Technology Power Making Challenges Active Power Cost

0.01 10 1980 1990 2000 2010 2020

IntelIntel 2 Scaling Gets Tougher at Smaller Dimensions

1 1000 W Plug 0.8 CMP 0.5 200mm 0.35 248nm STI 0.25 Lithography 0.18 CoSi2, SiOF Enablers Copper 0.13 micron 0.1 300mm 90 193nm 100 nm NiSi, Strain, Low-k 65 Phase Shift

Technology High-k EUV Enablers Tri-Gate

0.01 10 1980 1990 2000 2010 2020 Intel continues to develop and implement new materials and structures to meet the challenge IntelIntel 3 What are We Announcing Today?

• Intel is disclosing details of its 65 nm generation logic technology which provides improved performance and reduced power:

− 1.2 nm gate oxide − 35 nm transistor gate length − Enhanced strained technology − 8 layers of copper interconnect − Low-k dielectric

• This technology is being demonstrated on fully functional 70 Mbit SRAM chips with >0.5 billion

• Intel’s 65 nm technology is on track for delivery in 2005

IntelIntel 4 Intel's Logic Technology Evolution

Process Name Px60 P1262 P1264 P1266 P1268

Lithography 130nm 90nm 65nm 45nm 32nm

Gate Length 70nm 50nm 35nm 25nm 18nm

Wafer (mm) 200/300 300 300 300 300

1st Production 2001 2003 2005 2007 2009

Moore's Law continues! Intel continues to introduce a new technology generation every 2 years

IntelIntel 5 Key Density Indicator Continues to Scale

10 Pitch

Contacted Gate Pitch 1 (micron) 0.7x every 2 years

0.1 1992 1994 1996 1998 2000 2002 2004 2006 Transistor gate pitch continues to scale 0.7x per generation 0.7x linear scaling provides 2x transistor density improvement IntelIntel 6 65 nm Generation Transistors

• 1.2 nm gate oxide, 35 nm gate length for improved performance

• 220 nm contacted gate pitch for improved density

• NiSi for low resistance cap on gates and source-drains

• Intel’s unique uniaxial strained silicon technology, first introduced on the 90 nm generation, is further enhanced on 65 nm transistors for improved performance

• At the 65 nm generation, strained silicon improves performance ~30% relative to non-strain

Intel has developed a second generation of strained silicon technology while others are still struggling to develop their first generation IntelIntel 7 Intel’s Strained Silicon Technology

G G

S D S D

Selective SiGe S-D Tensile Si3N4 Cap

PMOS NMOS Uniaxial Compressive Strain Uniaxial Tensile Strain

From Intel’s 90 nm press release, October 2003 IntelIntel 8 Improved Transistor Performance

1000 1.0 V PMOS NMOS

100

IOFF (nA/um) 90 nm Better Better 10 2002

1 0.2 0.4 0.6 0.8 1.0 1.2

ION (mA/um)

Improved transistors provide increased drive current (ION) at constant leakage current (IOFF) IntelIntel 9 Improved Transistor Performance

1000 1.0 V PMOS NMOS

100

IOFF (nA/um) 90 nm 10 2002 2004

1 0.2 0.4 0.6 0.8 1.0 1.2

ION (mA/um)

90 nm transistors have continued to improve

IntelIntel 10 Improved Transistor Performance

1000 1.0 V PMOS NMOS

100

IOFF (nA/um) 90 nm 65 nm 10 2002 2004 2004

1 0.2 0.4 0.6 0.8 1.0 1.2

ION (mA/um)

65 nm transistors increase drive current 10-15% with enhanced strain

IntelIntel 11 Improved Transistor Performance

1000 1.0 V PMOS NMOS

100 Power IOFF Saving (nA/um) 90 nm 65 nm Feature 10 2002 2004 2004

1 0.2 0.4 0.6 0.8 1.0 1.2

ION (mA/um) 65 nm transistors can alternatively provide ~4x leakage reduction No other company has matched these performance-leakage capabilities IntelIntel 12 Reduced Gate Capacitance

• Gate oxide thickness is held constant at 1.2 nm to avoid increased gate leakage Gate CGATE

• Gate capacitance (CGATE) reduced ~20% due to smaller gate length (35 nm) Source Drain

• Lower gate capacitance reduces chip Substrate active power

• Combination of higher drive current and lower gate capacitance provides ~1.4x Power increase in switching frequency Saving Feature

IntelIntel 13 65 nm Generation Interconnects

• Metal 8 layer is added for improved density and performance M8 (1 more layer than 90 nm generation) • Low-k carbon doped oxide dielectric reduces interconnect M7 capacitance (improved from 90 nm generation) M6 • Interconnect capacitance is reduced by use of low-k dielectric M5 and by ~0.7x line length scaling M4 M3 • Lower capacitance improves M2 interconnect performance and M1 reduces chip power Power Saving Feature IntelIntel 14 0.57 µm2 6-T SRAM

• Ultra-small SRAM cell used in 65 nm process packs six transistors in an area of 0.57 µm2 • Approximately 10 million transistors could fit in the area of the tip of a ball point pen (1 mm2) • This SRAM cell is optimized for both small area and Power Saving ability to operate large arrays at low voltage Feature

IntelIntel 15 Intel 6-T SRAM Cell Size Trend 100

10 Cell Area 2 0.5x every (um ) 2 years 1

0.1 1992 1994 1996 1998 2000 2002 2004 2006

Transistor density continues to double every 2 years IntelIntel 16 70 Mbit SRAM Chip

• Fully functional 70 Mbit SRAM chips have been made

• >0.5 billion transistors

• 0.57 µm2 cell size

• Uses all process features needed for 65 nm logic products

110 mm2 chip size

No other company has yet demonstrated this level of integration on their 65 nm technology

IntelIntel 17 Power Reduction with Sleep Transistors

VDD 70 Mbit SRAM IR photos

SRAM Cache Sub-Block

NMOS Sleep Transistor Sleep transistors Normal SRAM V shut off leakage in SS block leakage inactive blocks

Power >3x SRAM leakage reduction with use of sleep transistors Saving Feature

IntelIntel 18 Product Benefits from 65 nm

Intel’s 65 nm process technology can:

• Improve CPU performance at constant or lower power by using smaller and faster transistors

• Reduce chip size by a factor of two for previous-generation designs for reduced cost and lower power

• Double the number of transistors per chip at constant chip size

• More transistors add new circuit capabilities and improve CPU performance

IntelIntel 19 65 nm Manufacturing

• Intel's 65 nm logic technology is being developed at our 300 mm wafer fab, D1D, located in Hillsboro, Oregon • At 176,000 sq feet, D1D is Intel's largest individual clean room (roughly the size of 3.5 football fields) • In addition to D1D, the 65 nm process will be manufactured on 300 mm wafers in Fab 12 in Arizona and Fab 24 in Ireland

IntelIntel 20 Summary

• Intel’s 65 nm logic technology provides industry-leading density, performance and power reduction features

• With this advanced technology, circuit designers can add more circuit features and increase performance while staying within power limits

• Intel’s 65 nm logic technology is being demonstrated on fully functional 70 Mbit SRAM chips with >0.5 billion transistors

• No other company has demonstrated this level of integration on their 65 nm process

• Intel’s 65 nm technology is on track for delivery in 2005

IntelIntel 21 More information on Intel’s 65 nm logic technology will be presented in a paper at the IEEE International Electron Devices Meeting San Francisco, December 12-15, 2004

For further information on Intel's silicon technology please visit the Silicon Showcase at www.intel.com/research/silicon

IntelIntel 22