NI sbRIO-9651
System on Module Carrier Board Design Guide
NI sbRIO-9651 System on Module Carrier Board Design Guide
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About This Document Terminology ...... ix Schematic Conventions ...... x Additional Documentation Resources...... xi Chapter 1 Fixed Behavior Signals Primary Ethernet (GBE0) ...... 1-1 GBE0 Signal Definitions...... 1-2 GBE0 Implementation on the Reference Carrier Board...... 1-3 Gigabit Ethernet Magnetic Requirements ...... 1-4 GBE0 Routing Considerations ...... 1-4 USB (USB0, USB1) ...... 1-5 USB0 Host/Device Signal Definitions ...... 1-5 USB0 Device Implementation on the Reference Carrier Board...... 1-6 USB1 Host Signal Definitions...... 1-7 USB1 Host Implementation on the Reference Carrier Board ...... 1-8 Supporting Onboard USB Devices...... 1-10 USB Routing Considerations...... 1-10 UART/Console Out (Serial1) ...... 1-10 Serial1 Signal Definitions...... 1-10 Serial1 Implementation on the Reference Carrier Board ...... 1-11 Adding Flow Control and Modem Control Signals...... 1-12 SD Card ...... 1-12 SD Signal Definitions...... 1-13 SD Implementation on the Reference Carrier Board...... 1-14 SD Routing Considerations ...... 1-16 RTC Battery (VBAT) ...... 1-16 VBAT Signal Definitions ...... 1-17 VBAT Implementation on the Reference Carrier Board...... 1-17 Eliminating the Effects of Contact Bounce ...... 1-17 Resets...... 1-18 Reset Signal Definitions ...... 1-18 Reset Implementation on the Reference Carrier Board...... 1-19 Status LED...... 1-20 Status LED Signal Definitions ...... 1-20 Status LED Implementation on the Reference Carrier Board ...... 1-20 FPGA Config...... 1-21 FPGA Config Signal Definitions...... 1-21 FPGA Config Implementation on the Reference Carrier Board ...... 1-21 Temp Alert...... 1-22 Temp Alert Signal Definitions ...... 1-22 Temp Alert Implementation on the Reference Carrier Board ...... 1-22
© National Instruments | v Contents
Chapter 2 User-Defined FPGA Signals Secondary Ethernet (GBE1) ...... 2-1 GBE1 Signal Definitions on the Reference Carrier Board ...... 2-2 GBE1 Reference Schematic...... 2-4 GBE1 Routing Considerations...... 2-8 Additional RS-232 (Serial2, Serial3, Serial4) ...... 2-9 Serial2 Signal Definitions on the Reference Carrier Board...... 2-9 Serial2 Reference Schematic ...... 2-10 RS-485 (Serial5, Serial6)...... 2-11 Serial5 Definitions on the Reference Carrier Board...... 2-12 Serial5 Reference Schematic ...... 2-13 RS-485 Layout Considerations...... 2-14 CAN (CAN0, CAN1) ...... 2-14 CAN0 Signal Definitions on the Reference Carrier Board...... 2-15 CAN0 Reference Schematic ...... 2-16 Termination Resistors for CAN Cables ...... 2-18 Chapter 3 Carrier Board PCB Layout Guidelines Impedance-Controlled Signaling ...... 3-1 Single-Ended Signal Best Practices...... 3-2 Differential Signal Best Practices ...... 3-2 Ground and Power Plane Recommendations...... 3-3 Fanout and Layout Options...... 3-3 Chapter 4 Mechanical Considerations Mounting...... 4-1 Selecting an Appropriate Mating Connector ...... 4-1 Selecting Appropriate Standoffs...... 4-2 Mounting Direction Options...... 4-4 Managing Thermal Conditions ...... 4-6 Designing a Suitable Enclosure ...... 4-6 Understanding Thermal Specifications...... 4-7 Validating the System...... 4-8 Validating Temperature Measurements...... 4-8 Managing Power and Feature Utilization ...... 4-10 Mounting Recommendations for Maximizing Thermal Performance...... 4-11 Additional Resources for Managing Thermal Conditions...... 4-12 Shock and Vibration ...... 4-12
vi | ni.com NI sbRIO-9651 System on Module Carrier Board Design Guide
Appendix A Reference Carrier Board Specifications and User Guide Parts Locator Diagram and Block Diagram ...... A-1 Specifications...... A-1 Ethernet...... A-2 Serial...... A-2 CAN...... A-2 SD Card ...... A-2 USB ...... A-2 Pmod...... A-2 RTC Battery...... A-4 Support Signals...... A-4 Connector Pinouts...... A-4 RS-232, RS-485, and CAN Connector Pinouts...... A-4 Pmod 12-Pin Connector Pinout ...... A-5 Pmod I2C Connector Pinout ...... A-6 Environmental Management...... A-6 Appendix B Revision History Appendix C NI Services
© National Instruments | vii About This Document
The NI sbRIO-9651 System on Module (SOM) provides an embedded real-time processor and reconfigurable FPGA. The sbRIO-9651 SOM requires a user-designed carrier board to provide power and I/O interfaces. You can optimize the carrier board to implement the exact functions your application requires. You can design the carrier board size and connector locations to fit the packaging or enclosure of your specific system.
This document provides detailed information about carrier board design techniques, guidelines, and requirements.
Note Refer to the documents listed in the Additional Documentation Resources section of this chapter for more information as you design, prototype, and implement your sbRIO-9651 SOM application. In particular, refer to the NI sbRIO-9651 System on Module OEM Device Specifications for dimensions, pinout information, functional specifications, and electrical specifications for the sbRIO-9651 SOM. Terminology
Table 1 defines terms used in this document to describe sbRIO-9651 SOM concepts and technology.
Table 1. sbRIO-9651 SOM Terminology in This Document
Term Definition
System Components
J1 Molex 45971-4185 320-pin, 8 × 40 position, SEARAY open-pin-field-array connector on the sbRIO-9651 SOM. SEARAY Connector family used for the J1 connector on the sbRIO-9651 SOM. Manufactured by Samtec and Molex. SOM System on Module. SoC System on Chip. USB Device Physical, electrical, addressable, and logical entity that is attached to USB and performs a function. USB Device port Port on a carrier board that provides a USB Device interface to the SOM. USB Host USB interface that controls the bus and communicates with connected USB devices.
USB Host port Port on a carrier board that provides a USB Host interface from the SOM.
© National Instruments | ix About This Document
Table 1. sbRIO-9651 SOM Terminology in This Document (Continued)
Term Definition
Reference Schematic and Signal Naming
LVTTL In compliance with the Low-Voltage Transistor-Transistor Logic (LVTTL) specification. LVCMOS In compliance with the Low-Voltage Complementary Metal Oxide Semiconductor (LVCMOS) specification. PUDC Pull-up During Configuration
Mechanical
CPU/FPGA The temperature reported digitally by a sensor that measures the die temperature junction temperature of the Xilinx Zynq SoC. Primary System The temperature reported digitally by a sensor on the Xilinx Zynq SoC temperature side of the circuit card assembly underneath the integrated heat spreader. This value is an approximation of the local ambient temperature inside the heat spreader. Secondary System The temperature reported digitally by a sensor on the SEARAY side temperature of the circuit card assembly. This value is a conservative approximation of the local ambient temperature on that side of the circuit card assembly. Schematic Conventions
Table 2 describes symbol conventions used in the I/O interface schematic diagrams in this document.
Table 2. Schematic Conventions in This Document
Symbol Description
Off-page symbol that represents communication to and from the mating connector.
Off-page symbol that represents communication from the mating connector. Off-page symbol that represents communication to the mating connector.
On-page symbol that represents the signal being driven.
x | ni.com NI sbRIO-9651 System on Module Carrier Board Design Guide
Table 2. Schematic Conventions in This Document (Continued)
Symbol Description
On-page symbol that represents the signal being received.
Power supply rail.
Analog ground.
I
Digital ground.
Chassis ground.
SPARE Refers to an unpopulated reference designator. Additional Documentation Resources
Refer to the following additional resources as you design, prototype, and implement your sbRIO-9651 SOM application.
© National Instruments | xi About This Document
What Would You Like to Resources Availability Learn More About?
NI sbRIO-9651 NI sbRIO-9651 System on Module System on Module OEM Device OEM Device Specifications
NI sbRIO-9651 NI sbRIO-9651 System on Module System on Module Development Kit Development Kit Quick Start Guide
Designing a carrier board NI sbRIO-9651 System on Module for your application Carrier Board Design Guide
Adding an sbRIO-9651 LabVIEW Help (NI-RIO) System on Module target in LabVIEW
Creating a socketed CLIP that defines the NI Single-Board RIO CLIP I/O configuration to use in your application Generator Help
ni.com/singleboard/setup NI Training and Support ni.com/training ni.com/support
PDF available online at ni.com/manuals Help file available locally Included in the shipping kit Available online at ni.com
xii | ni.com 1 Fixed Behavior Signals
A subset of pins on the J1 connector on the sbRIO-9651 SOM are dedicated to implementing the following specific I/O functionality: • Primary Ethernet (GBE0) • USB Host/Device (USB0) • USB Host (USB1) • UART/Console Out (Serial1) •SD Card
Other pins on the J1 connector are dedicated to implementing the following support signals: • RTC Battery (VBAT) •Resets •Status LED • FPGA Config • Temp Alert
Note Refer to the NI sbRIO-9651 System on Module OEM Device Specifications for a complete list of all pins and signals on the J1 connector.
The reference carrier board included with the sbRIO-9651 SOM development kit demonstrates how to implement each of these signals. Refer to the specific sections in this chapter for more information about how the reference carrier board implements each signal. Primary Ethernet (GBE0)
The sbRIO-9651 SOM provides a primary Gigabit Ethernet port (GBE0) for use on a carrier board. Refer to the Secondary Ethernet (GBE1) section of Chapter 2, User-Defined FPGA Signals, for information about implementing a secondary Gigabit Ethernet port.
© National Instruments | 1-1 Chapter 1 Fixed Behavior Signals GBE0 Signal Definitions Table 1-1 describes the GBE0 port pins and signals on the J1 connector on the sbRIO-9651 SOM.
Table 1-1. GBE0 Signal Definitions
Dedicated I/O Signal Name SOM Pin # Direction* Standard Description
GBE0_MDI0_P 1 I/O Defined by Pre-magnetic GBE0_MDI0_N 9 Ethernet Gigabit Ethernet GBE0_MDI1_P 18 PHY data pairs. GBE0_MDI1_N 26 specification. GBE0_MDI2_P 3 GBE0_MDI2_N 11 GBE0_MDI3_P 20 GBE0_MDI3_N 28 GBE0_SPEED_LEDg 5 O LVTTL Speed LED GBE0_SPEED_LEDy 13 signals. GBE0_ACT_LEDg 6 O LVTTL Activity/link LED signal.
* I/O direction is with respect to the sbRIO-9651 SOM.
1-2 | ni.com NI sbRIO-9651 System on Module Carrier Board Design Guide GBE0 Implementation on the Reference Carrier Board Figure 1-1 shows a schematic design for the GBE0 implementation on the reference carrier board. Figure 1-1. GBE0 Reference Schematic
J3 2 11 GBE0_MDIO_P MDIA_P 2 10 GBE0_MDIO_N MDIA_N~ 2 4 GBE0_MDI1_P MDIB_P 2 5 GBE0_MDI1_N MDIB_N~ 2 3 GBE0_MDI2_P MDIC_P 2 2 GBE0_MDI2_N MDIC_N~ 2 8 GBE0_MDI3_P MDID_P 2 GBE0_MDI3_N 9 MDID_N~ 17 12 SHIELD1 MCTA 18 6 SHIELD2 MCTB 1 MCTC 7 MCTD 13 1 C7 1 C8 1 C2 1 C4 LED1(GRN-CATH) 14 0.1UF 0.1UF 0.1UF 0.1UF LED1(GRN-AN) 15 10% 10% 10% 10% LED2(GRN-CATH/YEL-AN) 2 2 2 2 16V 16V 16V 16V 16 LED2(GRN-AN/YEL-CATH)
08261K1T-43-F R5 2 2 1 GBE0_ACT_LEDg 475 1% 1/16 W 2 GBE0_SPEED_LEDy
R6 2 21 GBE0_SPEED_LEDg 475 1% 1/16 W
Reference Schematic Design Considerations Table 1-2 lists design considerations for the schematic shown in Figure 1-1.
Table 1-2. GBE0 Reference Schematic Design Considerations
Consideration Notes
MDI data pairs • The MDI data pairs are routed differentially and connected directly to the Ethernet connector. • The Ethernet connector has the required Ethernet magnetics built into it. You may use discrete magnetics instead. LED signals • The LED signals can be used to directly drive connector LEDs. • The current-limiting resistors must be sized so that the drive current of the LED signals is not exceeded. • Refer to the Ethernet Speed LED Behavior section of the NI sbRIO-9651 System on Module OEM Device Specifications for information about Ethernet LED signal behavior and rated drive current.
© National Instruments | 1-3 Chapter 1 Fixed Behavior Signals Gigabit Ethernet Magnetic Requirements The Ethernet PHY on the sbRIO-9651 SOM uses voltage-mode drivers for the MDI pairs, which greatly reduces the power that the magnetics consume and eliminates the need for a sensitive center tap power supply.
You must consider the following requirements for connecting center taps: • Do not connect the center taps of the isolation transformer on the MDI pair side to any power source. Keep the center taps separate from each other. • Connect each center tap through separate 0.1 μF capacitors to ground. The separation is required because the common-mode voltage on each MDI pair might be different.
Table 1-3 lists recommended magnetic characteristics.
Table 1-3. Recommended Magnetic Characteristics
Parameter Value Test Condition
Turns ratio 1 CT : 1 CT — Open-circuit inductance (min) 350 μH 100 mV, 100kHz, 8 mA Insertion loss (max) 1.0 dB 0 MHz to 100 MHz HIPOT (min) 1500 Vrms —
The sbRIO-9651 SOM development kit uses the Gigabit Ethernet connector parts described in Table 1-4.
Table 1-4. Gigabit Ethernet Connector Parts
Part Manufacturer Part Number
sbRIO-9651 SOM PHY Micrel KSZ9031MNXIA Reference carrier board Gigabit Bel Stewart Magjack 0826-1K1T-43-F Ethernet connector
Refer to the datasheet for the Micrel Ethernet PHY for more information about magnetic requirements. GBE0 Routing Considerations NI recommends the following design practices for properly routing GBE0 signals on your carrier board: • Route MDI pairs differentially with 100 Ω differential trace impedance. • Length-match the positive and negative signal for each MDI data pair to within 10 mils.
1-4 | ni.com NI sbRIO-9651 System on Module Carrier Board Design Guide
• Limit the MDI trace lengths on the carrier board to 6.0 in. or less, which is the length at which Ethernet compliance was tested. USB (USB0, USB1)
The sbRIO-9651 SOM provides two USB 2.0-compliant ports for use on a carrier board: USB Host/Device port (USB0) and USB Host port (USB1).
Note Your carrier board design must provide the 5 V USB_VBUS power to USB Host ports and must limit the current supplied to each host port according to USB specifications. USB0 Host/Device Signal Definitions Table 1-5 describes the USB0 Host/Device port pins and signals on the sbRIO-9651 SOM connector.
Table 1-5. USB0 Host/Device Signal Definitions
Dedicated Signal Name SOM Pin # Direction* I/O Standard Description
USB0_DP 33 I/O Defined by USB0 data pair. USB USB0_DN 41 specification. USB0_MODE 65 I LVTTL Controls whether the USB0 port provides a Host or Device connection. Refer to the Configuring the USB0 Mode section of this chapter for more information. USB0_CPEN 73 O LVTTL USB0 over-current protection enable. USB0_VBUS 81 I 5 V tolerant USB0 VBUS input. voltage sense Allows USB PHY to sense if VBUS is present on the connector.
* I/O direction is with respect to the sbRIO-9651 SOM.
© National Instruments | 1-5 Chapter 1 Fixed Behavior Signals
Configuring the USB0 Mode You can configure the USB0 interface to be a USB Host port or a USB Device port, as shown in Table 1-6. This mode is set when the system boots and does not change dynamically. The reference carrier board uses the USB0 interface for a USB Device port.
Note USB On-The-Go (OTG) is not supported.
Table 1-6. Configuring the USB0 Mode
Mode How to Enable
USB Host Connect the USB0_MODE signal to digital ground on your carrier board. You can implement USB0 Host functionality in the same way that the USB1 Host signal is implemented on the reference carrier board, as described in the USB1 Host Implementation on the Reference Carrier Board section of this chapter. USB Device Connect the USB0_MODE signal to the VCC_3V3 rail on your carrier board. Refer to the USB0 Device Implementation on the Reference Carrier Board section of this chapter for more information about the USB0 Device implementation on the reference carrier board.
USB0 Device Implementation on the Reference Carrier Board Figure 1-2 shows a schematic design for the USB0 Device implementation on the reference carrier board. Figure 1-2. USB0 Device Reference Schematic
1 R78 2 0 5% 1/16W These lines can swap if layout is easier +3.3V Population Options For EMC/EMI L2 USB0_DN 2 2 4 3 USB0_DP 1 D+ U17 DLW21S_900 2 D– TPD2EUSB30 Not Populated R76 2 21 USB0_MODE 0, 5% 3 GND Pulled Up To Select Usb Device Port 1/16 W
J8 R66 2 1 2 C204 1 VBUS 12 USB0_VBUS 2 1 K D– 1 C32 1C33 3 D+ 0.5% 0.1 UF 10% 1.0 UF 0.1 UF 4 GND 50 V 2 10% 2 10% 5 SHLD1 16 V 16 V R61 6 SHLD2 21 Spare CONN-USB,B,HIGH_RETENTION R0603
1-6 | ni.com NI sbRIO-9651 System on Module Carrier Board Design Guide
Reference Schematic Design Considerations Table 1-7 lists design considerations for the schematic shown in Figure 1-2.
Table 1-7. USB0 Device Reference Schematic Design Considerations
Consideration Notes
USB data pair • The USB0_DP and USB0_DN data pair is routed differentially to the USB connector. • On the reference carrier board, the L2 common-mode choke is not populated, but you can populate it in your design to help with conducted immunity or emissions. • If you choose to populate L2, remove R76 and R78 from your design. • If your design does not include a common-mode choke, you can route the USB pair directly from the USB connector to the sbRIO-9651 SOM connector. • U17 provides ESD protection to the USB data pair and should be placed close to the USB connector.
USB0_MODE The USB0_MODE signal is pulled up to 3.3 V to select USB Device functionality. USB0_CPEN Leave the USB0_CPEN signal disconnected for a USB Device port. USB0_VBUS • For the USB Device port to function properly, the USB0_VBUS signal must be connected to the VBUS pin on the USB connector. • This is a low-current, voltage-sense connection. • In layout, you can treat this connection as a data signal. • R66 helps provide some overvoltage protection on USB0_VBUS and should be placed close to the USB connector. NI recommends that you use a 1 kΩ resistor.
USB1 Host Signal Definitions Table 1-8 describes the USB1 Host port pins and signals on the sbRIO-9651 SOM connector.
Table 1-8. USB1 Host Signal Definitions
Dedicated I/O Signal Name SOM Pin # Direction* Standard Description
USB1_DP 35 I/O Defined by USB1 data pair. USB USB1_DN 43 specification.
© National Instruments | 1-7 Chapter 1 Fixed Behavior Signals
Table 1-8. USB1 Host Signal Definitions (Continued)
Dedicated I/O Signal Name SOM Pin # Direction* Standard Description
USB1_CPEN 50 O LVTTL USB1 over-current protection enable. USB1_VBUS 58 I 5 V tolerant USB1 VBUS input. voltage sense Allows USB PHY to sense if VBUS is present on the connector.
* I/O direction is with respect to the sbRIO-9651 SOM. USB1 Host Implementation on the Reference Carrier Board Figure 1-3 shows a schematic design for the USB1 Host implementation on the reference carrier board. Figure 1-3. USB1 Host Reference Schematic
R82 1 2 0 5% 1/16 W These lines can swap if layout is easier POPULATION OPTIONS FOR EMC/EMI U18 L3 TPD2EUSB30 2 1 2 USB1_DN 2 4 3 USB1_DP 2 DLW21S_900 1 D+ USB1_VBUS NOT POPULATED 2 D– +5 V +5 V R79 1 2 1 0 5% R92 3 GND 1 R86 1/16 W 1 C57 1 k 4.7 K 0.1 UF 0.5% 0.5% 10% 2 1/16 W 2 16 V 2 U20 J10 6 1 1 IN OUT VCC 2 3 –DAT1 2 4 FAULT~ 3 USB1_CPEN EN +DAT1 5 4 GND GND 2 7 1 ILIM PAD 1 C67 1 C62 1 C61 – R93 5 100 UF 22 UF 0.01 UF SHLD1 1 K 6 1 1 TPS2553 6.3 V 25 V 100 V SHLD2 R85 R89 2 2 2 .5% 20% 10% 10% 2 4.7 K 23.2 K USB_A 0.5% 0.5% 1/16 W 1/16 W 2 2
C203 12
0.1 UF 10% 50 V
1-8 | ni.com NI sbRIO-9651 System on Module Carrier Board Design Guide
Reference Schematic Design Considerations Table 1-9 lists design considerations for the schematic shown in Figure 1-3.
Table 1-9. USB1 Host Reference Schematic Design Considerations
Consideration Notes
USB data pair • The USB1_DP and USB1_DN data pair is routed differentially to the USB connector. • On the reference carrier board, the L3 common-mode choke is not populated, but you can populate it in your design to help with conducted immunity or emissions. • If you choose to populate L3, remove R79 and R82 from your design. • If your design does not include a common-mode choke, you can route the USB pair directly from the USB connector to the sbRIO-9651 SOM connector. • U18 provides ESD protection to the USB data pair and should be placed close to the USB connector.
USB1_CPEN The USB1_CPEN signal must be connected to the enable of the VBUS current limit switch (U20). This allows the sbRIO-9651 SOM to power-cycle USB devices when the processor is reset. USB1_VBUS • For the USB Host port to function properly, the USB1_VBUS signal must be connected to VBUS on the USB connector. • This is a low-current, voltage-sense connection. • In layout, you can treat the trace after R92 going to the sbRIO-9651 SOM connector as a data signal. • R92 helps provide some overvoltage protection on USB1_VBUS and should be placed close to the USB connector. NI recommends that you use a 1 kΩ resistor. • The carrier board must provide 5 V VBUS power for the USB Host port. • A current limit switch is required between the 5 V rail and the USB connector. • U20 is the current limiter. • NI recommends that you provide 100 μF of capacitance on the VBUS rail.
© National Instruments | 1-9 Chapter 1 Fixed Behavior Signals Supporting Onboard USB Devices When you implement a USB device directly on your carrier board, you can connect the device to a USB Host port from the sbRIO-9651 SOM. For this case, use the following design guidelines: • You can connect the USB data pair directly to a USB device on your carrier board. • A current limiter is not required. • Use the CARRIER_RST# signal to reset the USB device when the sbRIO-9651 SOM is in reset. •Tie the USBx_VBUS signal to 3.3 V or 5 V. USB Routing Considerations NI recommends the following design practices for properly routing USB signals on your carrier board: • Route the USBx_DP and USBx_DN signals as differential pairs with 90 Ω differential impedance. • Length-match the positive and negative signal for each USB data pair to within 10 mils. • Limit the USBx_DP and USBx_DN trace lengths on the carrier board to 8.0 in. or less, which is the length at which USB compliance was tested. UART/Console Out (Serial1)
The sbRIO-9651 SOM provides a dedicated UART (Serial1) interface for use on a carrier board. This interface also functions as an operating system console when Console Out is enabled. Refer to the Additional RS-232 (Serial2, Serial3, Serial4) and RS-485 (Serial5, Serial6) sections of Chapter 2, User-Defined FPGA Signals, for information about implementing additional serial ports. Serial1 Signal Definitions Table 1-10 describes the Serial1 port pins and signals on the sbRIO-9651 SOM connector.
Note The NI-Serial driver has been developed for and tested with the Texas Instruments TRS3253EIRSMR RS-232 transceiver. Other transceivers may be compatible.
1-10 | ni.com NI sbRIO-9651 System on Module Carrier Board Design Guide
Table 1-10. Serial1 Signal Definitions
Dedicated I/O Signal Name SOM Pin # Direction* Standard Description
SERIAL1_TX 52 O LVTTL Two-wire serial and console out signals for SERIAL1_RX 60 I the sbRIO-9651 SOM.
* I/O direction is with respect to the sbRIO-9651 SOM.
Serial1 Implementation on the Reference Carrier Board Figure 1-4 shows a schematic design for the Serial1 implementation on the reference carrier board. Figure 1-4. Serial1 Reference Schematic
+3.3 V
2 C187 1 C189 1 C190 10% 0.1 UF 0.1 UF 0.1 UF 10% 10% C107 1 2 2 12 16 V 16 V 16 V +3.3 V 0.1 UF 10% U24 50 V 15 VL 30 J15 V+ 29 1 C1+ DSUB9-761918-A R125 31 3 C111 C1- V– 5 1 K 1 2 1 0.5% C2+ 9 5 2 2 4 0.1 UF 10% C2- R116 SERIAL1_TX_F# 4 2 50 V 4 25 1 2 8 SERIAL1_TX DIN1 DOUT1 SERIAL1_TX_CONN# 3 5 23 DIN2 DOUT2 0 5% 7 3 7 22 DIN3 DOUT3 1/16 W 2 789 14 ROUT1 RIN1 21 6 R123 13 ROUT2 RIN2 20 R115 1 6 2 1 2 12 19 SERIAL1_RX_F# 1 2 SERIAL1_RX_CONN# 12 SERIAL1_RX ROUT3 RIN3 11 ROUT4 RIN4 18 +3.3 V 10 39 0.5% 10 17 0 5% C94 11 1/16 W ROUT5 RIN5 1/16 W 1 2 9 27 +3.3 V +3.3 V FORCEON VCC 28 C188 FORCEOFF~ GND 26 2 C1206, SPARE 6 INVALID~ 0.1 UF 1 1 R124 33 R122 THERMALPAD 10% C99 4.7 K 1 SPARE 8 24 16 V 1 2 0.5% NC1 NC3 R0402 16 NC 32 2 2 1/16 W NC4 C1206, SPARE
2, 4 TRS3253EIRSMR FPGA_CFG
1 C106 R121 12 4.7 K 0.5% 0.1 UF 10% 2 1/16 W 50 V
Reference Schematic Design Considerations Table 1-11 lists design considerations for the schematic shown in Figure 1-4.
Table 1-11. Serial1 Reference Schematic Design Considerations
Consideration Notes
Interface The reference carrier board demonstrates how to use the Serial1 interface to implement a two-wire RS-232 serial port. Serial U24 is the RS-232 serial transceiver that converts between RS-232 and transceiver LVTTL signal levels. To minimize the impact of higher voltage signals on your carrier board, place the serial transceiver near the RS-232 connector.
© National Instruments | 1-11 Chapter 1 Fixed Behavior Signals
Table 1-11. Serial1 Reference Schematic Design Considerations (Continued)
Consideration Notes
Series R123 is the series termination for SERIAL1_RX. Use series termination termination at the serial transceiver on all signals being driven to the sbRIO-9651 SOM. The sbRIO-9651 SOM provides onboard series termination for SERIAL1_TX near the Xilinx Zynq SoC. FPGA All serial port signals pass through the FPGA on the sbRIO-9651 SOM. The FPGA_CFG signal is used to disable the serial transceiver when the FPGA is not configured. Disabling the transceiver in this way prevents any unwanted glitches on the RS-232 port. Adding Flow Control and Modem Control Signals You can use the sbRIO CLIP Generator application included with the NI-RIO Device Drivers software to add optional flow control and modem control signals to the Serial1 interface.
Refer to the Additional RS-232 (Serial2, Serial3, Serial4) section of Chapter 2, User-Defined FPGA Signals, for an example of how to implement a full-modem RS-232 port. Refer to the NI Single-Board RIO CLIP Generator Help, described in the Additional Documentation Resources section of the About This Document preface, for more information about using the sbRIO CLIP Generator application. SD Card
The sbRIO-9651 SOM provides a Secure Digital (SD) Card interface for use on a carrier board. This interface supports SD and SDHC cards. You can implement this interface with standard SD or microSD card connectors. The maximum supported SDHC card capacity is 32 GB.
1-12 | ni.com NI sbRIO-9651 System on Module Carrier Board Design Guide SD Signal Definitions Table 1-12 describes the SD pins and signals on the sbRIO-9651 SOM connector.
Table 1-12. SD Signal Definitions
Dedicated Signal Name SOM Pin # Direction* I/O Standard Description
SD_CLK 15 O LVTTL SD clock. SD_CMD 31 I/O LVTTL SD command. SD_D0 8 I/O LVTTL SD data bus. SD_D1 22 SD_D2 24 SD_D3 30 SD_CD# 32 I LVTTL SD card detect. Assert low when card is present. Can connect to a mechanical switch in the SD card socket. SD_WP 40 I LVTTL SD write protect. Assert high to enable protection. Can connect to a mechanical switch in the SD card socket. SD_PWR_EN 38 O LVTTL Power enable for SD card socket.
* I/O direction is with respect to the sbRIO-9651 SOM.
© National Instruments | 1-13 Chapter 1 Fixed Behavior Signals SD Implementation on the Reference Carrier Board Figure 1-5 shows a schematic design for the SD implementation on the reference carrier board. Figure 1-5. SD Reference Schematic
+3.3V
R38 2 12 1 R14 SD_PWR_EN 4.7 K 0 5% 0.5% 1/16 W U9 1/16 W 2 +3.3 V 4 5 EN OC# SD_OC# 3 INS1 6 VOUT_SD 2 OUTD1 INS2 7 1 OUTD2 1 C12 1 C13 1 C144 1 8 R21 GND OUTD3 10 UF 0.1 UF 10% 1 K 10% 10% 0.1 UF 0.5% 2 2 10 V 2 16 V 16 V TPS2030D 2
R211 2 1 2 J2 SD_D3 4 24.9 0.5% Vdd 1/16 W 1 R212 CD/D3 2 1 2 9 D2 SD_D2 8 D1 24.9 0.5% 7 1/16 W D0
R213 2 5 2 1 2 SD_CLK CLK SD_D1 2 CMD SD SOCKET 24.9 0.5% 1/16 W 10 CardDetect R214 11 2 1 2 +3.3V Common SD_D0 12 24.9 0.5% WP 1/16 W 3 R215 1 Vss1
6 hield1 2 1 2 Vss2 SD_CMD R198 S 24.9 0.5% 1 K 1/16 W 0.5% CONN9-764432-01-RA 13 2 R216 2 12 SD_CD# 68.1 0.5% +3.3V 1/16 W C205 12 1 R199 0.1UF 10% 1 K 50 V 0.5% 2 R217 2 1 2 SD_WP 68.1 .5% 1/16 W
1-14 | ni.com NI sbRIO-9651 System on Module Carrier Board Design Guide
Reference Schematic Design Considerations Table 1-13 lists design considerations for the schematic shown in Figure 1-5.
Table 1-13. SD Reference Schematic Design Considerations
Consideration Notes
SD_CLK, • You can route these signals directly from the sbRIO-9651 SOM to the SD_CMD, and SD connector. SD_D0 through • Each of these signals requires series termination near its driver. The SD_D3 sbRIO-9651 SOM provides series termination near the Xilinx Zynq SoC to prevent overshoot on the SD card when the sbRIO-9651 SOM drives these signals. The bi-directional signals also require series termination at the SD converter. • Use series termination at the SD connector for the SD_CMD and SD_D0 through SD_D3 signals to prevent overshoot on the sbRIO-9651 SOM when the SD card drives these signals.
SD_CD# • The SD_CD# signal is connected to the mechanical card-detect switch in the SD connector. • When a card is inserted, the card-detect pin on the SD connector is shorted to ground. • Because this is a mechanical switch with low output impedance, you must place a series termination resistor (R216) at the SD connector. • You must have a card-detect switch to properly support hot-swapping cards. If you do not need to support hot-swapping cards, you can use an SD connector without a card-detect switch. In this case, tie the SD_CD# signal to ground so that the sbRIO-9651 SOM attempts to initialize a card on boot.
© National Instruments | 1-15 Chapter 1 Fixed Behavior Signals
Table 1-13. SD Reference Schematic Design Considerations (Continued)
Consideration Notes
SD_WP • When the SD_WP signal is asserted high, the sbRIO-9651 will not write to the SD card. • Standard-size SD card connectors provide a mechanical write-protect switch that you can connect to the SD_WP signal. The switch detects the position of the lock slide on the SD card. • Because this is a mechanical switch with low output impedance, you must place a series termination resistor (R217) at the SD connector. • If you are using a microSD connector or do not have a write-protect switch, you can tie the SD_WP signal to ground in order to disable write protection and allow changes to the SD card.
SD_PWR_EN • Use the SD_PWR_EN signal to gate power to the SD connector. • U9 acts as a power switch and current limiter for the SD interface. SDHC cards must not draw more than 200 mA. • The SD_PWR_EN signal controls when power is going to the SD card. • The SD_PWR_EN signal asserts high when a card is detected using the SD_CD# signal. The SD_PWR_EN signal deasserts when a card is not present. SD Routing Considerations NI recommends the following design practices for properly routing SD signals on your carrier board: • Length-match the SD_CMD and SD_D0 through SD_D3 signals to within ±250 mils of SD_CLK. • Limit the trace length of the SD_CLK, SD_CMD, and SD_D0 through SD_D3 signals on the carrier board to 8.0 in. or less. RTC Battery (VBAT)
The reference carrier board contains a lithium cell battery that maintains the real-time clock (RTC) on the sbRIO-9651 SOM when the sbRIO-9651 SOM is powered off. A slight drain on the battery occurs when power is not applied to the sbRIO-9651 SOM. For information about the VBAT current drain, refer to the VBAT Requirements section of the NI sbRIO-9651 System on Module OEM Device Specifications.
If the battery is dead, or if no voltage has been applied to the VBAT pins, the system still starts but the system clock resets to the UNIX epoch date and time.
1-16 | ni.com NI sbRIO-9651 System on Module Carrier Board Design Guide VBAT Signal Definitions Table 1-14 describes the VBAT pins and signals on the sbRIO-9651 SOM connector.
Table 1-14. VBAT Signal Definitions
Dedicated I/O Signal Name SOM Pin # Direction* Standard Description
VBAT 64 I Power rail RTC battery input that provides backup power to the RTC to keep track of absolute time.
* I/O direction is with respect to the sbRIO-9651 SOM.
VBAT Implementation on the Reference Carrier Board Figure 1-6 shows a schematic design for the VBAT implementation on the reference carrier board. Figure 1-6. VBAT Reference Schematic
2 VBAT
1 +
BTH1 –
2 Use Br1225
BATHLDR-747921-01 Battery In This Holder
Reference Schematic Design Considerations You can directly connect the battery to VBAT. The sbRIO-9651 SOM already provides a current-limiting resistor and reverse-voltage protection. Eliminating the Effects of Contact Bounce If you are using the A revision of the sbRIO-9651 SOM, it is important to eliminate the effects of contact bounce when you initially attach the battery.
Note To determine the revision, check the bottom side of the sbRIO-9651 SOM for a sticker with the part number 157660x-01L, where x is the revision letter.
Contact bounce can cause a momentary power interruption to the RTC, which might result in drift greater than the RTC accuracy listed in the NI sbRIO-9651 System on Module OEM Device Specifications.
© National Instruments | 1-17 Chapter 1 Fixed Behavior Signals
To eliminate the effects of contact bounce, try one of the following methods: • (Preferred) Use power sequencing by applying Vcc to the RTC before attaching the battery. • Filter the signal using a small capacitor between VBAT and ground. The manufacturer recommends capacitor values between 0.1 nf and 1.0 nf. Resets
The sbRIO-9651 SOM provides signals for implementing a reset button on a carrier board and indicating that the sbRIO-9651 SOM is in reset. Reset Signal Definitions Table 1-15 describes the Reset pins and signals on the sbRIO-9651 SOM connector.
Table 1-15. Reset Signal Definitions
Dedicated I/O Signal Name SOM Pin # Direction* Standard Description
CARRIER_RST# 37 O LVTTL Reset that indicates that main power is not adequate or that the sbRIO-9651 SOM is in reset. Asserted low. SYS_RST# 47 I LVTTL System reset that puts the sbRIO-9651 SOM in reset. Asserted low. Asserting this signal causes the CARRIER_RST# signal to also assert. You can also assert this signal to put the sbRIO-9651 SOM into safe mode or reset IP address settings.
* I/O direction is with respect to the sbRIO-9651 SOM.
1-18 | ni.com NI sbRIO-9651 System on Module Carrier Board Design Guide Reset Implementation on the Reference Carrier Board Figure 1-7 shows a schematic design for the Reset implementation on the reference carrier board. Figure 1-7. Reset Reference Schematic
+3.3 V
1 R4 1K 0.5% 2 R2 2 1 2 RESET_SW# 2 4 SYS_RST# 68.1 0.5% 1 3 1 C3 1/16 W C0402 SW3 SPARE 2 720176-01
Refer to the SYS_RST# and CARRIER_RST# sections of the NI sbRIO-9651 System on Module OEM Device Specifications for more information about the behavior of the Reset signals. Reference Schematic Design Considerations Table 1-16 lists design considerations for the schematic shown in Figure 1-7.
Table 1-16. Reset Reference Schematic Design Considerations
Consideration Notes
Series When SYS_RST# is driven, you must place a series termination resistor termination at the driver. When the driver is a mechanical switch, placing series termination is especially important due to the low output impedance of the switch.
© National Instruments | 1-19 Chapter 1 Fixed Behavior Signals Status LED
The sbRIO-9651 SOM provides a Status LED signal for use on a carrier board. The Status LED indicates the status of the SOM boot process or Safe Mode and can be used to report software errors. Status LED Signal Definitions Table 1-17 describes the Status LED pins and signals on the sbRIO-9651 SOM connector.
Table 1-17. Status LED Signal Definitions
Dedicated I/O Signal Name SOM Pin # Direction* Standard Description
STATUS_LED 14 O LVTTL Status LED indicator.
* I/O direction is with respect to the sbRIO-9651 SOM.
Status LED Implementation on the Reference Carrier Board Figure 1-8 shows a schematic design for the Status LED implementation on the reference carrier board. Figure 1-8. Status LED Reference Schematic
DS7 YEL R127 2 1 2 1 2 STATUS_LED 357 0.5% 1/16 W
Refer to the STATUS_LED section of the NI sbRIO-9651 System on Module OEM Device Specifications for more information about the behavior of the Status LED signal.
1-20 | ni.com NI sbRIO-9651 System on Module Carrier Board Design Guide FPGA Config
The sbRIO-9651 SOM provides an FPGA Config signal to indicate when the FPGA is configured. FPGA Config Signal Definitions Table 1-18 describes the FPGA Config pins and signals on the sbRIO-9651 SOM connector.
Table 1-18. FPGA Config Signal Definitions
Signal Dedicated Name SOM Pin # Direction* I/O Standard Description
FPGA_CFG 53 O Refer to the FPGA Config Asserts NI sbRIO-9651 when the FPGA is System on Module configured. Asserted OEM Device high when the FPGA Specifications for has been more information programmed. about the behavior of this signal.
* I/O direction is with respect to the sbRIO-9651 SOM.
FPGA Config Implementation on the Reference Carrier Board Figure 1-9 shows a schematic design for the FPGA Config implementation on the reference carrier board. Figure 1-9. FPGA Config Reference Schematic
DS3 GRN R128 2, 3, 4 1 12 2 FPGA_CFG 357 0.5% 1/16 W LED_GRN_735278-01
Refer to the FPGA_CFG section of the NI sbRIO-9651 System on Module OEM Device Specifications for more information about the behavior of the FPGA Config signal.
© National Instruments | 1-21 Chapter 1 Fixed Behavior Signals Temp Aler t
The sbRIO-9651 SOM provides a Temp Alert signal to indicate that the onboard CPU/FPGA or Primary System temperature has exceeded the minimum or maximum temperature specifications of the sbRIO-9651 SOM. Refer to the Environmental section of the NI sbRIO-9651 System on Module OEM Device Specifications for the minimum and maximum temperature specifications. Temp Alert Signal Definitions Table 1-19 describes the Temp Alert pins and signals on the sbRIO-9651 SOM connector.
Table 1-19. Temp Alert Signal Definitions
Dedicated I/O Signal Name SOM Pin # Direction* Standard Description
TEMP_ALERT 46 O LVTTL Temp Alert indicator. Asserted high.
* I/O direction is with respect to the sbRIO-9651 SOM.
Temp Alert Implementation on the Reference Carrier Board Figure 1-10 shows a schematic design for the Temp Alert implementation on the reference carrier board. Figure 1-10. Temp Alert Reference Schematic
LED-QTLP630 RED R129 2 122 1 TEMP_ALERT 357 0.5% 1/16 W DS4
Refer to the TEMP_ALERT section of the NI sbRIO-9651 System on Module OEM Device Specifications for more information about the behavior of the Temp Alert signal.
Refer to the Validating Temperature Measurements section of Chapter 4, Mechanical Considerations, for information about validating the system temperatures of your sbRIO-9651 SOM application.
1-22 | ni.com 2 User-Defined FPGA Signals
The sbRIO-9651 SOM connector provides several banks of FPGA pins that you can configure for purposes specific to your application. In addition to FPGA Digital I/O (DIO), you can use these pins to implement the following run-time peripheral interfaces: • Secondary Ethernet (GBE1) • Additional RS-232 (Serial2, Serial3, Serial4) • RS-485 (Serial5, Serial6) • CAN (CAN0, CAN1)
The reference carrier board included with the sbRIO-9651 SOM development kit shows an example of how to implement these signals. Refer to the specific sections in this chapter for more information about how the reference carrier board implements each signal.
Note To read or write to this I/O from a LabVIEW project, you must use the sbRIO CLIP Generator application to create a socketed component-level IP (CLIP) that defines the I/O configuration of the sbRIO-9651 SOM to use in your application. Refer to the Getting Started with the NI sbRIO-9651 in LabVIEW topic in the LabVIEW Help for more information about creating a CLIP.
Tip When you create your own CLIP, you must compile your FPGA VI and download it to the flash of the sbRIO-9651 SOM. This ensures that the driver for each enabled peripheral can load properly at boot time. Refer to the Downloading an FPGA VI to the Flash Memory of an FPGA Target topic in the LabVIEW Help (FPGA Module) for more information. Secondary Ethernet (GBE1)
You must use specific FPGA pins to implement a secondary Ethernet port due to the strict timing requirements across semiconductor process and temperature variations.
The reference carrier board implements one secondary Ethernet port (GBE1) in addition to the primary Ethernet port. Refer to the Primary Ethernet (GBE0) section of Chapter 1, Fixed Behavior Signals, for more information about implementing a primary Ethernet port.
Note The sbRIO CLIP Generator enforces the selection of specific FPGA pins when you implement a secondary Ethernet port.
© National Instruments | 2-1 Chapter 2 User-Defined FPGA Signals GBE1 Signal Definitions on the Reference Carrier Board Table 2-1 describes the GBE1 pins and signals on the sbRIO-9651 SOM connector used to implement a secondary Ethernet port on the reference carrier board.
Table 2-1. GBE1 Signal Definitions
DIO Signal on Reference Signal Name Pin #* Carrier Board Direction† Description
TX Signals
GBE1_GMII_GTX_CLK 192 DIO_62_N O Gigabit transmit clock. GBE1_MII_TX_CLK 207 DIO_60_SRCC I 10/100 transmit clock. GBE1_GMII_TX_EN 215 DIO_60_N O Transmit enable. GBE1_GMII_TX_ER 183 DIO_59 O Transmit error. GBE1_GMII_TX_D0 235 DIO_49_N O Transmit data GBE1_GMII_TX_D1 227 DIO_49 bus. GBE1_GMII_TX_D2 211 DIO_48_N GBE1_GMII_TX_D3 203 DIO_48 GBE1_GMII_TX_D4 187 DIO_47_N GBE1_GMII_TX_D5 179 DIO_47 GBE1_GMII_TX_D6 234 DIO_46_N GBE1_GMII_TX_D7 242 DIO_46
RX Signals
GBE1_GMII_RX_CLK 231 DIO_61_MRCC I Receive clock. GBE1_GMII_RX_DV 200 DIO_62_MRCC I Receive data valid. GBE1_GMII_RX_ER 239 DIO_61_N I Receive error.
2-2 | ni.com NI sbRIO-9651 System on Module Carrier Board Design Guide
Table 2-1. GBE1 Signal Definitions (Continued)
DIO Signal on Reference Signal Name Pin #* Carrier Board Direction† Description
GBE1_GMII_RX_D0 210 DIO_45_N I Receive data GBE1_GMII_RX_D1 218 DIO_45 bus. GBE1_GMII_RX_D2 194 DIO_44 GBE1_GMII_RX_D3 186 DIO_44_N GBE1_GMII_RX_D4 170 DIO_43 GBE1_GMII_RX_D5 162 DIO_43_N GBE1_GMII_RX_D6 225 DIO_42 GBE1_GMII_RX_D7 233 DIO_42_N
Support Signals
GBE1_GMII_COL 201 DIO_41 I Collision detect.
GBE1_GMII_CRS 209 DIO_41_N I Carrier sense. GBE1_MDC 177 DIO_40 O MDIO clock, which needs to be pulled up on carrier board. GBE1_MDIO 185 DIO_40_N I/O MDIO data, which needs to be pulled up on carrier board. GBE1_IRQ# 191 DIO_59_N I PHY interrupt request, which should be pulled high on reference carrier board.
© National Instruments | 2-3 Chapter 2 User-Defined FPGA Signals
Table 2-1. GBE1 Signal Definitions (Continued)
DIO Signal on Reference Signal Name Pin #* Carrier Board Direction† Description
GBE1_SPEED_LEDg 126‡ DIO_33 O Speed LED GBE1_SPEED_LEDy 118‡ DIO_33_N signals: Yellow = 1000 Green = 100 Off = 10
* When you use the sbRIO CLIP Generator to enable secondary Ethernet, you must use the pins listed in this table. If you do not enable secondary Ethernet, you can use these pins for other FPGA DIO.
† I/O direction is with respect to the sbRIO-9651 SOM. I/O standards for these signals are defined in the sbRIO CLIP Generator.
‡ You can use any available FPGA DIO lines to implement these signals. In NI-RIO Device Drivers February 2015 or later, you can use the sbRIO CLIP Generator to assign FPGA DIO to these signals. GBE1 Reference Schematic Figure 2-1 shows a schematic design for the GBE1 implementation on the reference carrier board.
2-4 | ni.com NI sbRIO-9651 System on Module Carrier Board Design Guide 17 18 2 GBE1_ACT_LED C207 0.1 UF 10% 16 V 50 V C206 1 2 S HIELD1 S HIELD2 0.1 UF 10% 1 J6 + 3 . V 3 5 08261K1T-43-F DIR VCCA 2 MDIA_P MDIA_N~ MDIB_P MDIB_N~ MDIC_P MDIC_N~ MDID_P MDID_N~ MCTA MCTB MCTC MCTD LED1(GRN-CATH) LED1(GRN-AN) LED2(GRN-CATH/YEL-AN) LED2(GRN-AN/YEL-CATH) U26 C208 0.1 UF 10% 16 V R5 3 475 1% 1/16 W 8 9 4 5 3 2 6 1 7 11 10 12 1 3 14 15 16 74LVC1T45 16 V C115 VCCB BA GND 1 2 2 1 61 2 4 1 0.1 UF 10% C147 0.1 UF 10% 16 V +1.8 V 2 1 + 3 . V 5 4 R224 3 9 0.5% 1/16 W +1.8 V Y1 Y2 2 1 5 4 VCC U11 NC7WZ16 GDN A1 A2 Y U5 2 3 16 A B GBE1_ACT_LED 1 16 V C12 3 12 74LVCE1G08 2 2 0.1 UF 10% R22 3 3 9 0.5% 1/16 W 1 2 3 R 3 0 1/16W 475 1% 2 1 2 +1.8 V 5 4 GBE1_IRQ# Y U7 C9 0.1 UF 10% 16 V A B 2 u pling 74LVCE1G08 1 2 u pling 1 2 3 GBE1_ S PEED_LEDy C128 0.1 UF 16 V 10% GBE1_ S PEED_LEDg C10 0.1 UF 10% 16 V 1 2 1 2 R1 3 4 4.7 K 0.5% 1/16 W DVDDH Deco R222 3 9 0.5% 1/16 W AVDDH Deco C125 0.1 UF 10% 16 V 1 2 C140 0.1 UF 10% 16 V 1 2 C19 0.1 UF 10% 16 V 1 2 1 2 1 2 C122 0.1 UF 10% 16 V R1 33 1 K 0.5% PERIPHERAL_RE S ET_1V8# C18 0.1 UF 10% 16 V C14 3 0.1 UF 10% 16 V 2 1 C124 0.1 UF 10% 16 V +1.8 V 1 2 +1.8 V +1.8 V 5 4 1 2 1 2 1 2 Y VCC C1 3 7 0.1 UF 10% 16 V C1 3 1 10 UF 10% 10 V U8 1 2 1 2 +1.8 V + 3 . V NC A GND 1 2 3 S N74LVC1G04DBVR R19 1 K 0.5% 2 1 +1.8V R20 1 K 0.5% 2 2 2 1 C17 C14 50 V 50 V 33 pF 33 pF 1 1 R41 12.1 K 0.1% 1/16 W 2Y1 4 AVDDL_PLL_1V2 1 2 +1.2 V NC_GBE1_6 NC_GBE1_62 GND1 GND2 GBE1_I S ET GBE1_MDI1_N GBE1_MDI1_P GBE1_MDI2_P GBE1_MDI2_N GBE1_MDI 3 _P GBE1_MDI 3 _N GBE1_MDIO_P GBE1_MDIO_N GBE1_LED[2]_1P8 GBE1_LED_MODE GBE1_LED[1]_1P8
C126 0.1 UF 10% 16 V C1 3 9 0.1 UF 10% 16 V + 3 . V 1 25MHZ 3 4 5 58 59 2 3 7 8 55 5 3 6 3 65 9 64 1 16 12 1 3 10 11 14 15 19 17 62 6 1 2 1 2 I S ET NC[0] NC[1] C1 3 2 0.1 UF 10% 16 V C127 0.1 UF 10% 16 V LDO_O P_GND AVDDL[0] AVDDL[1] AVDDL[2] AVDDL[ 3 ] R45 S PARE R0402 TXRXP_A TXRXP_B AVDDH[0] AVDDH[1] TXRXP_C TXRXP_D TXRXM_A TXRXM_B AGNDH[0] AGNDH[1] TXRXM_C TXRXM_D 1 1 2 2 AVDDL_PLL 1 2 LED[2]/PHYAD1 C1 3 8 0.1 UF 10% 16 V C1 33 0.1 UF 10% 16 V ~I~N~T/~P~M~E~_~2 1 2 1 2 U10 CLK125_ND0/LED_MODE DVDDL Deco u pling LED1/PHYAD0/~P~M~E~_~1 KSZ9031MNXIA C1 3 6 0.1 UF 10% 16 V C142 0.1UF 10% 16 V GBE1_XTAL_IN GBE1_XTAL_OUT 1 2 1 2 R44 0 5% C141 0.1 UF 10% 16 V C1 3 4 0.1 UF 10% 16 V 1/16 W DVDDH[ 3 ] DVDDL[ 3 ] TXD1 TXD0 RX_DV/CLK125_EN RXD7 RXD4 MDIO TX_ER DVDDH[0] DVDDH[1] DVDDH[2] DVDDL[0] DVDDL[1] DVDDL[2] DVDDL[4] GTX_CLK TX_CLK TX_EN TXD7 TXD6 TXD5 TXD4 TXD 3 TXD2 RX_CLK/PHYAD2 RX_ER RXD6 RXD5 RXD 3 /MODE RXD2/MODE2 RXD1/MODE1 RXD0/MODE0 COL CR S MDC RE S ET~ XI XO 12 1 2 1 2 3 0 40 25 49 18 46 20 3 6 3 2 29 28 24 2 3 22 47 45 3 4 3 5 3 7 4 3 44 52 50 51 42 54 57 27 26 21 48 3 8 3 9 41 56 61 33 3 1 60 GBE1 Reference Schematic GBE1 Reference C148 10 UF 10% 10 V C118 10 UF 10% 10 V 2 2 2 2 2 2 2 2 2 2 +1.8 V 1 2 1 2 +1.2V +1.2V +1.2 V 2 R51 1/16 W 24.9 0.5% 1 GBE1_GMII_TX_ER GBE1_GMII_TX_EN GBE1_GMII_TX_D[7] GBE1_GMII_TX_D[6] GBE1_GMII_TX_D[5] GBE1_GMII_TX_D[4] GBE1_GMII_TX_D[ 3 ] GBE1_GMII_TX_D[2] GBE1_GMII_TX_D[1] GBE1_GMII_TX_D[0] 2 2 Figure 2-1. 2-1. Figure R52 1 K 0.5% R 3 6 R15 R17 R50 R24 R29 1/16 W GBE1_MII_TX_CLK 1/16 W 1/16 W 1/16 W 1/16 W 1/16 W 1 2 PERIPHERAL_RE S ET_1V8# 24.9 0.5% 24.9 0.5% 24.9 0.5% 24.9 0.5% u pling 24.9 0.5% 24.9 0.5% 12 GBE1_GMII_GTX_CLK 12 12 12 12 12 AVDDL_PLL_1V2 2 C15 0.1 UF 10% 16 V R55 R16 R 3 7 R47 R49 R40 R18 R25 R28 1 2 1/16 W 1/16 W 1/16 W C151 0.1 UF 10% 16 V 1/16 W 1/16 W 1/16 W 1/16 W 1/16 W 1 24.9 0.5% 24.9 0.5% 24.9 0.5% 24.9 0.5% 24.9 0.5% 24.9 0.5% 24.9 0.5% 24.9 0.5% 12 12 12 12 12 12 12 12 1 2 AVDDL_PLL Deco C16 10 UF 10% 10 V R26 10 K 0.5% 1/16 W 1 2 1 2 +1.8V 1 5 3 2 DIR R1 3 7 4.7 K 0.5% 1/16 W VCCA F L1 1 2 U1 3 1 6 BLM15AG121 74LVC1T45 VCCB BA GND 4.7 K 0.5% 1/16 W R1 3 2 6 4 2 1 R27 10 K 0.5% 1/16 W +1.2 V +1.8V +1.8V +1.8V + 3 . V 2 1 C20 0.1 UF 10% 16 V R2 3 10 K 0.5% 1/16 W R54 1 K 0.5% 2 1 1 2 1 2 R22 10 K 0.5% 1/16 W 2 2 1 R 3 5 10 K 0.5% 1/16 W 1 2 R 3 9 10 K 0.5% 1/16 W 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 1 2 CARRIER_R S T# GBE1_MDC GBE1_MDIO GBE1_GMII_COL GBE1_GMII_CR S GBE1_GMII_RX_ER GBE1_GMII_RX_DV GBE1_GMII_RX_D[7] GBE1_GMII_RX_D[6] GBE1_GMII_RX_D[5] GBE1_GMII_RX_D[4] GBE1_GMII_RX_D[ 3 ] GBE1_GMII_RX_D[2] GBE1_GMII_RX_D[1] GBE1_GMII_RX_D[0] GBE1_GMII_RX_CLK
© National Instruments | 2-5 Chapter 2 User-Defined FPGA Signals
Figure 2-2 shows additional schematic details for the GBE1 TX signal series termination resistors at the SEARAY. Figure 2-2. GBE1 TX Series Termination Reference Schematic
+1.8V +1.8V
R227 2C145 7 1 2 2C146 GBE1_MDC 0.1 UF 0.1 UF 49.9 0.5% 16 V 10% 1/16 W 1 10% 1 16 V R226 J5 7 1 2 GBE1_MDIO 168 176 VIO_BANK2_1 VIO_BANK2_2 49.9 0.5% 177 244 1/16 W DIO_40 DIO_52 185 236 DIO_40_N DIO_52_N 7 201 181 GBE1_GMII_COL DIO_41 DIO_53 7 209 189 GBE1_GMII_CRS DIO_41_N DIO_53_N 7 225 205 R203 GBE1_GMII_RX_D[6] DIO_42 DIO_54 7 1 2 7 233 213 GBE1_GMII_TX_D[7] GBE1_GMII_RX_D[7] DIO_42_N DIO_54_N 49.9 0.5% 7 170 229 1/16 W GBE1_GMII_RX_D[4] DIO_43 DIO_55 7 162 237 R204 GBE1_GMII_RX_D[5] DIO_43_N DIO_55_N 7 1 2 GBE1_GMII_TX_D[6] 7 194 198 GBE1_GMII_RX_D[2] DIO_44 DIO_56 49.9 0.5% 7 186 190 GBE1_GMII_RX_D[3] DIO_44_N DIO_56_N 1/16 W 7 218 222 R205 GBE1_GMII_RX_D[1] DIO_45 DIO_57 7 1 2 7 210 214 GBE1_GMII_TX_D[5] GBE1_GMII_RX_D[0] DIO_45_N DIO_57_N 49.9 0.5% 242 246 DIO_46 DIO_58 1/16 W 234 238 DIO_46_N DIO_58_N R206 R200 7 1 2 179 183 1 2 7 GBE1_GMII_TX_D[4] DIO_47 DIO_59 GBE1_GMII_TX_ER 49.9 0.5% 187 191 7 DIO_47_N DIO_59_N GBE1_IRQ# 49.9 0.5% 1/16 W 203 207 7 1/16W R207 DIO_48 DIO_60_SRCC GBE1_MII_TX_CLK R201 7 1 2 211 215 1 2 7 GBE1_GMII_TX_D[3] DIO_48_N DIO_60_N GBE1_GMII_TX_EN 49.9 0.5% 227 231 7 49.9 0.5% DIO_49 DIO_61_MRCC GBE1_GMII_RX_CLK 1/16 W 235 239 7 1/16W DIO_49_N DIO_61_N R208 GBE1_GMII_RX_ER 7 1 2 196 200 7 GBE1_GMII_TX_D[2] DIO_50 DIO_62_MRCC GBE1_GMII_RX_DV R202 188 192 1 2 7 49.9 0.5% DIO_50_N DIO_62_N GBE1_GMII_GTX_CLK 1/16 W 220 224 49.9 0.5% R209 DIO_51 DIO_63_SRCC 7 1 2 212 216 1/16W GBE1_GMII_TX_D[1] DIO_51_N DIO_63_N 49.9 0.5% 1/16 W SBRIO-9651 Mating Connector R210 Bank 2 - 4 of 6 Symbols 7 1 2 GBE1_GMII_TX_D[0] 49.9 0.5% 1/16 W
2-6 | ni.com NI sbRIO-9651 System on Module Carrier Board Design Guide
Reference Schematic Design Considerations Table 2-2 lists design considerations for the schematics shown in Figures 2-1 and 2-2.
Table 2-2. GBE1 Reference Schematic Design Considerations
Consideration Notes
Ethernet PHY • The only PHY supported for secondary Ethernet is the Micrel selection Ethernet PHY, part number KSZ9031MNXIA. Refer to Table 1-4, Gigabit Ethernet Connector Parts, of Chapter 1, Fixed Behavior Signals, for information about the Gigabit Ethernet connector parts used in the sbRIO-9651 SOM development kit. • To meet GMII timing to the sbRIO-9651 SOM, the DIO bank for the PHY (DVDDH) and VIO_BANK2 on the sbRIO-9651 SOM must be powered at 1.8 V. • All pull-up and pull-down resistors connected to the PHY must be implemented in your carrier board design as shown in Figure 2-1. These connections ensure that the PHY is set up properly for sbRIO-9651 SOM software support. • Refer to the datasheet for the Micrel Ethernet PHY for more information about secondary Ethernet PHY requirements.
GMII TX signals • Route the GMII TX signals directly to the Ethernet PHY. • To meet timing requirements, the TX signals must be 1.8 V logic. • You must place series termination resistors at the sbRIO-9651 SOM connector on the TX signals driving to the Ethernet PHY, as shown in Figure 2-2.
GMII RX signals • Connect the GMII RX signals directly to the Ethernet PHY. • The pull resistors on the RX signals set options in the PHY when coming out of reset. • The pull resistors must be implemented in your carrier board design as shown in Figure 2-1 to ensure that secondary Ethernet works properly. The resistors must be the same values shown in Figure 2-1. • You must place series termination resistors near the Ethernet PHY on all RX signals, as shown in Figure 2-1.
PHY crystal • NI recommends that you use a crystal with the Ethernet PHY. selection • The crystal must be 25 MHz with 50 ppm or better accuracy. • Ensure that you use suitable load capacitors for your crystal.
© National Instruments | 2-7 Chapter 2 User-Defined FPGA Signals
Table 2-2. GBE1 Reference Schematic Design Considerations (Continued)
Consideration Notes
MDI data pairs • The MDI data pairs are connected directly to the Ethernet connector. • Route the MDI data pairs differentially from the PHY to the connector. • The Ethernet connector has magnetics built into it. You may use discrete magnetics instead.
Magnetic Refer to the Gigabit Ethernet Magnetic Requirements section of selection Chapter 1, Fixed Behavior Signals, for information about magnetic requirements.
Ethernet speed Refer to the Ethernet Speed LED Behavior section of the LEDs NI sbRIO-9651 System on Module OEM Device Specifications for information about Ethernet LED signal behavior and rated drive current.
Ethernet link Figure 2-1 shows the logic required to create the same link activity activity LEDs LED behavior that the primary Ethernet signal uses. GBE1 support Connect these signals as shown in Figure 2-1. signals listed in Table 2-1 CARRIER_RST# The CARRIER_RST# signal should control the Ethernet PHY reset. Because the PHY has 1.8 V I/O, including the reset input, and the CARRIER_RST# signal is a 3.3 V signal, level translation is required to connect the CARRIER_RST# signal to the PHY. U13 provides this translation in Figure 2-1. GBE1 Routing Considerations NI recommends the following design practices for properly routing GBE1 signals on your carrier board: • Length-match GMII TX signals to within ±250 mils of the GBE1_GMII_GTX_CLK signal. • Length-match GMII RX signals to within ±250 mils of the GBE1_GMII_RX_CLK signal. • Limit the overall length of GMII TX and RX signals to 5.0 in. or less. • Route MDI pairs differentially with 100 Ω differential trace impedance. • Length-match the positive and negative signal for each MDI data pair to within 10 mils. • Limit the MDI trace lengths to 6.0 in. or less, which is the length at which Ethernet compliance was tested.
2-8 | ni.com NI sbRIO-9651 System on Module Carrier Board Design Guide Additional RS-232 (Serial2, Serial3, Serial4)
You can use any FPGA pins to implement additional RS-232 ports.
The reference carrier board implements one secondary RS-232 port (Serial2) in addition to the primary UART/Console Out port. You can implement additional RS-232 ports (Serial3 and Serial4) in the same way that the Serial1 signal is implemented on the reference carrier board. Refer to the UART/Console Out (Serial1) section of Chapter 1, Fixed Behavior Signals for more information about implementing the primary UART/Console Out port. Serial2 Signal Definitions on the Reference Carrier Board Table 2-3 describes the Serial2 pins and signals on the sbRIO-9651 SOM connector used to implement an additional RS-232 port on the reference carrier board.
Note The NI-Serial driver has been developed for and tested with the Texas Instruments TRS3253EIRSMR RS-232 transceiver. Other transceivers may be compatible.
Table 2-3. Serial2 Signal Definitions
DIO Signal on Reference Signal Name Pin #* Carrier Board Direction† Description
SERIAL2_TX 66 DIO_0 O Full-modem RS-232 serial port signals. SERIAL2_RX 69 DIO_7 I SERIAL2_RTS# 74 DIO_1 O SERIAL2_CTS# 76 DIO_6 I SERIAL2_DTR# 59 DIO_2 O SERIAL2_DSR# 83 DIO_4 I SERIAL2_DCD# 75 DIO_3 I SERIAL2_RI# 68 DIO_5 I
* The pin numbers listed in this table are the pins used on the reference carrier board. For your carrier board design, you can use the sbRIO CLIP Generator to configure these pins for any FPGA DIO.
† I/O direction is with respect to the sbRIO-9651 SOM. I/O standards for these signals are defined in the sbRIO CLIP Generator.
© National Instruments | 2-9
Chapter 2 User-Defined FPGA Signals
789 6
J11
45 3 UB9-761918-A 12 S D 5 9 4 8 3 7 2 6 1 10 11 2 3 PARE _CONN _CONN PARE PARE PARE PARE PARE 50V PARE PARE PARE PARE C58 R_CONN S S R108 3 3 S , S , S , S , S , S , S , S , S , S C66 C6 C64 C65 12 C84 C8 C82 C81 C80 12 0.1 UF 10% IGNAL_GND_2 R0805, S S 12 12 12 12 12 12 12 12 12 3 C060 3 C060 3 C060 3 C060 3 C060 C060 3 C060 3 C060 3 C060 3 ERIAL2_RI_CONN ERIAL2_CD_CONN ERIAL2_RX_CONN# ERIAL2_RT ERIAL2_CT ERIAL2_DTR_CONN ERIAL2_TX_CONN# ERIAL2_D S S S S S S S S ERIAL2_ S 2 2 2 2 . s ced ctice. ed a a R154 R162 R160 R152 0 5% 0 5% 0 5% 0 5% 1/16W 1/16W 1/16W 1/16W e us re pl a
n b 1 1 1 1 s a p c a t a nd rd pr C S ce emi ss ion u ce to red 2 120pF, 220pF, 470pF, etc 470pF, 220pF, 120pF, 2 2 2 2 3 3 R155 0 5% 1/16W R16 R161 R159 R15 0 5% 0 5% 0 5% 0 5% 1/16W 1/16W 1/16W 1/16W 1 1 1 1 1 _F _F S S R_F S ERIAL2_RI_F ERIAL2_CD_F S ERIAL2_TX_F# ERIAL2_RX_F# ERIAL2_CT ERIAL2_RT ERIAL2_DTR_F S ERIAL2_D S S S S S S C76 1800 PF 50 V 5% V 3 . 3 2 1 + C175 0.1 UF 10% 16 V V 3 . 3 2 1 + _F _F R_F S S S C168 0.1 UF 10% 16 V tion on board. the reference carrier 1 2 ERIAL2_TX_F# ERIAL2_RT ERIAL2_DTR_F ERIAL2_RX_F# ERIAL2_CT ERIAL2_RI_F ERIAL2_CD_F ERIAL2_D S S S S S S S S Serial2 Reference Schematic Serial2 Reference 1 0 3 2 7 3 3 25 2 22 21 20 19 18 17 27 26 33 24 3 0.1 UF 10% 16 V C1 3 V- V+ 1 2 NC4 NC 3 VCC GND RIN1 RIN2 3 RIN RIN4 RIN5 DOUT1 DOUT2 DOUT MR S EIR THERMALPAD U19 25 3 S3 3 TR C176 0.1 UF 10% 16 V C1+ C1- C2+ C2- DIN1 DIN2 3 DIN ROUT1 ROUT2 ROUT ROUT4 ROUT5 FORCEON FORCEOFF~ INVALID~ VL NC1 NC2 2 1 1 2 4 5 7 9 6 8 1 3 V Figure 2-3. 15 29 3 14 1 12 11 10 28 16 3 . 3 + 21 10%
R147 4.7 K 0.5% 1/16 W C48 C46 50 V 50 V 12 2 0.1 UF 10% 1 0.1 UF R80 4.7 K 0.5% 1/16 W V 3 . 3 1 2 + 0.5% R81 1 K 0.5% PARE V R88 R84 R145 S R0402 3 9 1/16W V 9 0.5% 9 1/16W . 3 3 3 3 . 1 2 + 3 1 2 12 12 + 3 R8 R87 0.5% 9 0.5% 9 9 0.5% 9 1/16W 1/16W R90 3 3 9 1/16W 3 12 12 tic design for the Serial2 implementa the Serial2 for tic design 12 2, 3 2 2 2 2 2 2 2 2 # # S S R# S ERIAL2_TX ERIAL2_RX FPGA_CFG ERIAL2_RI# S S S ERIAL2_CT ERIAL2_RT ERIAL2_DTR# ERIAL2_D ERIAL2_DCD# S S S S S Serial2 Reference Schematic Serial2 Reference Figure 2-3 shows a schema
2-10 | ni.com NI sbRIO-9651 System on Module Carrier Board Design Guide
Reference Schematic Design Considerations Table 2-4 lists design considerations for the schematic shown in Figure 2-3.
Table 2-4. Serial2 Reference Schematic Design Considerations
Consideration Notes
Interface The reference carrier board demonstrates how to use the Serial2 interface to implement a null-modem RS-232 serial port. Serial U19 is the RS-232 serial transceiver that converts between RS-232 and transceiver LVTTL signal levels. To minimize the impact of higher voltage signals on your carrier board, place the serial transceiver near the RS-232 connector. Series • R83, R84, R87, R88, and R90 are the series termination for Serial2. termination Use series termination at the serial transceiver on all signals being driven to the sbRIO-9651 SOM. • FPGA DIO signals from DIO Bank 0 include series termination on the sbRIO-9651 SOM. Use series termination at the SEARAY connector on all signals outside of Bank 0 being driven from the sbRIO-9651 SOM to the serial transceiver.
FPGA All serial port signals pass through the FPGA on the sbRIO-9651 SOM. The FPGA_CFG signal is used to disable the serial transceiver when the FPGA is not configured. Disabling the transceiver in this way prevents any unwanted glitches on the RS-232 port. RS-485 (Serial5, Serial6)
You can use any FPGA pins to implement an RS-485 port.
The reference carrier board implements one RS-485 port (Serial5). You can implement an additional RS-485 port (Serial6) in the same way that the Serial5 signal is implemented on the reference carrier board.
© National Instruments | 2-11 Chapter 2 User-Defined FPGA Signals Serial5 Definitions on the Reference Carrier Board Table 2-5 describes the Serial5 pins and signals on the sbRIO-9651 SOM connector used to implement an RS-485 port on the reference carrier board.
Note The NI-Serial driver has been developed for and tested with the Analog Devices ADM2587EBRWZ Isolated RS-485 transceiver. Other isolated and non-isolated transceivers may be compatible.
Table 2-5. Serial5 Signal Definitions
DIO Signal on Reference Signal Name Pin #* Carrier Board Direction† Description
SERIAL5_TX 70 DIO_11 O Isolated RS-485 interface signals. SERIAL5_TX_EN 78 DIO_12 O SERIAL5_RX 79 DIO_14 I SERIAL5_RX_EN 87 DIO_15_MRCC O
* The pin numbers listed in this table are the pins used on the reference carrier board. For your carrier board design, you can use the sbRIO CLIP Generator to configure these pins for any FPGA DIO.
† I/O direction is with respect to the sbRIO-9651 SOM. I/O standards for these signals are defined in the sbRIO CLIP Generator.
2-12 | ni.com NI sbRIO-9651 System on Module Carrier Board Design Guide Serial5 Reference Schematic Figure 2-4 shows a schematic design for the Serial5 implementation on the reference carrier board. Figure 2-4. Serial5 Reference Schematic
0.1 uF and 0.01 uF 10 uF and 0.1 uF Across pin 2 and 1 Across pin 8 and 9 10 uF and 0.1 uF 0.1 uF and 0.01 uF +3.3V +3.3V Across pin 12 and 11 Across pin 19 and 20
Vcc_RS485_1 Vcc_RS485_1
2 C154 1 C153 2 C159 2 C160 1 C161 1 C162 1 C156 1 C155 0.1 UF 0.01 UF 10 UF 0.1 UF 0.1 UF 10 UF 0.01 UF 0.1 UF 10% 10% 10% 10% 10% 10% 10% 10% 1 16 V 2 100 V 1 10 V 1 16 V 2 16 V 2 10 V 2 100 V 2 16 V
I I I IGND0 IGND0 IGND0
+3.3V Vcc_RS485_1 U25 1 GND1-1 isoPower DC-DC Converter 2 20 VDD1-1 GND2-4 19 3 VISOIN J7 GND1-2 16 DSUB9-761918-A GND2-3 8 12 VDD1-2 VISOOUT 14 5 54 9 GND2-2 SERIAL5_RXN GND1-3 9 +3.3V SERIAL5_TXN 10 I 4 GND1-4 Digital SERIAL5_RXP IGND0 8 Isolation iCoupler Tranceiver SERIAL5_TXP 2 3 3 Y 13 2 7 TxD SERIAL5_TXP 7 R141 D Z 15 10 K SERIAL5_TXN 2 1/16 W SERIAL5_TX 0.5% 6 6789
1 2 6 DE 1 12 SERIAL5_TX_EN A 18 I 10
OLATION BARRIER SERIAL5_RXP R140 IGND0 11 2 1 2 4 RxD I S R SERIAL5_RX B 17 SERIAL5_RXN 39 0.5% 1/16W 2 5 RE~ 11 GND2-1 SERIAL5_RX_EN ADM2587E I IGND0
© National Instruments | 2-13 Chapter 2 User-Defined FPGA Signals
Reference Schematic Design Considerations Table 2-6 lists design considerations for the schematic shown in Figure 2-4
Table 2-6. Serial5 Reference Schematic Design Considerations
Consideration Notes
Interface The reference carrier board demonstrates how to use the Serial5 interface to implement an isolated RS-485 serial port. Serial U25 is the RS-485 serial transceiver that converts between RS-485 and transceiver LVTTL signal levels. This transceiver provides functional isolation of the RS-485 signals to prevent ground loops from affecting the RS-485 signals. Series • R140 is the series termination for Serial5. Use series termination at the termination serial transceiver on all signals being driven to the sbRIO-9651 SOM. • FPGA DIO signals from DIO Bank 0 include series termination on the sbRIO-9651 SOM. Use series termination at the SEARAY connector on all signals outside of Bank 0 being driven from the sbRIO-9651 SOM to the serial transceiver.
RS-485 Layout Considerations Pay close attention to how the ground planes are arranged under the isolated RS-485 transceiver. Isolated and non-isolated ground planes overlap across layers to provide some capacitance between the grounds and help with EMC. Refer to the datasheet for the RS-485 transceiver for more information. CAN (CAN0, CAN1)
You can use any FPGA pins to implement a CAN interface port.
The reference carrier board implements one CAN port (CAN0). You can implement an additional CAN port (CAN1) in the same way that the CAN0 signal is implemented on the reference carrier board.
2-14 | ni.com NI sbRIO-9651 System on Module Carrier Board Design Guide CAN0 Signal Definitions on the Reference Carrier Board Table 2-7 describes the CAN0 pins and signals on the sbRIO-9651 SOM connector used to implement a CAN interface port on the reference carrier board.
Note The NI-Embedded CAN driver has been developed for and tested with the NXP PCA82C251T/YM CAN transceiver. Other transceivers may be compatible.
Table 2-7. CAN0 Signal Definitions
DIO Signal on Reference Signal Name Pin #* Carrier Board Direction† Description
CAN0_TX 85 DIO_8 O Transmit line. CAN0_RX 54 DIO_9 I Receive line. CAN0_RS 62 DIO_10 O Slope control and standby.
* The pin numbers listed in this table are the pins used on the reference carrier board. For your carrier board design, you can use the sbRIO CLIP Generator to configure these pins for any FPGA DIO.
† I/O direction is with respect to the sbRIO-9651 SOM. I/O standards for these signals are defined in the sbRIO CLIP Generator.
© National Instruments | 2-15 Chapter 2 User-Defined FPGA Signals CAN0 Reference Schematic Figure 2-5 shows a schematic design for the CAN0 implementation1 on the reference carrier board. Figure 2-5. CAN0 Reference Schematic
+3.3V +5V
1 C113 0.1 UF 1 C6 10% 0.1 UF 10% 2 16 V 2 16 V U2 6 1 CAN0_RX R8 VCCB VCCA 2 1 2 4 3 CAN0_RX_5V BA 2 5 49.9 0.5% GND DIR 1/16 W 74LVC1T45
+3.3V +3.3V +5V +5V
1 2 C120 1 C117 R132 0.1 UF 0.1 UF 1 1 K 10% 10% R12 0.5% 1 16 V 2 16 V 1 K 2 U4 0.5% R7 1 2 CAN0_RX_5V_R 61 2 CAN0_TX VCCB VCCA R11 2 4 3 1 2 CAN0_TX_5V 39 0.5% BA 1/16 W J4 2 5 U3 GND DIR 39 0.5% DSUB9-761918-A 1/16 W +5V 4 5 RXD VREF 74LVC1T45 1 5 TXD 3 9 VCC
NC_RESERVED1 4 9
2 C114 NC_RESERVED2 8 45 +3.3V +5V 0.1 UF +3.3V 3 8 10% 2 7 CAN0_CANH 7 3 1 16 V GND CANH +5V 8 6 CAN0_CANL 2 7 RS CANL
1 2 2 C130 1 C121 6 R130 0.1 UF 0.1 UF 1 PCA82C251T NC_RESERVED3 1 6 1 K 10% 10% 0.5% 1 16 V 2 16 V R10 1 1 K 10 2 U6 0.5% 11 6 1 2 CAN0_RS VCCB VCCA R9 2 4 3 1 2 CAN0_RS_5V B A 2 5 GND DIR 39 0.5% 1/16 W 74LVC1T45
C11 12
0.1 UF 10% 50 V
1 The NXP PCA82C251T CAN transceiver requires 5 V logic levels. The reference carrier board uses external discrete buffers to translate 3.3 V FPGA lines to 5 V logic levels.
2-16 | ni.com NI sbRIO-9651 System on Module Carrier Board Design Guide
Reference Schematic Design Considerations Table 2-8 lists design considerations for the schematic shown in Figure 2-5
Table 2-8. CAN0 Reference Schematic Design Considerations
Consideration Notes
CANx_RX, • The recommended CAN transceiver requires 5 V I/O. CAN _TX, and x • U2, U4, and U6 provide level translation between the 3.3 V I/O on the CANx_RS sbRIO-9651 SOM and the 5 V I/O on the transceiver. Use caution when implementing this level translation. • The TXD and RS inputs of the CAN transceiver must remain high during power-down and power-up of the sbRIO-9651 SOM and carrier board. This prevents glitches on the CAN bus that might disrupt communication between other devices on the bus. The level translator IC in this schematic prevents these glitches. • The level translator output remains at high impedance until both of its power supply rails are powered to allow the 5 V power supply to power-up before the 3.3 V power supply. • All signals have series termination at the outputs to prevent over- or under-shoot at the receivers. • FPGA DIO signals from DIO Bank 0 include series termination on the sbRIO-9651 SOM. Use series termination at the SEARAY connector on all signals outside of Bank 0 being driven from the sbRIO-9651 SOM to the CAN transceiver.
CANx_CANH • Route these signals differentially with a 120 Ω differential trace and impedance. CANx_CANL • Minimize the overall length of the traces so that you can place termination resistors in the CAN cabling as close as possible to the CAN transceiver. • Depending on your design requirements, you can also place the CAN termination resistor on the carrier board.
© National Instruments | 2-17 Chapter 2 User-Defined FPGA Signals Termination Resistors for CAN Cables The termination resistors should match the nominal impedance of the CAN cable and therefore comply with the values in Table 2-9.
Table 2-9. Termination Resistor Specification
Characteristic Value Condition
Termination resistor 100 Ω minimum Minimum power 120 Ω nominal dissipation: 220 mW 130 Ω maximum
2-18 | ni.com 3 Carrier Board PCB Layout Guidelines
Use the guidelines in this chapter to help you arrange the I/O signals you implement in your carrier board design. Impedance-Controlled Signaling
Use the following guidelines for implementing impedance for all I/O signals: • All signals connected to the sbRIO-9651 SOM must use impedance-controlled traces. Refer to the sections of this document listed in Table 3-1 for information about impedance requirements.
Table 3-1. Impedance Requirements Resources
Impedance Requirement Resource
General requirements for single-ended Single-Ended Signal Best Practices section of this signals chapter
General requirements for differential Differential Signal Best Practices section of this signals chapter
Signal-specific requirements Signal-specific sections in Chapter 1, Fixed Behavior Signals, or Chapter 2, User-Defined FPGA Signals
• Trace geometry to meet impedance requirements vary depending on your specific carrier board PCB stack-up. Collaborate with your vendor to match impedance requirements, stack-up, and trace geometry appropriate for your application. • To properly maintain trace impedance and avoid discontinuities, you cannot route traces over gaps in the reference plane. Use stitching vias and capacitors when appropriate near layer changes to provide a transient return path between reference planes.
© National Instruments | 3-1 Chapter 3 Carrier Board PCB Layout Guidelines Single-Ended Signal Best Practices
Use the following guidelines for implementing single-ended I/O signals: • Route all single-ended signals that are implemented on your carrier board and connected to the sbRIO-9651 SOM with 50 Ω characteristic trace impedance. • Maintain at minimum a 2 × H line spacing between single-ended traces, where H is the distance in the board stack-up from the trace to its reference plane. • When you configure FPGA DIO signals from DIO Bank 1, 2, or 3 as single-ended traces, observe the following guidelines: – Use the DIO_x positive signals first because those signals have slightly lower crosstalk in the J1 connector on the sbRIO-9651 SOM than the DIO_x negative (DIO_x_N) signals. – To minimize crosstalk when using the DIO_x_N signals, ensure that you implement corresponding positive and negative signals in the same direction. For example, if you are using DIO_16 and DIO_16_N, implement both signals as inputs or both as outputs. Avoid implementing one as an input and the other as an output. – To improve signal integrity on the carrier board, place series termination resistors on outputs from the sbRIO-9651 SOM as close to the mating connector as possible.
Note FPGA DIO signals from DIO Bank 0 include series termination resistors near the Xilinx Zynq SoC on the sbRIO-9651 SOM. Refer to the FPGA DIO section of the NI sbRIO-9651 System on Module OEM Device Specifications for more information. Differential Signal Best Practices
Use the following guidelines for implementing differential I/O signals: • Route all differential signals that are implemented on your carrier board and connected to the sbRIO-9651 SOM—other than USB data pair signals—with 100 Ω differential trace impedance. Route USB data pair signals with 90 Ω differential trace impedance. • Maintain at minimum a 3 × H spacing between differential pairs and any other copper features on the same layer, where H is the distance in the board stack-up from the trace to its reference plane.
3-2 | ni.com NI sbRIO-9651 System on Module Carrier Board Design Guide Ground and Power Plane Recommendations
Use the following guidelines for implementing ground and power planes: • You must include ground planes on your carrier board. All GND pins on the J1 connector of the sbRIO-9651 SOM must connect to the carrier board ground planes. • If possible, use planes to connect power to the sbRIO-9651 SOM. All power pins on the J1 connector of the sbRIO-9651 SOM must be connected and powered, even if a bank of DIO is unused. Fanout and Layout Options
Refer to Samtec SEARAY documentation for information about possible fanout and layout options with various layer count carrier boards.
© National Instruments | 3-3 4 Mechanical Considerations
Proper mechanical design is critical for rugged environments in which the sbRIO-9651 SOM may be subjected to extreme temperatures, shock, vibration, and other factors. In particular, pay special attention to thermal performance to ensure that your application meets the sbRIO-9651 SOM operating requirements. Mounting
You can mount the sbRIO-9651 SOM and carrier board in a variety of ways in order to maximize system performance. Some mounting methods might require custom fasteners or unique assembly techniques to maintain required connector stack heights and enable improved thermal and structural design for rugged environments. Selecting an Appropriate Mating Connector The J1 connector on the sbRIO-9651 SOM is a Molex 45971-4185 320-pin, 8 × 40 position, SEARAY open-pin-field-array connector. To interface with the J1 connector, your carrier board design must implement a mating connector that is compatible with the Molex 45971 series or Samtec SEAF series. Table 4-1 lists compatible mating connectors, such as the Molex 45970 series or Samtec SEAM series.
Table 4-1. sbRIO-9651 SOM Connector and Compatible Mating Connectors
Connector Manufacturer, Part Number
sbRIO-9651 SOM J1 connector Molex, 45971-4185 (equivalent to Samtec SEAF-40-05.0-S-08-2-A-K-TR) Recommended mating connector* Molex, 45970-4130 Alternative 7-mm stack height mating Molex, 45970-4185 connectors Samtec, SEAM-40-02.0-S-08-2-A-K-TR
* Compatible connectors are available in multiple stack height and termination options. NI has secured a special Molex connector part number, 45970-4130, with a 7-mm mated pair stack height. Refer to the Ordering the Recommended Mating Connector section of this chapter for information about ordering connectors. Consult Molex or Samtec for alternative stack heights and terminations.
© National Instruments | 4-1 Chapter 4 Mechanical Considerations
Ordering the Recommended Mating Connector The recommended mating connector is distributed through TTI, Inc. at NI-negotiated pricing and with shortened lead times. Complete the following steps to order individual bulk or reel quantities of the mating connector. 1. Visit www.ttiinc.com. 2. Search for the 45970-4130 part number. Table 4-2 describes the available parts. 3. Contact TTI, Inc. directly and request NI pricing when obtaining a quote. You may also be able to place an order directly from the TTI, Inc. website.
Table 4-2. Orderable Mating Connector Parts from TTI, Inc.
Part Number Description
45970-4130 A packaged reel of 300 connectors. 45970-4130 BULK One or more individual connectors.
Note These recommended connectors are available only from TTI, Inc. distribution centers located in the United States but can be shipped internationally. Customers outside the U.S. should contact a U.S.-based distribution center and request international shipping.
Note Online pricing might not reflect negotiated pricing. Selecting Appropriate Standoffs The Molex 45970 series and Samtec SEAM series connectors are available in multiple heights. The height of the mating connector you select determines the height of the standoffs you need.
To prevent over-insertion, the SEARAY connector design requires that standoffs never be less than the stack height. Because standard nominal tolerances might result in a standoff being shorter than the stack height, NI requires that you use standoffs that are 0.15 mm (0.006 in.) taller than the combined height of the J1 connector on the sbRIO-9651 SOM and the mating SEARAY connector. Therefore, to determine the required standoff height, you must add the heights of the mated connectors plus an additional 0.15 mm (0.006 in.). Refer to Samtec documentation for more information about SEARAY standoff requirements.
4-2 | ni.com NI sbRIO-9651 System on Module Carrier Board Design Guide
Table 4-3 provides an example standoff height calculation using a Molex 45970-4130 mating connector.
Table 4-3. Example Connector Configuration and Calculated Standoff Height
Manufacturer, Component Part Number Height
J1 connector on the sbRIO-9651 SOM Molex, 45971-4185 5.00 mm (0.197 in.) Mating connector Molex, 45970-4130 2.00 mm (0.079 in.) Required additional standoff height — 0.15 mm (0.006 in.)
Total calculated standoff height — 7.15 mm (0.281 in.)
NI Custom Standoffs NI offers a custom standoff that is an exact fit with the recommended or other compatible 7-mm stack height mating connectors listed in Table 4-1. This custom M3 × 7.15 mm (0.281 in.) is made from 4.5 mm (0.177 in.) stainless steel hex stock and includes a nylon threadlock patch. The external threads extend 4.78 mm (0.188 in.) and the internal threads are 5 mm (0.197 in.) deep. Table 4-4 lists orderable quantities of this custom standoff.
Table 4-4. Custom M3 × 7.15 mm (0.281 in.) Standoff Kits
Quantity Manufacturer, Part Number
20 NI, 157543-020 500 NI, 157543-500
NI recommends that you use stainless steel fasteners for good corrosion resistance and strength. Tighten M3 fasteners to a torque of 0.76 N · m (6.70 lb · in), unless otherwise noted or required by your specific design constraints.
© National Instruments | 4-3 Chapter 4 Mechanical Considerations Mounting Direction Options Figures 4-1 through 4-3 show possible mounting configurations and associated fastener types. Mounting on a Panel or Plate (Recommended) If possible, NI recommends that you mount the sbRIO-9651 SOM on a panel or plate, as shown in Figure 4-1. Figure 4-1. Mounting on a Panel or Plate
1 2
4 3
5
6 7 8
1 Exploded view of all mounting components 5 Mounting surface 2 Complete assembled and mounted view 6 Mounting screw, panel thickness + 3 Standoff, 15.00 mm (0.591 in.) 12.00 mm (0.472 in.) 4 Carrier board 7 sbRIO-9651 SOM 8 Standoff, 7.15 mm (0.281 in.)
The sbRIO-9651 SOM was designed so that you can use the 15.00 mm (0.591 in.) standoffs between the carrier board and the base panel when the 7.15 mm (0.281 in.) standoffs are used between the carrier board and the sbRIO-9651 SOM, as shown in Figure 4-1.
4-4 | ni.com NI sbRIO-9651 System on Module Carrier Board Design Guide
This method accommodates a layer of thermal grease that is 0.08 mm (0.003 in.) thick between the aluminum heat spreader of the sbRIO-9651 SOM and the metal base panel. However, thicker thermal interface materials may require different lengths of standoffs or mounting bosses. The direction of fastening may also require custom lengths or types of fasteners and might impact ease of assembly. Mounting on a Panel or Plate with Flathead Screws Alternatively, use flathead screws when mounting on a panel or plate, as shown in Figure 4-2. Figure 4-2. Mounting on a Panel or Plate with Flathead Screws
1 2
4
3 5
6 7
1 Exploded view of all mounting components 5 Mounting screw, 12.00 mm (0.472 in.) 2 Complete assembled and mounted view 6 Standoff, 7.15 mm (0.281 in.) 3 Mounting surface 7 sbRIO-9651 SOM 4 Carrier board
Mounting on a Panel or Plate with an Attached Heat Sink Your system design might require you to attach a heat sink or other thermal solution described in the Mounting Recommendations for Maximizing Thermal Performance section of this chapter. Figure 4-3 shows standoffs and fasteners that are compatible with the AlphaNovatech S01LZZ0E-A heat sink that is included in the sbRIO-9651 SOM development kit.
© National Instruments | 4-5 Chapter 4 Mechanical Considerations
Figure 4-3. Mounting on a Panel or Plate with an Attached Heat Sink
1 2
4
3
5 6 7
1 Exploded view of all mounting components 5 Standoff, 7.15 mm (0.281 in.) 2 Complete assembled and mounted view 6 sbRIO-9651 SOM 3 Mounting surface 7 Mounting screw, 16.00 mm (0.630 in.) 4 Carrier board Managing Thermal Conditions
Due to the compact size of the sbRIO-9651 SOM, it is very important to appropriately dissipate the heat generated during operation. You must plan for the thermal conditions of your application throughout development and validation. This section provides design recommendations and validation tools and methods for maximizing the thermal performance of the system. Designing a Suitable Enclosure NI sbRIO devices operate as components in a higher-level system and may require an enclosure to protect the internal circuit card assembles and dissipate heat. For the sbRIO-9651 SOM, the system integrator is responsible for designing an enclosure that meets the thermal requirements of your specific application.
4-6 | ni.com NI sbRIO-9651 System on Module Carrier Board Design Guide
NI sbRIO devices integrated into an enclosure or system with proper thermal dissipation can be deployed in high- and low-temperature environments. However, the 85 °C local ambient operating temperature rating of the sbRIO-9651 SOM does not mean that the external temperature of the natural convection environment such as a room or larger enclosure can be 85 °C. In this way, properly designed NI sbRIO devices may still require an external ambient temperature of 70 °C or less and may still require specific mounting requirements to ensure that the local ambient and thermally-relevant component maximum operating temperatures are within specification. Understanding Thermal Specifications A deployed system has several temperature measurement locations that indicate the thermal performance of the system and the devices the system contains. For example, in a natural convection system, the temperature of a critical component will be higher than the temperature of the air in the immediate vicinity of the component. This local air temperature will also be higher inside an enclosure than in the room ambient that surrounds the enclosure.
Figure 4-4 identifies these types of ambient temperatures. Figure 4-4. Ambient Temperatures
1 2
3
4 5 6
1 External ambient temperature 4 sbRIO-9651 SOM 2 Internal/enclosure ambient temperature 5 Local ambient temperature 3 Carrier board 6Enclosure
© National Instruments | 4-7 Chapter 4 Mechanical Considerations
• External ambient—The maximum air temperature of the room or installation location that surrounds the system. • Internal/enclosure ambient—The maximum air temperature inside the enclosure. This can be measured at various locations within the enclosure and is highly influenced by the proximity and dissipation of devices inside the enclosure. • Local ambient—The maximum air temperature as specified directly adjacent to the NI sbRIO device. This is measured on all sides of a device that has exposed circuitry. Because the sbRIO-9651 SOM has an integrated heat spreader on the primary side, only the secondary side needs to be measured.
Because the system integrator may use any number of enclosure sizes, materials, thermal solutions, and room conditions when designing an enclosure for a specific application, NI sbRIO devices are specified in a manner that removes most of these external variables. Therefore, the sbRIO-9651 SOM thermal performance is not determined by measuring the external ambient or internal/enclosure ambient temperatures, but by measuring the local ambient and specific component temperatures. NI provides digitally reported temperatures to help you accurately measure these critical temperatures. Validating the System
NI recommends that you use a validation system for an extended period of time in a test environment with the same thermal, environmental, and functional utilization characteristics as the target deployment environment. You are responsible for final validation of your application. Validating Temperature Measurements The sbRIO-9651 SOM includes three onboard temperature-monitoring sensors to simplify validation of a thermal solution, as shown in Figure 4-5. The sensors provide an indication of thermal performance and are used to validate the system along with the local ambient operating temperature.
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Figure 4-5. Onboard Temperature-Monitoring Sensors
1 2
3
1 CPU/FPGA sensor 2 Primary System sensor 3 Secondary System sensor
• CPU/FPGA sensor—Digitally reports the die junction temperature of the Xilinx Zynq SoC. • Primary System sensor—Digitally reports the temperature on the Xilinx Zynq SoC side of the circuit card assembly underneath the integrated heat spreader. This value is an approximation of the local ambient temperature inside the heat spreader. • Secondary System sensor—Digitally reports the temperature on the SEARAY side of the circuit card assembly. This value is a conservative approximation of the local ambient temperature on that side of the circuit card assembly.
To meet the thermal specifications described in the NI sbRIO-9651 System on Module OEM Device Specifications, you must record the following measurements: • The CPU/FPGA reported temperature, which must not exceed 98 °C • The Primary System reported temperature, which must not exceed 85 °C • The local ambient operating temperature near the device, which must not exceed 85 °C
Measure the local ambient temperature by placing a thermocouple near the center of the printed circuit board 5 mm (0.2 in.) from the board surface. Alternatively, you can rely on the reported Secondary System temperature to provide a conservative estimate of the local ambient
© National Instruments | 4-9 Chapter 4 Mechanical Considerations temperature. This alternative method provides a completely digital validation scheme that does not require using a thermocouple and allows you to validate the sbRIO-9651 SOM as part of every deployment.
In addition to being useful for system validation, digitally reported temperatures also provide feedback about system health and can be used as triggers or set points. The TEMP_ALERT signal from the J1 connector on the sbRIO-9651 SOM asserts when the CPU/FPGA or Primary System reported temperatures exceed specification. However, you should not use the TEMP_ALERT signal in place of proper system validation because the TEMP_ALERT signal does not monitor the Secondary System or local ambient temperatures. Refer to the Temp Alert section of Chapter 1, Fixed Behavior Signals, for more information about the TEMP_ALERT signal.
NI recommends that you monitor the digitally reported temperatures on deployed systems, especially if the temperatures approach the maximum thermal specifications during system validation testing. Monitoring allows individual systems to identify adverse thermal changes caused by differences in environmental, operating, or process conditions.
For more information about how to access and use the digitally reported temperature sensor measurements, visit ni.com/info and enter the Info Code sbriosensors. Managing Power and Feature Utilization An sbRIO-9651 SOM that heavily utilizes all of its performance and features consumes and dissipates substantially more power than when the device is idle. Certain features, such as LVDS outputs, can greatly increase the power that the Xilinx Zynq SoC dissipates and therefore also quickly raise the die junction temperature.
Consider the following options for reducing the die junction temperature: • Design for additional thermal cooling that can appropriately dissipate power • Reduce device feature utilization
Note Your final validation must consider software and hardware utilization that is representative of the final deployment conditions.
Note Refer to the Input Power Requirements section of the NI sbRIO-9651 System on Module OEM Device Specifications for specifications that approximate the maximum power requirement for each input rail on an sbRIO-9651 SOM with worst-case silicon manufacturing process and maximum junction temperatures. For a more accurate estimate of the power consumption for a specific application, NI recommends that you directly measure the power the sbRIO-9651 SOM consumes when running your application in an environment that is representative of the intended use case. You can use the Xilinx Power Estimator to calculate the VIO_BANK input rail power for a given configuration.
4-10 | ni.com NI sbRIO-9651 System on Module Carrier Board Design Guide Mounting Recommendations for Maximizing Thermal Performance The sbRIO-9651 SOM includes an integrated heat spreader that uses a thermal gap filler material to effectively conduct into the spreader the heat that the circuit card assembly components generate. NI recommends the following mounting procedures for maximizing the thermal performance of your application: • Directly mount the flat and smooth exterior surface of the integrated heat spreader to a thermally-conductive surface, such as a metal enclosure wall or plate, as shown in Figure 4-1. An interface material such as thermal grease should be used to maximize the heat transfer from the integrated heat spreader to the enclosure or plate. The enclosure or plate conducts and convects the heat to the external ambient environment. If design limitations prevent this solution, you can alternatively attach a heat sink or other thermal solution to the integrated heat spreader, as shown in Figure 4-3. This solution takes advantage of natural convection or forced convection cooling provided by a fan. • Mount the sbRIO-9651 SOM vertically with respect gravity to take advantage of natural convection cooling. • Mount the sbRIO-9651 SOM below and away from other heat-dissipating components.
Note Placing the sbRIO-9651 SOM within a system or enclosure will also influence thermal performance.
Figure 4-6 shows good, better, and best thermal mounting solutions for the sbRIO-9651 SOM. Figure 4-6. Thermal Mounting Solutions Comparison
1 2 3
1 Good—Horizontal mounting with no additional thermal provisions 2 Better—Vertical mounting with an attached heat sink, as described in Figure 4-3 3 Best—Vertical mounting directly to a thermally-conductive wall or plate, as described in Figure 4-1
© National Instruments | 4-11 Chapter 4 Mechanical Considerations Additional Resources for Managing Thermal Conditions Visit ni.com/info and enter the Info Code sbriocooling for the following additional information to help you manage thermal conditions: • Examples regarding the effect of the design factors discussed in this chapter • Case study examples to help you estimate the achievable external ambient temperature for a representative system Shock and Vibration
The mounting method you use, components you select, and assembly techniques you use influence the ability of the system to resist fretting corrosion and other damage caused by exposure to shock and vibration. Consider the following factors when designing your sbRIO-9651 SOM system to account for shock and vibration: • In general, shorter SEARAY stack heights perform better than taller stack heights. • Directly mounting the sbRIO-9651 SOM heat spreader to a rigid surface provides the best performance. If this method is not feasible for your design, minimize the amount of extra mass that only the sbRIO-9651 SOM supports, such as a heat sink or other thermal solution, that is fastened to the four standoffs. If you require substantial thermal solutions, provide additional structural support. • NI recommends that you use connectors that provide the following benefits: – Positive locking – Provisions for strain relief – Substantial gold plating on pins • The connectors on the reference carrier board are representative of connectors that NI has used and validated for high shock and vibration environments. The connectors and the sbRIO-9651 SOM have been tested to industry specifications and are recommended, where possible, for rugged environments. Exceptions to this recommendation are the barrel jack and Peripheral Module (Pmod) headers, which have designs that are not positive-locking or do not provide strain relief. • NI offers a variety of cable assemblies and other connectivity accessories to complete your system design. Typically, these accessories include the best available designs, materials, and plating to maximize performance and longevity in rugged environments.
4-12 | ni.com A Reference Carrier Board Specifications and User Guide
This appendix provides pinouts, connectivity information, and specifications for the reference carrier board included with the sbRIO-9651 SOM development kit.
The reference carrier board provides the following: • A hardware environment for developing and evaluating designs that target the sbRIO-9651 SOM. • Access to most of the onboard peripherals available on the sbRIO-9651 SOM, including Ethernet, serial RS-232 and RS-485, USB Device, USB Host, SD card, and FPGA I/O. • Additional supported capability through five Pmod connectors on the breadboard circuit prototyping area.
Note Visit ni.com and search for 9651 for the reference carrier board schematic and PCB gerber files. Parts Locator Diagram and Block Diagram
Refer to the NI sbRIO-9651 System on Module Development Kit Quick Start Guide for the reference carrier board parts locator diagram and hardware block diagram. Specifications
The following specifications are typical and not guaranteed.
Note Refer to the NI sbRIO-9651 System on Module OEM Device Specifications for complete specifications for each interface the sbRIO-9651 SOM supports. The specifications listed in this section pertain only to the interfaces implemented on the reference carrier board.
© National Instruments | A-1 Appendix A Reference Carrier Board Specifications and User Guide Ethernet The reference carrier board includes the following tri-mode Ethernet ports: • Ethernet0—Utilizes the primary Ethernet (GBE0) fixed behavior interface from the sbRIO-9651 SOM. • Ethernet1—Implemented from the secondary Ethernet user-defined FPGA interface. Serial
Number of ports TX/RX-only RS-232 1 (Serial1) Full-modem RS-232 1 (Serial2) RS-485 1 (Serial5)
CAN
Number of CAN ports 1 (CAN0)
SD Card
Number of full-size SD card sockets 1 (J2)
Refer to SanDisk Corporation or SD Association websites for information about SD I/O card specifications. USB
Number of ports USB Device 1 (USB0) USB Host 1 (USB1) USB Host maximum current 900 mA (supports USB3 Vision cameras)
Pmod The Pmod standard is defined by Digilent, Inc. and is used for small I/O interface boards that extend the capabilities of FPGA control boards. Pmods communicate with system boards via 6- or 12-pin connectors. The reference carrier board provides Pmod-compatible connectors to support quick connectivity to the Pmod ecosystem for prototyping and evaluating sensors, converters, connectors, and other devices.
A-2 | ni.com NI sbRIO-9651 System on Module Carrier Board Design Guide
Note Refer to the Digilent website at www.digilentinc.com for more information about Pmods.
Number of ports Pmod 12-pin 4 (Pmod1, Pmod2, Pmod3, Pmod4)
Pmod I2C 1 (Pmod5) Pmod Vcc Volt age 3.3 V Current 100 mA
Pmod Signal Definitions on the Reference Carrier Board Table A-1 describes the pins and signals on the sbRIO-9651 SOM connector used to implement four Pmod 12-pin connectors.
Note Refer to the Pmod 12-Pin Connector Pinout section of this chapter for more information about the Pmod 12-pin connector pins and signals on the reference carrier board.
Table A-1. Pmod 12-pin Connector Signal Definitions
Signal Name* Pin # DIO Signal Signal Name* Pin # DIO Signal
PMOD1_PIN1 114 DIO_20_N PMOD2_PIN1 164 DIO_28_N PMOD1_PIN2 90 DIO_19_N PMOD2_PIN2 131 DIO_23 PMOD1_PIN3 122 DIO_20 PMOD2_PIN3 172 DIO_28 PMOD1_PIN4 98 DIO_19 PMOD2_PIN4 139 DIO_23_N PMOD1_PIN7 138 DIO_21_N PMOD2_PIN7 107 DIO_22 PMOD1_PIN8 146 DIO_21 PMOD2_PIN8 155 DIO_24 PMOD1_PIN9 153 DIO_18 PMOD2_PIN9 115 DIO_22_N PMOD1_PIN10 161 DIO_18_N PMOD2_PIN10 163 DIO_24_N PMOD3_PIN1 148 DIO_27 PMOD4_PIN1 135 DIO_37_MRCC PMOD3_PIN2 116 DIO_26_N PMOD4_PIN2 111 DIO_36_SRCC PMOD3_PIN3 140 DIO_27_N PMOD4_PIN3 143 DIO_37_N PMOD3_PIN4 124 DIO_26 PMOD4_PIN4 119 DIO_36_N PMOD3_PIN7 92 DIO_25_N PMOD4_PIN7 159 DIO_38_MRCC PMOD3_PIN8 109 DIO_29 PMOD4_PIN8 167 DIO_38_N PMOD3_PIN9 100 DIO_25 PMOD4_PIN9 142 DIO_34_N PMOD3_PIN10 117 DIO_29_N PMOD4_PIN10 150 DIO_34
* All signals have both I/O directions and comply with the LVTTL I/O standard.
© National Instruments | A-3 Appendix A Reference Carrier Board Specifications and User Guide
Table A-2 describes the specific pins and signals on the sbRIO-9651 SOM connector used to implement a Pmod I2C connector.
Note Refer to the Pmod I2C Connector Pinout section of this chapter for more information about the Pmod I2C connector pins and signals on the reference carrier board.
Table A-2. Pmod I2C Connector Signal Definitions
Signal Name* Pin # DIO Signal
PMOD_I2C_SCL1 105 DIO_16 PMOD_I2C_SCL2 129 DIO_17 PMOD_I2C_SDA1 113 DIO_16_N PMOD_I2C_SDA2 137 DIO_17_N
* All signals have both I/O directions and comply with the LVTTL I/O standard.
RTC Battery The reference carrier board provides a battery backup for the RTC on the sbRIO-9651 SOM. Support Signals The reference carrier board implements support signals in the following ways: • STATUS_LED and TEMP_ALERT signals are routed to user-visible LEDs. • SYS_RST# is connected to a Reset push button. Connector Pinouts
RS-232, RS-485, and CAN Connector Pinouts The RS-232, RS-485, and CAN connectors on the reference carrier board use the port shown in Figure A-1. Table A-3 describes the pins and signals on each port. Figure A-1. RS-232, RS-485, and CAN Port Pin Locations
Pin 1 Pin 6
Pin 9 Pin 5
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Table A-3. RS-232, RS-485, and CAN Port Pins and Signals
TX/RX-only Full-modem RS-232 RS-232 RS-485 CAN
Pin Signal Pin Signal Pin Signal Pin Signal
1 NC 1 DCD 1 GND 1 NC 2 RXD 2 RXD 2 NC 2 CANL 3 TXD 3 TXD 3 NC 3 GND 4 NC 4 DTR 4 RXP 4 NC
5 GND 5 GND 5 RXN 5 SHIELD 6 NC 6 DSR 6 NC 6 GND 7 NC 7 RTS 7 NC 7 CANH 8 NC 8 CTS 8 TXP 8 NC 9 NC 9 RI 9 TXN 9 NC
Pmod 12-Pin Connector Pinout The Pmod 12-pin connectors on the reference carrier board use the port shown in Figure A-2. Table A-4 describes the pins and signals on the port. Figure A-2. Pmod 12-Pin Port Pin Locations
6 45 3 2 1 12 1011 9 8 7
Table A-4. Pmod 12-Pin Port Pins and Signals
Pin Signal Pin Signal
1 PMODx_PIN1 7 PMODx_PIN7 2 PMODx_PIN2 8 PMODx_PIN8 3 PMODx_PIN3 9 PMODx_PIN9 4 PMODx_PIN4 10 PMODx_PIN10 5 GND 11 GND 6 3.3 V power 12 3.3 V power
© National Instruments | A-5 Appendix A Reference Carrier Board Specifications and User Guide Pmod I2C Connector Pinout The Pmod I2C connector on the reference carrier board uses the port shown in Figure A-3. Table A-5 describes the pins and signals on the port. Figure A-3. Pmod I2C Port Pin Locations
2864 1 3 75
Table A-5. Pmod I2C Port Pins and Signals
Pin Signal Pin Signal
1 PMOD5_SCL1 5 GND 2 PMOD5_SCL2 6 GND 3 PMOD5_SDA1 7 3.3 V power 4 PMOD5_SDA2 8 3.3 V power Environmental Management
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For additional environmental information, refer to the Minimize Our Environmental Impact web page at ni.com/environment. This page contains the environmental regulations and directives with which NI complies, as well as other environmental information not included in this document. Waste Electrical and Electronic Equipment (WEEE) EU Customers At the end of the product life cycle, all products must be sent to a WEEE recycling center. For more information about WEEE recycling centers, National Instruments WEEE initiatives, and compliance with WEEE Directive 2002/96/EC on Waste and Electronic Equipment, visit ni.com/environment/ weee. Battery Replacement and Disposal Battery Directive This device contains a long-life coin cell battery. If you need to replace it, use the Return Material Authorization (RMA) process or contact an Cd/Hg/Pb authorized National Instruments service representative. For more information about compliance with the EU Battery Directives 2006/66/EC about Batteries and Accumulators and Waste Batteries and Accumulators, visit ni.com/ environment/batterydirective.
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© National Instruments | A-7 B Revision History
Table B-1 lists changes to this document since its first iteration.
Table B-1.
Revision Edition Date Changes
B August 2015 • Added information about eliminating the effects of contact bounce to the Eliminating the Effects of Contact Bounce section of Chapter 1, Fixed Behavior Signals. • Added more information about ordering the recommended mating connector (Molex, 45970-4130) from TTI, Inc. to the Ordering the Recommended Mating Connector section of Chapter 4, Mechanical Considerations. A December 2014 —
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