System and Silicon Challenges Portable Devices

• Minitiarutization • Price Erosion

2 Wearable Electronics

Electronic Societal Comfort 3 Biometrics and Implantables

Taking your meds? Sensors will know High Impact High-tech monitors, Webcams and GPS devices can help caregivers check in on elderly parents--from afar. Photos: Home monitoring Video: Long-distance eldercare July 5, 2007, 4:00 AM PDT shares source code with AIDS researchers Researchers hope to use four specialized software tools to identify genetic patterns that could help development of HIV vaccine. June 13, 2007, 9:19 AM PDT Managing the meds from miles away High Impact An increasing number of baby boomers are turning to technology to help keep track of their aging parents' medication. Photos: Tech lends hand to med management June 5, 2007, 4:00 AM PDT Revolutionary mechanical arm provides grip, feel Team lead by Applied Physics Laboratory has come up with a prosthetic breakthrough, giving fine motor skills and sensory perception to amputees. Photos: Testing the prosthetic arm April 27, 2007, 12:32 PM PDT This is your brain on TED A neurologist explains synesthesia--a cross-wiring of the senses of hearing, vision and touch. Is this how poetry is born? March 12, 2007, 4:16 AM PDT London hospital rolls out Wi-Fi tracking System combines Wi-Fi and wireless chip technology to help hospital staff quickly locate equipment. February 20, 2007, 6:25 AM PST

4 System Drivers

• Portable Consumer Electronics – Low power paramount – Need SOC integration (DSP, MPU, I/O cores, etc.) • Medical – High-end products only. – Reprogrammability possible. – Mainly ASSP, especially for patient data storage and telemedicine; – more SOC for high-end digital with cores for imaging, real-time diagnostics, etc. • Automotive – Mainly entertainment systems. – Mainly ASSP, but increasing SOC for high end using standard HW platforms with RTOS kernel, embedded software. • Office – Large gate counts – High speed Drives demand for digital functionality – Primarily SOC integration of custom MPUs and I/O cores • Networking and Communications – Large gate counts – High reliability – More reprogrammability to accommodate custom functions 5 Semiconductor Cycles

6 Fab Facts

• Cost of fab – $3b + • Running cost – extremely high (water, electricity, special gases, waste (toxic gases, phosphorus) management, environmental clearances • Class 1 (spec of clean room air - < 1 dust particle per cm2 of a size less than 0.1um) • Cycle time – 6 to 8 weeks

Crolles Alliance

7 Fab Mix-Production

• Running > 3 technology generation concurrently in the same Fab • Running > 10 process flows within the same technology generation • Running > 50 products concurrently through the manufacturing line • High mix is at least 5 large volume products (product flows) with no one product has >50% of production volume • Customers want new and volume products delivered quickly • Manufacturers need to have low wafer cost and do not want to sacrifice factory efficiency to achieve speed 8 Fab Complexity and Cost

100000 10 Fab Cost ($M)

Linewidth (nm) 10000

1 1000

100 Fab Cost ($M) 0.1 (um) Linewidth

10

100mm 150mm 200mm 300mm 450mm 1 0.01 1975 1980 1985 1990 1995 2000 2005 2010 2015 2020 2025

9 Mask Set Costs

Baseline CMOS mask set cost Development 800

600

400

200 Maskset Cost [k$] Cost Maskset 0 0.50 0.35 0.25 0.18 0.15 0.12 0.10 0.07 Technology Node

10 Utilization and Capacity

Production Lot Cycle Time

Average duration, expressed in fractional working days, consumed only by fastest class of full flow priority lots of wafers from time of release into the fab until time of exit from the fab: Exit includes final parametric test and wafer processes after final parametric test up to die probe/sort, divided by the number of photo wafer layers in the process flow.

11 FAB Utilization

Historically, for fab utilization, every time inventories climb, utilization drops as manufacturers pull back production levels to handle inventory increases12 Foundries: Adoption Rate By Process

[Nick Tredennick] 13 Factory Investment Issues • $3B min. revenue for • $7B min. revenue to own partnering for a 300mm fab a 300mm fab

Intel 23,850 30,400 • One company that can Toshiba 6,781 11,388 6,359 clearly do it alone STMicroelectronics 7,910 6,100 9,200 5,814 Samsung 10,592 NEC 5,309 10,900 Hitachi 5,037 • Companies with annual 7,286 Motorola 4,828 7,875 revenue between $3B Infineon 4,558 6,853 4,235 and $7B can either Philips 5,837 3,898 IBM 4,329 2000 revenues 3,891 AMD 4,644 – Outsource to 3,473 Mitsubishi 4,740 2001 revenues foundry Matsushita 3,176 4,150 Fujitsu 3,084 4,470 – Partner with Agere (Lucent Tech.) 3,051 4,875 Sanyo 2,675 3,260 Hynix 2,450 another company 6,400 2,411 Micron 6,314 (to achieve 2,100 Sony 2,817 1,897 2,710 economy of scale) 1,858 Sharp 2,550 Agilent 1,671 2,414 National Semi. 1,626 2,301 LSI Logic 1,597 2,448 Rohm 1,591 2,240 1,472 2,013 • IC companies with 1,407 1,521 1,216 revenues of less than 1,393 735 1,370 $3B typically need to 2,013 On Semiconductor 1,206 1,559 1,149 seek a foundry partner 847 1,110 Maxim for their wafer 1,010 Elpida 884 Via Technologies 980 fabrication needs 1,528 Oki 966 1,126 Broadcom 961 2,004 Conexant 881 991 ATI Technologies 848 1,380 Altera 839 1,220 812 Cypress 946 801 International Rectifier 1,172 780 Seiko Epson 886 723 Linear Technology 921 614 Source: Gartner, McKinsey analysis Macronix 587 609 741 Cirrus Logic 522 976 14 506 Integrated Device Tech. 757 481 Intersil 948 Winbond 441 15000 Design Strategy Processing complexity Transistor ULSI WSI count

VLSI

Cost Not profitable LSI IC Area

profitable

IC Yield 15 Design Activity

http://www.semiconductor.net/article/CA6589587.html?desc=topstory

Design expenditures are growing, but the number of designs is declining. “This means a drop in differentiation and value,” he warned. “At present, the value of silicon for the U.S. semiconductor industry is three times what it is in rest of the world because there is a high degree of differentiation. If we cannot design we’re in trouble because, as designs decline, so do revenues and ASPs.” Dan Hutcheson, CEO of VLSI RESEARCH 16 Timeline Electronic Devices

VLSI (> 104 components) LSI (103 – 104 components) 2000 MSI (102 – 103 components) SSI (< 102 components)

70 LSI 10 years 60 Si-MOSFET IC IC 50 st bipolar 30 years 1 Transistor 40 30 MOSFET Transistor MISFET Concept 20 20 years 10 Triode Vacuum tube 1900 Diode 17 Early on….

1904 Fleming the vacuum diode 1906 Pickard point contact diode (Si) 1906 DeForest triode Lee De Forest J. Lilienfield The invention of the three-element vacuum tube (known as the triode) was an extremely important milestone. The addition of a third element to a diode enabled electronic amplification to take place with good isolation between the input and output ports of the device 1928 MOSFET transistor concept Triode 18 The 40’s

1947 The first integrated transistor (Bell Telephone Laboratories) John Bardeen, Walter H. Brattain, William B. Shockley

A replica of the point-contact transistor created by John Bardeen and Walter Brattain, under the supervision of William Shockley in 1947. Courtesy: Lucent

19 The 50’s…

1951 Industrial production of the bipolar transistor dev. by Shockley 1954 The first transistor-based radio Texas Instruments makes first silicon transistor (price $250) 1958 Jack S. Kilby Texas Instruments Fairchild Semiconductors The first available as a First integrated circui (Kilby) monolithic chip (flip-flop) 1959 The first bipolar planar transistor

This device, developed by Robert Noyce in the late 1950s, was the first commercially available integrated circuit. Courtesy: Fairchild Semiconductor. The first Mosfet transistor, designed by M. M. Atalla, D. Kahng, and E. Labate in late 1959. Courtesy: Lucent. 20 The 60’s Small Scale Integration (SSI), up to 20 gates per chip.

1960 Metal--Oxide--Silicon (MOS) transistor is invented. 1961 Fairchild’s first planar IC (logic chips) bought by NASA Texas Instruments’ IC version bought by the U.S. Air Force Robert Noyce 1960: First MOSFET by 1962 Transistor--transistor Logic (TTL) is D. Kahng and M. Atalla developed. 1963 Complementary Metal Oxide Silicon (CMOS) is invented. 1965 The first op-amp by Robert Widlar 1967 Fairchild markets first semicustom chip

1959: The planar bipolar transistor 1965: First opamp Semicustom chip 21 The 70’s

1971 4-bit 4004 µP – 2.300 transistors – 60.000 operations/second – 4K bytes of programmed instructions 1972 8-bit µP – 3.300 transistors (‘71) – 30.000 operations/second – addresses 16K bytes of memory 1974 - 8-bit µP – the first general-purpose µP – 4.500 transistors – 200.000 operations/second – 64K bytes of memory

Intel 8080 22 Processors in the 80’s and 90’s

Metal 2

Poly gate Metal 1 Intel 8486

Cross section – 2 level metal Am386 - ~200k transistors

Cross section – 9 level metal

Around 2002, CMOS 0.13um AMD Opteron – 100M transistors

Intel 8085 Intel 8286 23 Intel Processors

Intel Year of introduction Transistors 4004 1971 2,250 8008 1972 2,500 Metal 2 8080 1974 5,000 Poly gate Metal 1 8086 Intel 8486 1978 29,000

286Cross section – 2 level metal 1982 120,000 Am386 - ~200k386™ transistors processor 1985 275,000 486™ DX processor 1989 1,180,000 ® processor 1993 3,100,000Cross section – 9 level metal Around 2002, CMOS 0.13um Pentium II processor 1997 7,500,000AMD Opteron – 100M transistors Pentium III processor 1999 24,000,000 processor 2000 42,000,000 Intel 8286 24 Moore’s Law Electronics, April 19, 1965. 16 • In 1965, Gordon 15 14 13 Moore noted that the 12 11 number of transistors 10 9 on a chip doubled 8 7 6

every 18 to 24 OF NUMBER THE OF

2 5 4 months. LOG 3 2 1

• He made a prediction FUNCTION INTEGRATED PER COMPONENTS 0

that semiconductor 1959 1960 1961 1962 1963 1964 1965 1966 1967 1968 1969 1970 1971 1972 1973 1974 1975 technology will double its effectiveness every 18 months

25 Moore's Law

Motivation: density 10 um ↑

Modern CMOS speed ↑

functionality ↑ ↑ Beginning of Submicron CMOS cost/bit

1 um Deep UV Litho

34 Years of 90 nm in 2004 Scaling History 100 nm n Every generation Presumed Limit – Feature size shrinks by 70% to Scaling – Transistor density doubles – Wafer cost increases by 20% – Chip cost comes down by 40% 10 nm n Generations occur regularly – On average every 2.9 years over the past 34 years – Recently every 2 years 1 nm 1970 1980 1990 2000 2010 2020

Source: Dennis Buss, TI, 2005 26 Timeline of Integration

27 Beyond CMOS

Alternative devices CMOS

100

m) CMOS IC evolution

µ 10 1 0.1µm in 2002 CMOS 0.1 0.01

Feature( Size Transition Region Alternative Quantum devices 0.001 devices Atomic dimensions 1960 1980 2000 2020 2040 Year After J.D. Plummer, Proceedings of IEEE, 2001. 28 More than Moore

2005 29ITRS