Non-Volatile Memory Technology Overview Ugo Russo, Andrea Redaelli, Roberto Bez

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Ugo Russo, Andrea Redaelli, Roberto Bez. Non-Volatile Memory Technology Overview. Norm Jouppi and Yuan Xie and Eren Kursun. WTAI: Workshop on Technology Architecture Interaction, Jun 2010, Saint-Malo, France. inria-00514448

HAL Id: inria-00514448 https://hal.inria.fr/inria-00514448 Submitted on 2 Sep 2010

HAL is a multi-disciplinary open access L’archive ouverte pluridisciplinaire HAL, est archive for the deposit and dissemination of sci- destinée au dépôt et à la diffusion de documents entific research documents, whether they are pub- scientifiques de niveau recherche, publiés ou non, lished or not. The documents may come from émanant des établissements d’enseignement et de teaching and research institutions in France or recherche français ou étrangers, des laboratoires abroad, or from public or private research centers. publics ou privés. Non-Volatile Memory Technology Overview

Ugo Russo, Andrea Redaelli and Roberto Bez R&D Technology Development Numonyx Outline

• Non-Volatile Memory (NVM): from applications to technology scaling • NVM technologies: evolutions and revolutions – Flash memory and its evolution – Ferroelectric memory (FeRAM) – Magnetic memory (MRAM) – Phase Change Memory (PCM) – Resistive-switching memory (RRAM) • Summary

45000 Source: Webfeet Research, Inc. 40000

35000

30000

25000

20000 $ Millions

15000

10000

5000

0 2005 2006 2007 2008 2009 2010 NOR NAND

Coming up: Solid State Discs • Promising for low power, high performance, fast boot up • Still need system-level optimization and to reduce costs

Red blood 10000 cell

1000 Visible spectrum

100

rhinovirus Critical Size [nm] CriticalSize

10 1970 1980 1990 2000 2010 2020 Year

Source: Gary Bronner (Rambus), Stanford EE 309 lecture, Fall 2007.

Strained Si-Ge, SOI, GaAs

PCM, FeRAM, MRAM

High k dielectrics

Porous Dielectrics

Low k dielectrics, Copper

Salicide (Ti, Co, Ni, Pt?)

Barriers (Ti, TiN, WTi, TaN), Tungsten Salicide

Silicon, Oxide, Nitride, Aluminium

1.5 0.6 250 120 65 32 1.0 350 180 90 45 25 microns nanometers

1967 First Floating Gate Structure 1977 EPROM 1980 EEPROM 1985 1T EEPROM (Flash) 1988 NOR Flash 1989 NAND Flash 1995 MLC Flash

• A chargeable floating gate is introduced to tune the transistor threshold voltage

• Different physical mechanisms are used to charge/uncharge the floating gate, depending on memory architecture

Copyright © 2008 Numonyx B.V. NOR flash GND GND GND 5V GND GND N GND GND N GND GND N GND GND N GND GND GNDGND GND GND Programming: 9V • Single bit GND GND • Random access GNDGNDGND GND GND GND GND GND • High programming GND GNDGND GND GND current FLOATFLOAT FLOAT FLOATFLOAT FLOAT

-9V 5V Erase: -9V 5V • Block erase -9V 5V • Low programming -9V current 5V -9V 5V -9V 5V

Programming: 18V

• Serial access 10V 10V

• Low programming 10V 10V current 10V 10V GND

FLOAT FLOAT FLOAT FLOAT FLOAT FLOAT

FLOAT Erase: GND Body =21V Body • Block erase GND • Low programming GND current GND GND GND

FLOAT

NOR NAND

Cell size (F 2) 10 5

Read access Random Serial (fast ~50ns) Progr. Mechanism/ CHE / FN / Troughput 0.5 MB/s 7-10MB/s SEM Cross-section (BL direction)

VRead "1" "0" 1 bit/cell => 2 levels

"11" "10" "01" "00" 2 bit/cell => 4 levels

VRead Multilevel storage is widely adopted in high density memories. Trade-offs: + double density with the same technology - Slower reading and programming - more sensitive to parasitics

Cell basic structure unchanged through the different generations

Cell area scaling through : 1. Active device scaling ( W/L ) NOR y-pitch L y-pitch L 2. Passive elements scaling NAND W W Main scaling issues: x-pitch x-pitch Tunnel oxide thickness Interpoly dielectric thickness Cell gate length CG C Contact dimension/ isolation spacing ONO CFG

Cell proximity (FG-FG parasitic coupling FG C cross talk) TUN Statistical effects

The low number of electrons stored in the floating gate makes it sensitive also to the effect of single charges trapped in the tunnel dielectric.

Floating gate Several effects: Erratic bits Source Moving bits (SILC)

Random Telegraph Signal Floating gate Fast erasing bits

Source

Flash Cell Vt instability Read/verify Cell threshold instability due 0.5 to Random Telegraph 0.49 Signal (RTS) 0.48

0.47

0.46

0.45 - V t [V ] 0.44 Trap

0.43 EF 0.42

0.41

0.4 1 8 15 22 29 36 43 50 57 64 71 78 85 92 99 106 113 120

Metal Poly gate gate Tantalum ONO High-k Alumina Si poly SiN Nitride SiO2 SiO2 Oxide Si subs Si subs Silicon

From continuous floating gate to charge trapping layer Based on well known SONOS concept, but o thicker tunnel oxide for retention

o high-k (Al 2O3) upper dielectric for capacitive coupling o metal (Tantalum) gate to prevent erase saturation o easy scalability, no capacitive coupling o requires introduction of new materials

• Bit-Cost Scalable (BiCS) flash memory – Increased memory density – Better control of channel charge/current

programmed Vth , subthreshold current – Integration complexity – Early development stage

Y. Fukuzumi et al., Toshiba Corp., IEEE IEDM, 2007 Y. Komori et al., Toshiba Corp., IEEE IEDM, 2008

More than 35 NVM alternatives have been so far proposed… Polymer FeRAM

FERAM PCM Word line Word line PMC RRAM Polymer Layer Bit line Bit line Bit line Polymer Layer Word line

CNT MOx-RRAM MRAM Polymer RRAM Molecular

• Storing mechanism – Permanent polarization of a ferroelectric material

• Writing mechanism – Electric field produced in the ferroelectric layer by the voltage applied to the capacitor plates

• Sensing mechanism – Displacement current associated to the polarization switch

• Cell structure – DRAM-like: 1 transistor, 1 capacitor (1T/1C)

The basic memory element is a ferroelectric capacitor (FeCAP) Destructive read

Qns

Qnss -+ Vpulse

Pr Read out signal: Q s-Qns = 2P r +-

Planar FeCAP area scaling

Minimum capacitance for sensing: 30 fF Operating voltage: 1 V

Minimum charge for sensing: 30 fC Equivalent electron number: 200 ֹ000 2D FeCAP Technology node: 90 nm FeCAP area: 100 x 100 nm 2 µµµ 2 Pr: 20 C/cm

Available electron number: 25 ֹ000

Hydrogen BE material seal Ir/SrRuO 3

BE contact to W-plug FeCAP etching (oxygen barrier and (accurate tapering control) air-gap formation)

• Main advantages • Main issues

– Fast (<100ns) read and write – Limited read endurance, operations with no intrinsic destructive read-out (apart limitation (<100ps) FeFET) – High write endurance (>10 12 ) – Difficult process integration – Low voltage and low power – Large cell size vs. Flash and operation DRAM (>15F 2) – Scaling limits and 3D capacitor required to go beyond the 90nm technological node

Tunable magnetization of the free layer: – Parallel to the pinned layer low BL to WL resistance – Antiparallel to the pinned layer low BL to WL resistance

CoFe or NiFe/CoFe

Al 2O3 or MgO CoFe or NiFe/CoFe NiMn or IrMn or CrPtMn

Cross-point architecture

N. Sakimura et al. , ISSCC 2003

MOSFET-selected architecture

W. J. Gallagher, Taiwan NVM Workshop, 2005

• Thermal stability – Smaller cell volume lower thermal stability – Lower thermal stability high-coercivity materials/ non-isotropic cell shape – high-coercivity materials/ non-isotropic cell shape higher programming current • Power consumption – Large magnetic fields for switching large power consumption (~4mA in standard MRAM, ~7mA for Toggle MRAM) – Tradeoff with stability increasing power consumption with scaling

1st generation not expected to be viable beyond the 90 nm technology node

• Programming current flows through (not close to) the MTJ stack spin torque mechanism • Advantages – Lower programming current – Better scaling perspectives (retention/programming tradeoff ) • Issues – Self-read disturbance – Writing time depends on the device area – Integration

Proposed for 65nm node and beyond

K. Miura et al. , VLSI Symp. on Tech. 2007

• Main advantages • Main issues

– Fast write (<100 ns) – Difficult process integration – High write endurance – Large cell size vs. Flash and – Low voltage write DRAM – Large write current (> 10 mA/B) – Small read signal – Scaling limits

SET Temperature (low resistive)

Time RESET (high resistive)

RESET Temperature (high resistive)

Tx Time SET (low resistive)

Pore and lance µµµtrench Planar structure structure structure

H. Horii et al. , F. Pellizzer et al. , M. Lankhorst et al., VLSI Symp. on Tech. 2003 VLSI Symp. on Tech. 2004 Nature Material, April 2005

Efforts to reduce the programming current still preserving a good controllability

8Mb Technology Demonstrator 128Mb Product 1Gb Product Advanced Development

Technology Node (nm) 180 90 45 32 2X

th Rc,Rc

th Rh,Rh

∆∆∆ . th TM = P M R

. ηηη 2 PM = V H I + RI

Phase change mechanism appears scalable to at least ~5nm

Min. stable cluster size for Ge 2Sb 2Te 5 vs. Temp.

D. Wright et al. , EPOCS 2004 C. Lam, SRC NVM Forum 2004

– Fast write (~100ns) – Process integration for GST – Good read signal window – Heater-GST interface (factor ten in resistance) optimization – Medium/low voltage write – Long endurance – Writing current reduction – Cell size comparable to Flash – Retention at very high and DRAM temperature (150 °C) – Good scalability – MLC capabilities

Numonyx: 128Mbit Omneo™ PCM Products qualified, 1Gbit product presented at ISSCC 2010

• Storing mechanism

– Resistive switching of a storage layer Set state I • Writing mechanism – Current or voltage-induced Reset state conductance switching • Sensing mechanism V

– Resistance change • Cell structure

– 1 transistor, 1 resistor (1T/1R) or cross-point (1R) A. Sawa, Materials Yun et al., Phys. Today 2008 Stat. Sol. 2007

• Chalcogenide – GST and other phase-change alloys

– AgGeSe, AgGeS, WO 3 and SiO 2 solid electrolyte • Binary oxide – Nb O , Al O , Ta O , TiO , ZrO , Cu O and NiO 2 5 2 3 2 5 2 x x M. Kozicki, EPCOS 2006 • Oxides with perovskite structure

– SrZrO 3, doped- SrTiO 3, Pb(Zr xTi 1-x)O 3 and Pr 0.7 Ca 0.3. MnO 3 • Conductive polymers

– Bengala Rose, AlQ 3Ag, Cu-TCNQ

A. Chen et al. , IEDM Tech. Dig. 2005

• Unipolar resistive switching in a binary oxide layer • Feasible small cell size (4-8 F2), very low-cost solution 2Mbit 1T-1R 90nm test chip (Y.H. Tseng, et al. , IEDM Tech. Dig. 2005) 3.0 V , I reset reset Reset operation 2.5 Set operation

2.0 Pt/NiO/Pt Joule heating + Ni thermal oxidation 1.5 reset (U. Russo et al., IEEE T-ED, 2009) 1.0 Current [mA] Threshold switching + 0.5 set NiO reduction Vset, Iset 0.0 (D. Ielmini et al., APL 2009) 0.0 0.5 1.0 1.5 2.0 Voltage [V] Copyright © 2008 Numonyx B.V. Programmable Metallization Cells – bipolar mode

Programmable metallization cell (PMC): a conductive filament of silver is created by diffusion into a chalcogenide (solid electrolyte) by applying an electric field

Oxidizable electrode Metallic electrodeposit

low resistance Ioncurrent M →→→ M+ + e -

Glassy electrolyte high resistance M+ + e - →→→ M Inert electrode

M. Kozicki, EPCOS 2006 M. Kund et al ., IEDM Tech. Dig., 2005

• Main advantages • Main issues

– Good read signal window (factor – Statistical variations of ten in resistance) programming voltage/current and programmed resistance – Medium/low voltage write – Difficult process integration (low – Low programming current and thermal budget required) energy (bipolar RRAM) – Retention capabilities for 10years – Cross-point solutions available at 85 °C must be demonstrated – Good scalability

Huge variety of proposed materials and solutions, but still at research level

• “simple” structure low cost 2 • reduced cell size: 4F top electrodes • suitable for 3D stacking cell top electrode size (4/n)F 2 memory material bottom electrodes

Vprog /2Vprog Vprog /2 • Parasitic paths exist through neighbouring cells V /2 prog • Programming (and also reading) can 0 V perturb the array • Some selector is needed to stop Vprog /2 parasitic paths low-temperature diode selectors needed for process compatibility

Selector device Storing device

• Homojunctions polySi p/n junctions • RRAM NiO, Nb 2O5, Al 2O3, • Heterojunctions p-CuO/n- Ta 2O5, TiO 2, ZrO x, Cu xO InZnO • PCM chalcogenide material • Schottky diode Ag/n-ZnO • Chalcogenide Ovonic Threshold Switching (OTS) materials

• An impressive growth of the portable systems market has been enabled by the NVM Flash technology and it is expected that Flash will dominate the NVM production well beyond the 30nm technology node • Semiconductor industries plan to exploit new physical mechanisms and new materials in nano-scale NVM – provide valuable solutions to cover specific application requirements – interesting challenges to be solved (integration into CMOS process, reliability assessment, scaling feasibility) • Among these alternative NVM, Phase Change Memory is a most promising candidate to take over mainstream Flash technology – better performances – longer-term scalability