CH05 Internal Memory • System Overview • Semiconductor Main Memory • Memory • Pentium II and PowerPC Cache Organizations • Advanced DRAM Organization

TECH Computer Science

CH04

Characteristics Location • Location • CPU • Capacity • Internal • Unit of transfer • External • Access method • Performance • Physical type • Physical characteristics • Organisation

Capacity Unit of Transfer • Word size 4The natural unit of organisation • Internal • Number of words 4Usually governed by bus width 4or • External 4Usually a which is much larger than a word • Addressable unit 4Smallest location which can be uniquely addressed 4Word internally 4Cluster on disks

1 Access Methods (1) Access Methods (2)

• Sequential • Random 4Start at the beginning and read through in order 4 Individual addresses identify locations exactly 4Access time depends on location of data and previous 4 Access time is independent of location or previous access location 4 e.g. RAM 4e.g. tape • Associative • Direct 4 Data is located by a comparison with contents of a portion of the store 4Individual blocks have unique address 4 Access time is independent of location or previous access 4Access is by jumping to vicinity plus sequential search 4 e.g. cache 4Access time depends on location and previous location 4e.g. disk

Memory Hierarchy Performance • Registers 4In CPU • Access time • Internal or Main memory 4Time between presenting the address and getting the 4May include one or more levels of cache valid data 4“RAM” • Memory Cycle time • External memory 4Time may be required for the memory to “recover” 4Backing store before next access 4Cycle time is access + recovery • Transfer Rate 4Rate at which data can be moved

Physical Types Physical Characteristics • Semiconductor • Decay 4RAM • Volatility • Magnetic • Erasable 4Disk & Tape • Power consumption • Optical 4CD & DVD • Others 4Bubble 4Hologram

2 Organisation The Bottom Line • Physical arrangement of bits into words • How much? • Not always obvious 4Capacity • e.g. interleaved • How fast? 4Time is money • How expensive?

Hierarchy List So you want fast? • Registers • It is possible to build a computer which uses only • L1 Cache static RAM (see later) • L2 Cache • This would be very fast • Main memory • This would need no cache • Disk cache 4How can you cache cache? • Disk • This would cost a very large amount • Optical • Tape

Semiconductor Memory Dynamic RAM • RAM • Bits stored as charge in capacitors 4Misnamed as all is random • Charges leak access • Need refreshing even when powered 4Read/Write 4Volatile • Simpler construction 4Temporary storage • Smaller per bit 4Static or dynamic • Less expensive • Need refresh circuits • Slower • Main memory

3 Static RAM Read Only Memory (ROM) • Bits stored as on/off switches • Permanent storage • No charges to leak • Microprogramming (see later) • No refreshing needed when powered • Library subroutines • More complex construction • Systems programs (BIOS) • Larger per bit • Function tables • More expensive • Does not need refresh circuits • Faster • Cache

Types of ROM Organisation in detail • A 16Mbit chip can be organised as 1M of 16 bit • Written during manufacture words 4 Very expensive for small runs • A bit per chip system has 16 lots of 1Mbit chip with • Programmable (once) bit 1 of each word in chip 1 and so on 4 PROM 4 Needs special equipment to program • A 16Mbit chip can be organised as a 2048 x 2048 x • Read “mostly” 4bit array 4 Erasable Programmable (EPROM) 4Reduces number of address pins f Erased by UV 4 Electrically Erasable (EEPROM) f Multiplex row address and column address 11 f Takes much longer to write than read f 11 pins to address (2 =2048) 4 f Adding one more pin doubles range of values so x4 capacity f Erase whole memory electrically

Typical 16 Mb DRAM (4M x 4) Refreshing • Refresh circuit included on chip • Disable chip • Count through rows • Read & Write back • Takes time • Slows down apparent performance

4 Packaging Module (256KB) Organisation

Module Organisation (1MB) • During the course of the execution of a program, memory references tend to cluster • e.g. loops

Average access time vs Hit ratio Cache // • Small amount of fast memory • Sits between normal main memory and CPU • May be located on CPU chip or module

5 Cache operation - overview Cache Design • CPU requests contents of memory location • Size • Check cache for this data • Mapping Function • If present, get from cache (fast) • Replacement Algorithm • If not present, read required block from main memory • Write Policy to cache • Block Size • Then deliver from cache to CPU • Number of Caches • Cache includes tags to identify which block of main memory is in each cache slot

Size does matter Typical Cache Organization // • Cost 4More cache is expensive • Speed 4More cache is faster (up to a point) 4Checking cache for data takes time

Direct Mapping Example Direct Mapping Cache Line Table • Cache line Main Memory blocks held • 0 0, m, 2m, 3m…2s-m • 1 1,m+1, 2m+1…2s-m+1

• m-1 m-1, 2m-1,3m-1…2s-1

6 Mapping Function Direct Mapping • Cache of 64kByte • Each block of main memory maps to only one cache • Cache block of 4 bytes line 4i.e. cache is 16k (214) lines of 4 bytes 4i.e. if a block is in cache, it must be in one specific place • 16MBytes main memory • Address is in two parts • 24 bit address • Least Significant w bits identify unique word 4(224=16M) • Most Significant s bits specify one memory block • The MSBs are split into a cache line field r and a tag of s-r (most significant)

Direct Mapping Address Structure Direct Mapping Cache Organization

Tag s-r Line or Slot r Word w 8 14 2

• 24 bit address • 2 bit word identifier (4 block) • 22 bit block identifier 4 8 bit tag (=22-14) 4 14 bit slot or line • No two blocks in the same line have the same Tag field • Check contents of cache by finding line and checking Tag

Direct Mapping pros & cons Associative Mapping • Simple • A main memory block can load into any line of cache • Inexpensive • Memory address is interpreted as tag and word • Fixed location for given block • Tag uniquely identifies block of memory 4If a program accesses 2 blocks that map to the same line • Every line’s tag is examined for a match repeatedly, cache misses are very high • Cache searching gets expensive

7 Associative Mapping Example Fully Associative Cache Organization

Associative Mapping Address Structure Set Associative Mapping • Cache is divided into a number of sets • Each set contains a number of lines Word Tag 22 bit 2 bit • A given block maps to any line in a given set • 22 bit tag stored with each 32 bit block of data 4e.g. Block B can be in any line of set i • Compare tag field with tag entry in cache to check • e.g. 2 lines per set for hit 42 way associative mapping • Least significant 2 bits of address identify which byte 4A given block can be in one of 2 lines in only one set (8bit) is required from 32 bit data block • e.g. (based 16 number (4bit)) 4Address Tag Data Cache line 4FFFC FFFC 24682468 3FFF

Two Way Set Associative Mapping Example Set Associative Cache Organization

8 Set Associative Mapping Replacement Algorithms (1) Address Structure Direct mapping • No choice • Each block only maps to one line Word Tag 9 bit • Replace that line Set 13 bit 2 bit • Use set field to determine cache set to look in • Compare tag field to see if we have a hit • e.g 4Address Tag Data Set number 41FF 7FFC 1FF 12345678 1FFF 4001 7FFC 001 11223344 1FFF

Replacement Algorithms (2) Associative & Set Associative Write Policy • Must not overwrite a cache block unless main memory is up to date • Hardware implemented algorithm (speed) • Multiple CPUs may have individual caches • Least Recently used (LRU) • I/O may address main memory directly • e.g. in 2 way set associative 4Which of the 2 block is lru? • First in first out (FIFO) 4replace block that has been in cache longest • Least frequently used 4replace block which has had fewest hits • Random

Write through Write back • All writes go to main memory as well as cache • Updates initially made in cache only • Multiple CPUs can monitor main memory traffic to • Update bit for cache slot is set when update occurs keep local (to CPU) cache up to date • If block is to be replaced, write to main memory only • Lots of traffic if update bit is set • Slows down writes • Other caches get out of sync • I/O must access main memory through cache • N.B. 15% of memory references are writes

9 Newer RAM Technology • Synchronous DRAM (SDRAM) 4 currently on DIMMs 4Access is synchronized with an external clock 4Address is presented to RAM 4RAM finds data (CPU waits in conventional DRAM) 4Since SDRAM moves data in time with system clock, CPU knows when data will be ready 4CPU does not have to wait, it can do something else 4Burst mode allows SDRAM to set up stream of data and fire it out in block

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