A Low Voltage, Low Power 4 Order Continuous-Time Butterworth Filter

A Low Voltage, Low Power 4 th Order Continuous-time Butterworth Filter for Electroencephalography Signal Recognition.

THESIS

Presented in Partial Fulfillment of the Requirements for the Degree Master of Science in the Graduate School of The Ohio State University

Ridwan Saleh Mulyana. B.S.E.C.E.

Graduate Program in Electrical and Computer Engineering

The Ohio State University

2010

Master’s Examination Committee:

Professor Mohammed Ismail El-Naggar, Advisor

Professor Waleed Khalil

Ridwan Saleh Mulyana

2010

Abstract

Operational Transconductance Amplifier filter (OTA-C) in biomedical devices have been explored significantly because of its advantages in low power and low voltage design which is very important for battery powered biomedical devices. Main idea of this design is to implement Gm-C filter in low voltage, power, and frequency with increased linearity and dynamic range. Moreover, portable patient monitoring system devices becomes more significant because it does not limit one’s mobility in daily activities. In order to operate in sub-hertz frequency, a very low transconductance or a very high capacitance value is required. Increasing capacitor size is not an option as it will consume more silicon area.

In this thesis, a filter for Electroencephalography (EEG) data acquisition system is designed. It is based on continuous-time analog filter topology to provide a good accuracy and high performance. The designed circuit combines active linearization technique with series-parallel current array to achieve good linearity and low power consumption. A tunable fourth-order maximally flat continuous-time filter is designed by using the OTAs. By utilizing biquad filter structure which is implemented with several different OTA configurations, a higher order filter can be achieved simply by cascading its structure. ii

The overall system is designed in 180nm CMOS technology from TSMC library. In deep analysis of circuit and design procedures are discussed in the following chapters.

Simulation results are also included to verify the robustness of the design. Finally, with a supply voltage of 1.5V, the filter is capable of handling input signals up to 400mV with a low distortion (THD = 52.3dB). As the total active area only 750µm x 550µm and total power consumption of 4.7µW, the filter is suitable for portable EEG data acquisition system.

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Dedication

This document is dedicated to my family.

Acknowledgments

First, I would like to thank my family for supporting me to study in electrical engineering field. Without them, I would never reach up to this point.

I also would like to thank my advisor, Professor Mohammed Ismail, for guiding me with knowledge and advice to go through this master program at the Ohio State University. His expertise and encouragement are very valuable to understand the big picture of why one supposes to do research. Additionally, I also thank to Professor Chung-Chih Hung and AIC group in National Chiao Tung University. Their outstanding supports in my electronics knowledge during the internship in Taiwan are extraordinary.

I would like to thank Professor Waleed Khalil for serving as master’s examination committee and providing valuable advice for my research. And thank to all friends in VLSI lab for supporting me during the school years. Finally, I would like to thank all my colleagues in

Industrial Engineering Department for supporting me to go through my study at the Ohio State

University.

Vita

June, 2007………………………………………………….. B.S. Electrical and Computer Engineering, The Ohio State University.

July, 2007 – Present …………………………………… Graduate Associate Assistant,

The Ohio State University.

Fields of Study:

Major Field: Electrical and Computer Engineering

Table of Contents

Abstract ...... ii

Dedication ...... iv

Acknowledgments...... v

Vita ...... vi

Fields of Study: ...... vi

Table of Contents ...... vii

List of Figures ...... x

List Of Tables ...... xiii

Chapter 1 : Introduction...... 1

1.1 Background ...... 1

1.2 Basic Structure of Biomedical Data Acquisition ...... 1

1.2.1 Electroencephalography Data Acquisition system...... 2

1.3 Analog Active Filter ...... 4

1.4 Thesis Organization ...... 5

Chapter 2 : Differential Amplifiers ...... 7 vii

2.1 Introduction ...... 7

2.2 General Methods of Improving Linearity ...... 8

2.2.1 Differential structure ...... 8

2.2.2 Constant Drain-Source Structure ...... 10

2.2.3 Source Degeneration Structure ...... 11

2.2.4 Pseudo-Differential Structure ...... 13

2.3 Advanced Models of Improving Linearity ...... 15

2.3.1 Multiple Differential Pair Structures ...... 16

2.3.2 Constant Drain Source Voltage with Opamps ...... 16

Chapter 3 : Low Voltage Low Power OTAs Architecture...... 18

3.1 Weak Inversion Transconductor ...... 18

3.2 A Weak Inversion OTA with active source degeneration transistors and Current

Division Array...... 20

3.3 Common Mode Sensing Circuit ...... 23

Chapter 4 : OTA-C Filters ...... 26

4.1 Introduction ...... 26

4.2 Transconductor Elements ...... 27

4.2.1 Resistors ...... 27

viii

4.2.2 Amplifiers ...... 28

4.2.3 Gyrators ...... 29

4.2.4 Integrators ...... 31

4.3 Fourth Order Maximally Flat Low-Pass Filter ...... 34

4.3.1 2 nd Order Biquad Block Structure ...... 34

4.3.2 Low-Pass Filter Implementation ...... 37

4.3.3 Extra Circuitry ...... 40

Chapter 5 : Simulation Results and Discussion of OTA-C Filter ...... 42

5.1 Parameters ...... 42

5.2 Performance of Designed OTAs and Maximally Flat Filter ...... 45

5.2.1 Pre-Simulation results of Transconductor and Filter ...... 45

5.2.2 Post-Simulation results of Transconductor and Filter ...... 52

Chapter 6 : Conclusion and Future Work ...... 61

6.1 Conclusion ...... 61

6.2 Future Work ...... 61

References: ...... 63

List of Figures

Figure 1.1. General diagram of data acquisition...... 1

Figure 1.2. EEG circuitry block diagram...... 3

Figure 1.3. Filter type based on the operating frequency range [18]...... 5

Figure 2.1. Differential input pair...... 8

Figure 2.2. Constant drain-source voltage structure...... 10

Figure 2.3. Source degeneration technique...... 12

Figure 2.4. NMOS and PMOS Pseudo Differential Input Pairs...... 14

Figure 2.5. Pseudo differential with common mode feedforward...... 15

Figure 2.6. Multiple Input Differential Input Pair...... 16

Figure 2.7. Linearity improved by the use of op-amp...... 17

Figure 3.1. Open loop gain vs. bias current [5]...... 20

Figure 3.2. Series-parallel current array...... 21

Figure 3.3. OTA with integrated CMFB...... 21

Figure 3.4. Common Mode Circuit...... 24

Figure 3.5. Resistor-based CMFB...... 24

Figure 3.6. Transistos-based CMFB...... 25

Figure 4.1. Resistor-like configurations of transconductors: (a) grounded single ended output. (b) differential. (c) floating resistor...... 28

Figure 4.2. Single-ended OTAs amplifier...... 29

Figure 4.3. Single-ended output Gyrator...... 30

Figure 4.4. Floating inductor...... 31

Figure 4.5. Integrators. (a) single-ended. (b) fully differential with floating capacitor. (c)

fully differential with grounded capacitors. (d) non-ideal integrator...... 32

Figure 4.6. (a) RLC equivalent circuit. (b) Norton’s equivalent circuit...... 35

Figure 4.7. 2nd Order single ended and fully differential biquad structure...... 36

Figure 4.8. A 4th Order Maximally Flat Low-Pass Biquad Filter...... 38

Figure 4.9. (a) Extra circuit blocks. (b) Biasing circuit. (c) Output buffer...... 41

Figure 5.1. OTA frequency response at typical typical (TT)...... 46

Figure 5.2.OTA Frequency response at fast fast (FF) corner...... 46

Figure 5.3.OTA frequency response at slow slow (SS) corner...... 47

Figure 5.4. Gm variation in some input range...... 47

Figure 5.5. Tranconductance values at different tuning voltage of source degenerated

resistance...... 48

Figure 5.6. Common mode rejection ratio at different corner...... 49

Figure 5.7. Power supply rejection ratio at different corner...... 49

Figure 5.8. Common Mode Transient Response...... 50

Figure 5.9. Filter frequency response at TT, FF, and SS corner...... 50

Figure 5.10. Filter HD3 analysis at 40Hz 0.4Vpp input signal...... 51

Figure 5.11. Filter tuning range...... 52

Figure 5.12. OTA frequency response at TT corner...... 53

Figure 5.13. OTA frequency response at SS corner...... 53

Figure 5.14. OTA frequency response at FF corner...... 54

Figure 5.15. Post-sim CMRR at different corner...... 54

Figure 5.16. Post-sim PSRR at different corner...... 55

5.17. Gm in montecarlo analysis...... 56

5.18. Gain and phase in Montecarlo analysis...... 56

5.19. CMRR in Montecarlo analysis...... 57

5.20. PSRR in Montecarlo analysis...... 57

Figure 5.21.Post-sim filter response at different corner...... 58

Figure 5.22. Post-sim filter HD3 at 40Hz 0.4Vpp input signal...... 58

Figure 5.23. Chip photo...... 59

xii

List of Tables

Table 1. Brain waves classification [1]...... 3

Table 2. OTA and filter specification...... 60

Table 3. Literature Comparison...... 60

xiii

Chapter 1 : Introduction

1.1 Background

Biomedical electronics and devices have been growing promptly in the modern time. The requirements of low power and low voltage circuit design have become major research topics because of limited amount of silicon area and energy sources. In some biomedical devices, for example: pacemaker and hearing aid, portability and compact design are the major points of the design goals. Human biological signals operate in sub-hertz to several kilo hertz with amplitude in the range of micro volts [1]. To record these type of signals need complex and high performance filters to achieve accurate data in such noisy situation.

1.2 Basic Structure of Biomedical Data Acquisition

Figure 1.1. General diagram of data acquisition.

In figure 1.1, it describes a general circuit diagram of biomedical data

acquisition device. It starts by connecting human body signals by using highly

conductive silver electrodes coated with silver-chloride and gold cup electrodes to

the front end transducer. Next, the analog block amplifies these signals up to the

desired operating point and an analog filter cleans out the unnecessary noise that

carries along with these signals. An Analog-Digital Converter (ADC) picks up the

analog signals and translates them into string of 1 and 0. A Digital Signal Processing

(DSP) processes the bits in digital domain and the results can be stored in various

digital media storages, e.g., hard disk, flash memory, writable disc, and etc.

1.2.1 Electroencephalography Data Acquisition system.

Electroencephalography, commonly known as EEG, is a method to measure brain waves by recording the electrical movements along the head scalp by the firing of neurons within the brain [2]. The electrical activity is recorded through highly conductive electrodes attached to the head’s surface and sends the signals into EEG machine. The recording can be done in several different conditions depending on the objective. Most of the time, EEG is used in medical practice to diagnose epilepsy, brain death, coma, and some other abnormal activities in brain. In the early stage,

EEG was used to detect brain tumors and focal brain disorders [3].

Several different rhythmic oscillations can be classified to define brain activities. Five major brain waves (Alpha, Beta, Delta, Gamma, and Theta waves)

define most the brain activities with three additional minor bands (Kappa, Lambda, and Mu waves) as the complements [1]. The classification is based on the operating frequency range of each wave and the state of the sample, in this case, human biological sample. The following table shows the characteristic of major and minor bands:

Band Frequency (Hz) Amplitude ( Individuals State Alpha 8 – 13 20 - 60 ) Relaxed, closed eyes Beta 13 – 40 2 – 20 Excited mental/ physical Delta 0.5 – 3.5 20 – 200 Deep sleep normal person Theta 4 – 7 20 - 100 Drowsiness in young adults Gamma 36 – 44 3 - 5 Sensory stimuli Kappa 10 N/A Thinking Lambda N/A 20-50 Visual image Mu 8-13 N/A Sensori motor cortex Table 1. Brain waves classification [1].

Figure 1.2. EEG circuitry block diagram.

EEG data acquisition system, as shown in figure above, detects the electrical signals by using several conductive electrodes attached to head scalp. The EEG machine receives signals from electrodes and gets amplify by an instrumental

amplifier. The amplification has to be done because signals from electrodes are too weak to be processed. Once the signals are properly amplified, a low pass filter determines the cutoff frequency of each brain wave. In this case, a tunable low pass filter is favorable. It plays an important role in the system because noise, which has been amplify by the instrument amplifier, needs to be canceled out in order to achieve high accuracy of the brain signals. Finally, the filtered signal goes the digital block which processes the signal in digital domain. It is necessary to have an extra analog circuitry, a Driven Right Leg (DRL) circuit, which feeds back into the biological sample to cancel out common mode interference.

1.3 Active Filter

In general, active filter design divides into two, digital and analog filters.

Analog filter processes the signal continuously, while the digital filter converts the signal into digital domain and processes in that mode. Based on the operating region, filters are classified into LC filter, Integrated Gm-C filter, Switched-Capacitor,

Active R-C, and waveguide filter (shown in figure 1.3). In Biomedical electronics, high performance low frequency filter is needed and switched capacitor filter is commonly implemented. However, it consumes quiet amount of power and is vulnerable to clock jitter, which generates noise that would affect the main signal [4].

On the other hand, Integrated Gm-C filter has a wide operating range, which can be suited from low to high frequency applications. It operates in open loop

architecture meaning that the performance of the system depends on the performan ce of the transconductor. Since Gm-C filter processes the analog signal continuously; with a proper design and tuning values, the total noise and the power consumption will be lower than switched capacitor topology. The remaining challenge is to increase Gm -C cell performance to adjust with the present requirements. Th erefore, implementing Gm -C filter in low power, low voltage, and low frequency applications have been researched in details.

Figure 1.3. Filter type based on the operating frequency range [18].

1.4 Thesis O rganization

In the next few sections, some important design techniques for filters are covered. Chapter 2 describes high linearity structures of Operational

Transconductance Amplifiers (OTA). It explains the characteristics, superiorities as well as the disadvantages of each different model. Chapter 3 covers the proposed

design of OTA, which shows a high performance, low operating frequency range, and very low power consumption structure. Circuit analyses, including: design concept and mathematical formulations will be discussed to verify the structure. Chapter 4 explains a principle of designing OTA-C or known as Gm-C filters, which includes other supporting basic blocks that supports the filter operation. Chapter 5 discusses the simulations procedures and results of the Gm-C filter and corresponding test bench. Chapter 6 wraps up the thesis with summary and conclusion.

Chapter 2 : Differential Amplifiers

2.1 Introduction

Transconductance is one of the most essential parameter in designing an analog circuit. It is usually represented as g m in AC small signal analysis. An

Operational Tranconductance Amplifier (OTA) is a voltage controlled current source type of amplifier because of its proportionality between the input voltage and the output current. A difference of an OTA from Op-Amp is that the all of the nodes, except input and output nodes, have low impedances [5]. A relation between transconductance (gm), AC gate voltage, and drain current can be described as:

(2.1) = OTAs operate as active devices in wide range of frequencies covering from ultra low frequency applications and up to high speed analog designs and they are basic building blocks of Gm-C filter. One important aspect of using OTAs is a limited linearity performance since the transconductors operate in an open loop manner. In addition, as process of CMOS technology goes more advances and smaller in term of transistor’s size, achieving a high linearity OTA appears to be a challenging task.

Therefore, the next sections explain several basic structures of high linearity OTAs in

details. Moreover, a concept of designing subthreshold transconductor and combination of high linearity with Op-Amps will also be included.

2.2 General Methods of Improving Linearity

Designing OTAs with simplest structures with high performance results are the goal of analog designers. However, a good result sometimes requires more complex structures. In the following subsections, several differential amplifiers are discusses based in [5] [9] [21].

2.2.1 Differential structure

Differential structure is a common model that analog designers use to cancel out even-order harmonics, common mode and power supply noises. Moreover, since the phase of input signals are 180° different, dynamic range is theoretically doubled compared to single-ended input. Figure 2.1 shows a basic differential input stage of a transconductor.

Figure 2.1. Differential input pair.

When M1 and M2 reach saturation condition, the output current I1 and I2 can be expressed as

(2.2) = . ,. − − ,

(2.3) = . ,. − − ,

Subtracting these two equations (2.2 and 2.3) shows the differential output current, which is:

(2.4) = − = , − − ). − − ,) Since the input common mode voltage (Vcm) is a fixed constant DC source voltage,

the node S can be expresses as:

(2.5) . =

The transconductance can be described as:

(2.6) = 2. β,. , Since the transconductance is proportional to the tail current Ib, tuning value

of gm can be done by varying this tail current, assuming that the node voltage Vs is a

fixed constant value. However, since Vs differs according to the input signal and

process variation, the transconductance gm cannot be tuned properly. This condition

affects the linearity performance of the transconductance cell.

2.2.2 Constant Drain-Source Structure

In figure 2.2, a constant drain-source voltage MOSFETS can be observed on point X and Y. Transistors M3 and M4 are biased into saturation region and they drive the input pair transistors M1 and M2 into linear operating region. By realizing this condition, input currents are described as follow:

(2.7) = , , − , − ,

(2.8) = , , − , − ,

Since this structure occupies differential structure, a straight forward subtraction of

I1 and I2 will result the ouput differential current Iout as follow:

(2.9) = − = . , − )

Figure 2.2. Constant drain-source voltage structure.

By observing the equations above, one can see that the linearity performance will be affected by the fluctuation of the drain source voltage of transistor M1 and

M2. Moreover, some second order effects that come from the relation of β.V ds will contribute to the reduction of linearity. Therefore an extra circuitry is required to maintain the stability of point X and Y. Combination of Op-amps with constant drain- source structure will be discussed in the following section.

2.2.3 Source Degeneration Structure

Another technique to increase linearity performance is to utilize source degenerated differential input structure. The relation between output current and the input voltage of both circuits can be described as follow [6]:

(2.10) = .

(2.11) ,. = . . 1 − ). ,)

(2.12) = . where: (2.13) = ∗

(2.14) = . ) ,)

In source degeneration structure, a resistor (R) is connected to the source of

input transistor. From equation (2.10), the gate source voltage relatives to the

resistor R, which is useful to reduce the effect of nonlinear distortion of the circuit.

However, this benefit does not come free because the resistor also reduces the tranconductance and affects the overall small signal gain.

As shown in equation (2.12), the transconductance can be controlled by changing the variable N, where (2.13) is the source degeneration factor. Moreover, the third order harmonic distortion (HD3) is decreased by (1+N) 2, which means that the larger the N factor, the better the HD3. When R is set to zero, one may notice that the formulas look the same with the ones in differential pair input structure.

Figure 2.3. Source degeneration technique.

In figure 2.3, it shows two source degeneration structures with different resistor setup [6]. Both setups look almost the same except for the resistances. 12

Figure 2.3a shows that the tails of two resistors are connected to one tail current, while in 2.3b, only one resistor with doubled the values connects to two tail currents.

The later model is more often to use in low voltage application because of less voltage drop. Furthermore, noise from the tail current on figure 2.3a is propagating into the outputs (Vop and Von) as common mode noise, while in 2.3b, the noise appears as differential noise current. However, in ideal condition, the differential input signals should flow from gate of transistors to the end of the resistor, then the voltage across the resistor produces the output current Iout, which shown in (2.11).

This condition works with assumption that the intrinsic resistance of transistors M1 and M2 are stable. In reality, they change based on the transconductance of each transistor. Therefore, source degeneration circuit needs a tunable resistance to add its robustness.

2.2.4 Pseudo-Differential Structure

Unlike the differential input pair, the pseudo differential structure has no bias current that connects the source node of transistor and the Ground for NMOS or the

Vdd for PMOS. This idea is useful for low voltage design because of fewer transistors used in series [7] .

Figure 2.4. NMOS and PMOS Pseudo Differential Input Pairs.

In figure 2.4, pseudo differential input pairs are shown in two setup, NMOS and PMOS pairs. Both show that the Vs nodes are not connected to bias current.

Therefore, the linearity of the circuit since there is no variation at the source node of input pair transistors. The differential output current can be described as:

(2.15) = − = , − − ). − ,) However, this structure does have some important issues. Since the current source or tail current has been removed, the gm tuning capability has become restricted. Common mode voltage gain increases to a level where Common Mode

Rejection Ratio (CMRR) becomes 1, which means it has the same gain factor with the differential voltage gain. Therefore, this circuit requires an extra configuration to reduce the common mode voltage gain, shown in figure 2.5 [7].

Figure 2.5. Pseudo differential with common mode feedforward.

This configuration applies a Common Mode Feedforward (CMFF) technique to cancel out the common mode signal that carries from the input pairs by feeding the signals back to the input stage. Hence, the output differential pair only contains a product of differential input voltage with transconductance gm.

2.3 Advanced Models of Improving Linearity

Basic concepts of increasing linearity are discusses above. However, these structures are not perfect. Some of them do need extra circuitry to make it work.

Some journals and papers have been discussing about improved linearity techniques.

Therefore, this section will discussed some improved structures to enhance linearity that already been proposed.

2.3.1 Multiple Differential Pair Structures

An interesting approach to increase linearity performance is by using partially linearized bipolar transconductors multiple input pairs. As shown in figure 2.6, the structure shows that two differential pairs are combined together with additional dc sources through positive and negative inputs. The idea of having dc source is to control the dc offset voltage, so that the current of the two differential pairs can linearized each other, which according to [8], the dc source should be chosen to be

1.317xVth to optimize its linearization factor.

I1 I1

M1 M3 M2 M4 Vin Vin V1 V1

I1 I1

Figure 2.6. Multiple Input Differential Input Pair.

2.3.2 Constant Drain Source Voltage with Opamps

One of the common ways to improve linearity is to have constant drain

source voltage of the differential input pair. A technique to add Op-Amps prior the

differential input pair has been proposed [9]. It eliminates the need of small input

signals and large biasing current. Combined with additional resistor, this structure performs quiet well. Due to the virtual ground of Op-Amps, The input voltage of transistor M1 and M2 equals to the source voltage of each transistor at point x and y.

The main point of this structure is to have the input voltage flows through the Op-

Amp up to the resistor, as shown in figure 2.7. Therefore, the source voltages on both sides do not depend on gate source voltage of each transistor and this will enhance the linearity performance.

Figure 2.7. Linearity improved by the use of op-amp.

There are many more different structures about how to improve linearity performance. Since the transistor size is getting smaller in advanced process, achieving high linearity has become more challenging issue. Therefore, in the next section, a different way to increase linearity targeted for biomedical application will be described in detail.

Chapter 3 : Low Voltage Low Power OTAs Architecture.

One of the common techniques used in biomedical filter design is to occupy a continuous time integrator [10]. In the past years, different architecture of generating very low transconductance OTAs have been reported in previous works by researchers. Common known techniques are the floating gate and bulk-drive input stages are discussed in [11]. A current cancellation technique also has been reported.

This method requires a very large transistors area in order to achieve very small transconductance [12]. As mentioned in previous chapter, linearity and dynamic range improvements are the main purpose of this project. Therefore, in this chapter, a combination of weak inversion fully differential structure with active linearization technique will be described. Moreover, the complete structure will occupy series- parallel current division method to improve overall gain and reduce transconductance further down to the preferred operating range.

3.1 Weak Inversion Transconductor

As the demand for low voltage and low power consumption, weak inversion region becomes more attractive to be used in recent design architecture and since biomedical signals are operating in sub-hertz region, substhreshold transistors are 18

good match in term of its characteristics. Weak inversion transistors should be tuned with Vds at least few times larger than UT [13]. The drain current can be described as:

(3.1) __ = . . exp

(3.2) = ≈ 26 300°

IDO is the reverse voltage saturation current, W/L is the ratio of width and length, n is

the slope factor, and V TH is the thermal voltage. The transconductance can be expressed as:

(3.3) =

One may notice that the current I D and transconductance are linearly related,

therefore maximum ratio of gm/ I D can be achieved. It also leads to maximum intrinsic gain voltage, minimum input offset voltage, maximum available bandwidth, and minimum input noise density [14].

(3.4) . = ..

(3.5) . = . . = ..

As shown in eqn (3.4), the cutoff frequency of weak inversion transistor is inversely related with length of transistor meaning that it does not fit for high speed operation, but works well in low frequency operation. The open loop gain of the

circuit is described in eqn (3.5 ). It shows that drain current does not affect the gain as long as the transistors stay in subthreshold region. Figure 3.1 represents relationship between gain and drain current. As the drain current goes up, the gain goes speed goes up, and vice versa.

Figure 3.1. Open loop gain vs. bias current [5].

3.2 A Weak Inversion OTA with active source degeneration

transistors and Current Division Array.

In this section, linearity improvement method of the weak inversion OTA combines with active source degeneration is discussed. The weak inversion OTA is based on series-parallel current array [ 15]. This structure serves two main purposes; first, it reduces the transconductance by dividing the input current source into several transistors, which usually known as current division method. the transistors are put in array, it has benefit of increasing its output resistance to the desired operating point. Due to its characteristic of a very high output resistance rds, the drain current vs. drain voltage curve of the tran sistors show a very flat curve over 20

the range of drain voltage, which means that the current mirrors are in very stable condition. The series-parallel current mirror array (figure 3.2) factors are adjustable depending how much division factor (N) that needed in a design. Equation (3.9) shows the ratio of the input current Iin over output current Iout. Another advantage of this method of reducing gm is that the area used can be reduced because interdigitized and common centroid layout rules can be applied [16].

Figure 3.2. Series-parallel current array.

Figure 3.3. OTA with integrated CMFB.

A combination of series-parallel current array and the active source degeneration transistors is shown in figure 3.3. A common mode feedback is also included as part of the OTA design. Most of the transistors are in sub threshold operation region. The input pair transconductance (M1 and M2) is defined in eqn

(3.3). According to [6], the linearized transconductance can be described as:

(3.6) _ = ..

With equivalent resistance of:

(3.7) = .. . )

This resistance is form of transistors (MR) working in linear region, which is controlled by Vtune to adjust the cutoff frequency of the system. The overall transconductance Gm can be defined as:

(3.8) _ =

(3.9) . = = .

The input referred noise and the third order harmonic distortion are described as follow:

(3.10) . . = . _ . 1 + _

(3.11) = . .

Transistor Mv, Mc1 through Mc4 and Mb1 through Mb4 are the transistors

that control and provide negative feedback voltage to the main circuit. It will be

discussed in detail in the following section.

3.3 Common Mode Sensing Circuit

In fully differential circuit, a reference voltage is needed to generate a virtual reference point for the positive and negative outputs. The reference voltage usually sets at ½ of Vdd-Vss due to maximum output voltage swing (doubled if compared to single ended output) and maximum output voltage gain. A common mode feedback circuit comes to play in this role by fixing the DC output voltage to the desired operating point, Vcm. Moreover, the CMFB not only stabilizes the output voltage, but also rejects common mode voltage that usually propagates to the next stage of the circuit. In figure 3.4, common mode sensing circuit can be observed. The common mode sensing circuit senses the differential outputs of OTA and takes the difference between that output voltage and the reference voltage, and then the resulting voltage is sent back to the OTA to either reduce or increase the voltage.

Figure 3.4. Common Mode Circuit.

One common technique to fix the common mode point is to occupy two same size resistors and tap them with reference voltage, as shown in figure 3.5. It offers a simple integration between the OTA and the CMFB. However, some drawbacks have to be considered in this design, for example: high DC offset and mismatch between the two resistors [17].

Figure 3.5. Resistor-based CMFB.

On the other hand, figure 3.6 shows different configuration of CMFB circuit by using only transistors to generate the Vcm. Transistors M1 and M2 are the input channels from the OTA. Later, the common voltage is compared with Vref through

M1b and M2b. The difference between M1 and M1b or M2 and M2b will be mirrored by transistor M3 back to the OTA as negative feedback. Transistors Mb1 through

Mb4 are the bias transistors which are connected to current bus stage to increase its robustness and eliminate the need of manual voltage sources. Therefore, when the transistor M1 or M2 sends a lower voltage than the reference voltage, the Vcm will send a higher voltage so that the actual voltage will be the same as reference voltage.

Figure 3.6. Transistos-based CMFB.

Chapter 4 : OTA-C Filters

4.1 Introduction

Many different techniques have been explored to create a low frequency biomedical filter. Most common techniques employ switched capacitor model.

However, in recent years, continuous time filter design, Gm-C, has been investigated more details because of its continuous time signal processing and no need of anti aliasing filter. Moreover, Gm-C filter design can integrate all of its building block into single integrated circuit.

As mentioned in the introductory chapter, Active R-C Opamp based filter can also be used for low frequency applications. In this case, it is only useful if the integrated capacitor is less than 30pF. A much larger capacitor value will generate a considerable noise and consume much more space than Gm-C filter [18].

Additionally, integrating a large resistor is not feasible because the resistor’s values vary based on the semiconductor process.

For comparison, in R-C Opamp filter, to generate frequency ωc=300rad/s with capacitor C=30pF, one needs resistor R = 1x10 13 Ω. While in Gm-C filter design, the required transconductance value is Gm= 9x10 -9 Siemens. Therefore, in terms of chip

integration and reliability, it is more practical to have a very small transconductor than a very large resistor.

In the next several sections, numerous different configurations of transconductance cells will be described along with extra circuitries of fourth order

Gm-C filter [18]. An overall structure of the electroencephalography biquad filter along with the output buffer will also be discussed.

4.2 Transconductor Elements

Understanding the basic element block of transconductors is crucial before one starts designing a filter. Gm-C filter contains several transconductor designs to replace the required active and passive elements. As explained above that it is nearly impossible to integrate such a large resistor, a transconductor block can solve this issue. An LC ladders setup can also be observed since the transconductor can also be set as inductor.

4.2.1 Resistors

First fundamental block of transconductor is a resistor-like element. This

model is useful to be implemented in low-sensitivity LC ladders filter source and load

resistors can to be integrated together. The figures below show several different

resistor-like elements based on transconductor. In figure 4.1(a), the negative output

of transconductor is shorted to the positive input and the negative input is grounded.

Since the Iin is equal to the Iout, resistance of transconductor can be described as:

(4.1) = = .

(4.2) = =

In figure 4.1 (b) and (c), two differential transconductors are shown. Even though both have differential inputs, (b) has positive feedback, which generates a negative resistor value. It can be described as:

(4.3) = − =

For (c), The relation between input and output current is:

(4.4) = = = . − =

iout iin + Vi gm - - (a)

Figure 4.1. Resistor-like configurations of transconductors: (a) grounded single ended output. (b) differential. (c) floating resistor.

4.2.2 Amplifiers

After designing a resistor-like transconductor blocks, a voltage amplifier can be made out of them. This can be done by cascading two or more different

transconductors together. A summer amplifier could also be made by put them in parallel and in series with resistor.

Figure 4.2. Single-ended OTAs amplifier.

In figure 4.2, two different OTAs are set in series. The relation between input and output voltages are as follow:

(4.5) = . =

(4.6) = .

From these equations, one can see that the amplification factor is generated by ratio of gm1 and gm2. Since it is a gm-based ratio, it is very common to tune this ratio either by biasing current or voltage.

4.2.3 Gyrators

Another interesting setup of transconductor block is the gyrators. A gyrator block is very useful element because it shows how transconductor and capacitor could generate an inductor-like behavior circuit. 29

Figure 4.3. Single-ended output Gyrator.

As shown in figure 4.3, to generate a single-ended output gyrator, only two OTAs and a capacitor are needed. It is a connection of inverting and noninverting transconductors with capacitor in between. The inductor can be described as follow:

(4.7) = . (4.8) = .

(4.9) = . ∗ = = .

In equation (4.9), the inductor L is described as the ratio of capacitor C and gm1 x

gm2. Two gyrators can be combined together forming a floating inductor, shown in

figure 4.4.

Figure 4.4. Floating inductor.

4.2.4 Integrators

The next building block is an integrator. It is the element block for continuous- time filters and it can be realized by connecting a transconductor block with a capacitor as an integrating element. A single-ended integrator and fully differential ones are shown in figure 4.5. In ideal condition, the relation of voltage Vout and transconductance gm is described as:

(4.10) = . = . = .

It is more useful to have fully differential structure in this case because, ideally, it

cancels out the even order harmonic distortions. Since the input and output of the

transconductor are infinite, the transfer function H(s) and unity gain frequency (ωt) can be expressed as:

(4.11) ) ) = ) = .

(4.12) ) = = ) ) = )

(4.13) =

From the equation (4.12), it shows that in ideal condition, an integrator has infinite

DC gain. Moreover, the phase margin PM is equal to invers tan(B (jω)/G (jω))-180°, which

means the PM always equal to -90° in all frequency range. And the quality factor is

equal to Q(jω)=X(jω)/R(jω).

2Cl + + Vout+ Vin gm iout - - Vout- 2Cl (c)

Figure 4.5. Integrators. (a) single-ended. (b) fully differential with floating capacitor.

Figure 4.5(b) and (c) show two different capacitor configurations for integrator. One may notice that (c) requires capacitance values to be four times larger than in (b). In process point of view, if one capacitor is used as in (b), there will be parasitic capacitance between the top and bottom plate, which usually has an asymmetric capacitance value. Moreover, it tends to effect linearity performance of the system [9]. Therefore, by separating them into two capacitors, one can maintain same capacitance value for both ends.

On the other hand, not all transconductors may operate in perfect condition.

Non-ideal transconductors have output conductance that is not zero, as shown in figure 4.5 (d). Additionally, parasitic poles and zeros generate signal latency in the integrator. These parasitic poles and zeroes can be simulated at high frequency, typically higher than its unity gain bandwidth. The transfer function of non-ideal integrators can be observed as:

(4.14) ) . . ) = ) = . = . . .

The zeroes of the system can be in complex left half-plane for leading and right half-plane for lagging phases. Typically, the absolute values and phase responses of the integrator are in the range of |1/τ1|<<ωt<<|1/τ2|. The non-zero output conductance causes limited DC gain and dominant pole, as shown in equation

(4.14). Moreover, in figure below, one can see that the deviation of the integrator occurs above -90°. The transfer function can be redefined as: 33

(4.15) . ) = . . = ) ) The Non-ideal integrator phase error:

(4.16) ) = Hjω) + 90° The Quality factor Q is described as:

) (4.17) ) = ) = tan− )

4.3 Fourth Order Maximally Flat Low-Pass Filter

Since the proposed OTAs are designed for Electroencephalography data acquisition system, maximally flat low-pass filter are chosen to optimize its capability obtaining data at the desired frequency range. A 4th order maximally flat filter is

designed with biquad structure, which provides flexibility to integrate different sets

of transconductor blocks. In the following sections, biquad structure will be discussed

along with the low pass filter architecture and supporting circuitry.

4.3.1 2nd Order Biquad Block Structure

As described in the above sections that Transconductance-C filter utilize same components as RC filter, but in the transconductor equivalent components. To review the structure of RLC circuit in biquad configuration, a model circuit is shown in figure below.

Figure 4.6. (a) RLC equivalent circuit. (b) Norton’s equivalent circuit.

Since transconductor converts the input voltage into current output, Norton’s equivalent theory is applied to the circuit, as shown in (b). The transfer function can be defined as:

(4.18) ) = =

(4.19) = .

(4.20) =

To see the big picture of how transconductor equivalent circuit can produce the same transfer function as the RLC circuit, one should started converting the passive elements that explain in previous section into gm building blocks.

Figure 4.7. 2nd Order single ended and fully differential biquad structure.

A single ended output and fully differential biquad structures are shown in figure 4.8. One advantage of biquad structure is the dual output characteristics. A band-pass and low-pass filters can be produced depending where output pairs are taken. Gm1 performs voltage to current conversion; Gm2 characterizes a resistor-like behavior and Gm3 and Gm4 represent a gyrator element. Capacitor C1 and C2 are there to complete RLC circuit behavior. The transfer function of 2 nd order biquad is

defined as:

For band-pass filter: (4.21) .. ) = = −

For Low-pass filter: (4.22) ∗ ) = =

The transfer functions show that there are only two elements that control the filter performance which are the OTAs and capacitors. Therefore, a robust tuning range and wide range performance can be approached.

4.3.2 Low-Pass Filter Implementation

Besides of its dual output capability, biquad structure is also useful if one wants to perform a higher order filter. Typically, a cascade model can be used in biquad structure because it can sustain its stability in higher order filter. However, one should be aware that by increasing its order, the loading effect increases as well.

Therefore, a thorough calculation should be done at first place.

A 4 th order maximally flat biquad low-pass filter occupies cascade design of

two biquad structures. The complete structure can be observed in figure 4.9. One

may notice that the output stage of gm1, gm2, and gm4 are connected, the common

mode feedback circuit can be reduce to only one common circuit to control the

common mode noise. Gm3 has its own common mode circuit because it does not

have direct connection to other output stage. These design is also valid the next

cascaded structure.

Figure 4.8. A 4th Order Maximally Flat Low-Pass Biquad Filter.

A typical transfer function of a 2 nd order filter low-pass filter is defined as:

(4.23) ) =

The cutoff frequency and the quality factor Q can be expressed as:

(4.24) ) = ; =

In biquad structure, two tuning methods, gm or capacitor tuning, can be

performed. However, since the capacitors are integrated with all the transistors in

one chip, tuning the transconductors are more feasible because no physical

modification is required. Therefore, the cutoff frequency and the quality factor can

be simplified as:

(4.25) = =

Where gm=gm1=gm3=gm4 and C=C1=C2. Therefore, the ratio of transconductors gm and gm2 of both biquad structures are:

(4.26) = 1.848 = 0.765

Since the 4 th order maximally flat filter is a combination of two 2 nd order structures, the normalized transfer function is defined as:

(4.27) ) = .

(4.28) ) = .

Combining equation (4.26) and (4.23), the overall transfer function is expressed as:

) (4.29) ) = .).)

As shown above, to meet the design specification of maximally flat filter, the quality factors must be set to Q1=0.54 and Q2=1.31. Once all these calculations are done, tuning the transconductors will be more practical.

4.3.3 Extra Circuitry

After done designing the filter block, extra circuit blocks have to be added in order to measure the filter performance. Biasing circuit and Output buffer are the typical blocks used in transconductors based filter. Since the filter block includes eight OTAs, routing its bias point takes quite amount of length. In this case, current routing is applied instead of voltage routing in order to prevent voltage drop along the routing line. In figure 4.10(b), cascode current mirror structure is shown to form a biasing circuit [23].

Figure 4.9. (a) Extra circuit blocks. (b) Biasing circuit. (c) Output buffer.

An output buffer is required to avoid loading effect from the test equipments.

There are two methods to design the output buffer. First, the buffer can be designed by using another transconductor based resistor. And it can also be designed by occupying a source follower buffer, which is preferable in this design. The source follower type buffer (fig.4.10c) is more ideal because the DC gain supposes to be 0 dB meaning that it will pass through the signal without affecting its characteristic.

However, in practice, one has to allow this buffer to consume much more current to reach that 0 dB operating point, otherwise, the buffer will also load the filter and degrade the filter signal.

Chapter 5 : Simulation Results and Discussion of OTA-C Filter

The OTA and filter are designed to meet certain specifications that decide how well the performance of the system. Several standard parameters are observed for example: frequency response, common mode rejection ratio, input offset voltage, power supply rejection rejection ratio, harmonic distortion and etc. In the following sections, simulation results of transconductor and low-pass filter will be discussed in detail.

5.1 Parameters

The following parameters are used to determine the performance of transconductor amplifier and the low-pass filter [21] [22] [24].

• Gain and Phase Margin

In order to determine the circuit stability at certain operating points, Gain and

Phase Margin are defined. The Gain margin determines how much the signal will be amplified. The Phase Margin shows the poles stability by looking at the phase shift at unity gain and taking the difference with 180 . A typical stable circuit has PM higher ° than 40°.

(5.1) = 20log

(5.2) ℎ = ℎℎ + 180°

• DC Power Supply Sensitivity

One should understand that the designed circuit should have good immunity of power supply sensitivity, which is usually calculated in term of Power Supply

Rejection Ratio (PSRR). PSRR is defined as the change at the output over the change in the input supply divide by the gain of the output over the supply, which can be written as:

(5.3) = =

Where A DM is the differential gain and A DM-PS is the power supply gain. The higher the

value, the less sensitivity the circuit is.

• DC Common-mode sensitivity

Common Mode Rejection Ratio (CMRR) is a measurement about how well the circuit can reject DC common mode signal. CMRR is described as the ratio of differential-mode gain over common-mode gain, which shows as:

(5.4) = 20.. =

In this case, a high CMRR value means that the circuit has great capability to reject input common mode noise.

• Power Dissipation

The circuit dissipates an amount of power based on the supply voltage and current consumption. Mathematically can be described as:

(5.5) = ∗

• Harmonic Distortion

It is known that in nonlinear system, when one applies a sinusoidal signal, the output signal will have its fundamental sinusoidal signal along with its harmonics. It is usually a multiple of its fundamental frequency. Ideally in fully differential structure is utilized in this design, the even-order harmonics should be zero. However, in some case, there might be some values due to mismatch in the differential circuit. The output signal can be defined as:

(5.6) ) = ℎ. ) + ℎ. ) + ℎ. ) + ⋯ + ℎ. ) Since the even-order harmonics are a lot smaller compare to the odd-order harmonics and only 3 rd order harmonic that is the most dominant harmonic, the

equation can be simplified to:

(5.7) ) = ℎ. ) + ℎ. ) 44

In AC signal representation, the output function can be described as:

(5.8) ) = . cos ) + . cos 3 ) Combining equation (5.7) and (5.8), 3 rd order harmonic distortion is defined as:

(5.9) = =

Where the H is the amplitude of harmonics, h1=H1, and H3=h3 (A2/4).

A Total Harmonic Distortion (THD) determines how much distortion that the

harmonics frequencies affect the fundamental frequency. By knowing THD value, one

could predict if the output signal of the circuit is useable or not. Typically, THD should

be more than 1% of its fundamental frequency. In mathematical language, THD is

defined as:

⋯ (5.7) = ∗ 100%

5.2 Performance of Designed OTAs and Maximally Flat Filter

5.2.1 Pre-Simulation results of Transconductor and Filter

OTA Characteristics:

In this section, pre-simulation is shown. Parasitic capacitance and resistance are not included. In figure 5.1, 5.2, and 5.3, three corner simulation results for the 45

OTA DC gain and phase margin are shown. Typical values for the gain and phase margin are 40dB and 88°.

Figure 5.1. OTA frequency response at typical typical (TT).

Figure 5.2.OTA Frequency response at fast fast (FF) corner.

Figure 5.3.OTA frequency response at slow slow (SS) corner.

In figure 5.4, the transconductance is tuned to have input voltage linear range about 400mVpp at 2.8 nA/V. The linearity range can be observed on the flat line area of the curve. Since the OTA is tunable based on the source degenerated resistor, different variation of tranconductances are shown in figure 5.5. The variation shows that the minimum transconductance is about 2 nA/V and maximum at 4 nA/V.

Variation may be larger if bias current is included as tuning variable.

Figure 5.4. Gm variation in some input range. 47

Figure 5.5. Tranconductance values at different tuning voltage of source degenerated resistance.

Common Mode Rejection Ratio (CMRR) and Power Supply Rejection Ratio are simulated with three different corners. As shown in figure 5.6, the typical gain for

CMRR is at 91.9dB and it varies about 2dB at different corners. Figure 5.7 shows that

PSRR typical gain is at 95.3dB and varies 3dB between corners.

Figure 5.6. Common mode rejection ratio at different corner.

Figure 5.7. Power supply rejection ratio at different corner.

Another important parameter to observe is about circuit common mode feedback settling time. In figure 5.8, it shows that the DC voltage is stabilized within

22μS from peak 1.5V to the DC bias point, which is at 0.9V. By observing the settling

time response, one can see whether the system is fast enough to get ready receiving the input ac signals.

Figure 5.8. Common Mode Transient Response.

Figure 5.9. Filter frequency response at TT, FF, and SS corner.

In figure 5.9, corner simulation for the filter is shown. At typical condition, the

3db cutoff frequency is at 42.3Hz and varies about 2Hz at different corners. Third order distortion (HD3) of the filter is shown below. Since the system is fully differential, 2 nd order harmonic is almost negligible. The 3 rd order harmonic becomes the next highest harmonic after the fundamental tone. In figure 5.10, it shows that the HD3 is at -56.4dB. Tuning range of filter is set to cover all major brain waves, as shown in figure 5.11.

Figure 5.10. Filter HD3 analysis at 40Hz 0.4Vpp input signal.

Figure 5.11. Filter tuning range.

5.2.2 Post-Simulation results of Transconductor and Filter

In this section, post-simulation results are shown. Post simulation means that the simulation was performed with the extra resistances and capacitances from transistors routing and interconnection between blocks. Some useful layout techniques can be found in [25]. Three different corners are simulated to make comparable results with the previous simulation. A comparison table can be found later in this section. The results show that typical DC gain is at 39dB (down about 1 dB) and the phase margin at -85.6dB (down about 2.4°). The corner variation difference is only about 1dB.

Figure 5.12. OTA frequency response at TT corner.

Figure 5.13. OTA frequency response at SS corner.

Figure 5.14. OTA frequency response at FF corner.

In figure 5.15 and 5.16, post-simulation of CMRR and PSRR are shown. Both results vary about 2-3 dB compared to the pre-simulation.

Figure 5.15. Post-sim CMRR at different corner.

Figure 5.16. Post-sim PSRR at different corner.

Another important simulation is Montecarlo method. By using Montecarlo simulation, random samplings are used to perform wide range of variables. In this case, TSMC Montecarlo random samplings are used. In figure 5. 17 through 5.20,

Montecarlo analysis is performed for the OTA block. The resulting figures show that this OTA block performs very close to the corner simulation.

5.17. Gm in montecarlo analysis.

5.18. Gain and phase in Montecarlo analysis.

5.19. CMRR in Montecarlo analysis.

5.20. PSRR in Montecarlo analysis.

In figure 5.21, post-simulation for filter response is shown. At typical corner cutoff frequency is about 41.4Hz and varies from 36.5 to 47.6Hz at different corners.

Figure 5.22 shows that the 3 rd order harmonic distortion is about 52.3dB. It reduces about 5dB from pre-simulation due to parasitic capacitance and resistance from the poly and metal layer.

Figure 5.21.Post-sim filter response at different corner.

Figure 5.22. Post-sim filter HD3 at 40Hz 0.4Vpp input signal.

In table 2, a comparison between pre and post simulation parameters are tabulated. The post simulation shows that third harmonic and total harmonic

distortion decrease about 4 dB due to the extra resistance and capacitance from layout routing and pads. Additionally, table 3 shows a comparison of this work with previously published literatures. The implemented chip can be observed in figure below.

Figure 5.23. Chip photo.

OTA Specification Target Post-simulation Power supply (V) <2.6 1.5 Total Current (nA) <1000 592.76 Power Dissipation (nW) <2600 889.14 DC gain (dB) 30 39.2 Transconductance 2-4 2 - 4 (nA/V) HD3 (dB) >40 52.3 THD (dB) >40 50.5 CMRR (dB) >60 89 PSRR (dB) >60 92.5 Phase margin (degree) >45 85.6 Filter Specification Power supply (V) 2.6 1.5 Total Current (uA) <10 3.157 Power Dissipation (uW) <26 4.735 Cutoff frequency (Hz) 4-50 4 to 50 Table 2. OTA and filter specification.

Reference [19 ] [20 ] [4] This work Technology 1.2uM CMOS 1.2uM CMOS 0.6uM CMOS 0.18uM CMOS HD3 -40dB@ 10Hz -40dB@ 1Hz -61.5dB@ 8Hz -52 dB @40Hz Input Swing Range 20 mVpp 240 mVpp 50 mVpp 400 mVpp Transconductance N/A 11.55 nA/V 3 nA/V 2 to 4 nA/V Supply Voltage 3 V 2.6 V 3 V 1.5 V Power Dissipation 15 uW 8.18 uW 11uW 4.7uW Input Referred Noise 15 uVrms 17.3 uVrms N/A 16 uVrms

Capacitor Off -chip Off -chip Off -chip On -chip

Table 3. Literature Comparison.

Chapter 6 : Conclusion and Future Work

6.1 Conclusion

Design works and the implementation procedures of the operational transconductance amplifier (OTA) and a maximally flat low-pass filter are introduced.

The implemented low-pass filter can be used in portable Electroencephalography data acquisition system to filter out the unnecessary analog data from the main signals. The performance of continuous time OTA is proven to work well in sub-hertz frequency range and it also shows its advantages when compared to other available structures. One the most common drawbacks of OTA is its linearity range. In this thesis, a combination of tuned source degeneration and series-parallel current division is proven to be able to produce a good linearity without sacrificing other performance parameters. By occupying biquad filter structure which is implemented with several different OTA configurations, a higher order filter can be achieved simply by cascading its structure.

6.2 Future Work

As the process technology gets smaller, the performance specifications of analog circuits also get tougher. In implantable and portable biomedical devices,

supply voltage, circuit area and power consumption are very important parameters.

Designing and implementing a better OTA performance with the newest process technology would be a good topic for the next research project. Moreover, an automatic tuning capability and capacitance scaler could also be part of the improvement to increase its robustness.

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