2012

A Quarterly Publication of The Microelectronics Packaging & Test Engineering Council Volume 16, Number 4 WINTER

SEMI-THERM® EXECUTIVE BRIEFING: Thermal Management Market Visions & Strategies page 17

In Association with

Like several other Silicon Valley success stories, Altera Corp. emerged from a legendary primordial broth: alumni of Fairchild Semiconductor, a bedroom office, and a profound shift in the industry. page 20

INSIDE THIS ISSUE

From 2004 through The Internet of What are the The Coming 2011, the packaging Things has the key multi Era of Intelligent materials market has potential to change integration Medical Systems grown at an annual the world, just as challenges for (IMS). rate of over 10%. the internet did. SATS providers? 14 23 26 SPRING 201134 MEPTEC Report 3

BOARD LETTER

Linking the Pieces in an Expanding Packaging Universe

Dr. Raj Pendse, Vice President of Advanced Products and Technology Marketing STATS ChipPAC MEPTEC Advisory Board Member

If you are a Packaging lover a judicious blending of Si and Packag- Even as the specific coverage of like me, you have probably enjoyed the ing technologies. In order to make this MEPTEC’s activities is continually ride up to here. Surely, we have come paradigm work it is imperative to link a evolving as technology progresses, its a long way from the days when people myriad different elements ranging from basic mission to provide an inter disci- would ask “if you are a Packaging Engi- Si fabrication, Packaging, Design and plinary meeting ground for intellectuals neer, you must be very busy during Test (to name a few). Enter MEPTEC, an remains the same – I encourage you Christmas?!?” (ouch) Happily, it is fair to institution that has been with us for many to join many others in participating in say that today Packaging has evolved into years and provided a forum for seamless MEPTEC’s diverse and dynamic activi- a significant part of the overall electronic discussion and meeting of the minds in ties so our happy ride may continue into solution and perhaps a discipline with semiconductors, packaging, test, and a the future. ◆ enough depth that many universities even diversity of products and end-applications. offer doctorate programs on Packaging Hence, it did not take much convincing Dr. Raj Pendse is Vice President topics. for me to accept MEPTEC’s invitation last of Advanced Products and Technol- It is worthwhile to take a look at where year to enlist me as one of its Advisory ogy Marketing at STATS ChipPAC. we have been, where we are going and Board Members. Prior to joining STATS ChipPAC, Raj what the challenges are in getting there. Through its various programs and held various positions in package We are in the midst of a rapidly chang- forums that range from monthly luncheon engineering and R&D at National ing Packaging industry landscape. The talks on topics of interest in an informal Semiconductor Corp. and Hewlett- traditional approach of a substrate-based setting, to sponsored conferences on per- Packard Labs. His work has spanned package comprising a die attached to a tinent subjects like 3D TSV, MEMS and the gamut from packaging of high-end lead frame or laminate substrate is giv- Medical electronics, and the publication , ASIC and graphics ing way to packaging at the wafer and of their Newsletter, the MEPTEC Report, products to low-cost packaging solu- Si level, with interconnection schemes that covers many topics of direct interest tions for logic and analog devices that changing from wire bond to and to professionals in these important disci- find use in mobile phones and con- Through Si Vias (TSV’s) and I/O densi- plines, MEPTEC provides the mechanism sumer products. His most recent focus ties increasing rapidly with finer Si nodes. to link the pieces in our expanding Pack- has been on Flip Chip and 3D Wafer The seemingly independent trajectories of aging universe. MEPTEC’s role is all the Level Packaging. Raj completed his integration at the die level in the form of more important today given the landscape B.S. in Materials Science from IIT SoC () and integration changes we talked about above and what Bombay with Top in Class honors and at the package level in the form of SiP seems to be an increased number of “mov- his Doctorate in Materials Science (System in a Package) are converging into ing parts” that need to be pulled together from UC Berkeley. a superset of 3D packaging which rely on in the construction of a working solution.

FIRST ANNUAL INTELLIGENT MEDICAL SYSTEMS CONFERENCE The Coming Era of Intelligent Medical Systems: Bringing Biomedical Devices to Life Tuesday, April 9, 2013 A University of Texas at Dallas Event in association with MEPTEC IMS 2013

For more information and to Register Today visit www.meptec.org or email [email protected] meptec.org WINTER 2012 MEPTEC REPORT 3 2012 The MEPTEC Report is a Publication of the Microelectronics Packaging & Test Engineering Council P. O. Box 222, Medicine Park, OK 73557 Tel: (650) 714-1570 Email: [email protected] WINTER A Quarterly Publication of The Microelectronics Packaging & Test Engineering Council Volume 16, Number 4 Publisher MEPCOM LLC Editor Bette Cooper Art Director/Designer Gary Brown 2012 On The Cover Sales Manager Gina Edwards A Quarterly Publication of The Microelectronics Packaging & Test Engineering Council Volume 16, Number 4 WINTER

SEMI-THERM® EXECUTIVE BRIEFING: Thermal Management Market Visions & Strategies MEPTEC Advisory Board page 17 SEMI-THERM, in association with MEPTEC and Electronics Cooling In Association with 17 Magazine, will present the SEMI-THERM Executive Briefing in Board Members March as part of the 29th Annual SEMI-THERM Conference and Exposi- Ivor Barber Xilinx, Inc. tion. The Executive Briefing titled “Thermal Management Marketing Jeanne Beacham Delphon Industries

Like several other Silicon Valley success stories, Altera Corp. emerged from a legendary primordial broth: alumni of Joel Camarda Amonix, Inc. Fairchild Semiconductor, a bedroom office, and a profound Visions & Strategies” will be held on Monday, March 18, 2013. SEMI- shift in the electronics industry. page 20 Jeff Demmin Tessera Inc.

INSIDE THIS ISSUE THERM runs March 17th to the 21st at the DoubleTree Hotel in San From 2004 through The Internet of What are the The Coming Douglass Dixon Henkel Corporation 2011, the packaging Things has the key multi die Era of Intelligent materials market has potential to change integration Medical Systems grown at an annual the world, just as challenges for (IMS). rate of over 10%. the internet did. SATS providers? 14 23 26 SPRING 201134 MEPTEC Report 3 Jose, California. Nikhil Kelkar mCube Nick Leonardi Premier Semiconductor Services Phil Marcoux PPM Associates

ANALYSIS

temporary bonding materials, new gen- material supplier base. Consolidation eration of underfill and encapsulants, is occurring at some levels. Leadframe Open Cavity Bhavesh Muni Dow Chemical Corp. ANALYSIS – Though market challenges exist for sup- dielectrics, and chemical mechanical plants have closed in recent years, espe- planarization (CMP) slurries. While not cially following the flood in Thailand QFN Packaging Materials Outlook new to the semiconductor industry, CMP in 2011. Hitachi Chemical has acquired is new to packaging. For TSV related Nitto Denko’s mold compound busi- processing, slurry suppliers can leverage ness, while Sumitomo Metal Mining and Dan Tracy, Senior Director their existing know-how developed for Hitachi Cable recently announced an Industry Research & Statistics, SEMI $50.74 $47.86 $48.59 copper interconnects, though control of agreement to integrate their leadframe $50 dishing in the larger TSV feature sizes businesses. In addition, earlier this year $44.84 Kumar Nagarajan Maxim Integrated $42.67 $42.52 and the higher copper removal rate are a Sumitomo Metal Mining announced its new challenges to be addressed. exit from the bonding wire market. pliers, new material solutions will be needed to deliver $40 For A NuMber oF yeArS NoW, $37.25 Any new material must be compat- Counter to some of the consolidation, the semiconductor industry has been $35.26 ible with high-volume manufacturing of material suppliers in Korea and China Your described as being in an “Age of Materi- $30.94 Die $28.81 high yielding and high reliability pack- seek a more prominent position in the $30 Here 14 als” as new elements, compounds, and ages. Material suppliers need to address market. Korean companies are focusing molecules have been integrated into both trade-offs when optimizing material on providing solutions to address oppor- device structures and packaging tech- $20 US$ Billions chemistries and formulations regarding tunities in the advanced and 3D packag- Fabless • MEMS • RF • Sensors Raj Pendse STATS ChipPAC nology. The latter has seen significant stress performance, moisture absorption, ing segment of the market. Some domes- changes in material sets as lead-free and adhesion strength, cure temperature, tic suppliers in China are boosting their halogen-free requirements have required increasingly complex and integrated packaging technologies $10 and other properties. While the industry capacity and technological capabilities to new formulations and chemistries to recognizes that thermal and stress man- serve the growing package & assembly meet new demands in semiconductor agement are key in integrating packaging operations located there. packaging. In addition, new and increas- $0 material solutions, it is expected that Though market challenges exist for ingly complex packaging form factors 2004 2005 2006 2007 2008 2009 2010 2011 2012F 2013F volume ramp of 3D configurations will suppliers, new material solutions will be require materials that deliver enhance Packaging 11.95 12.77 15.54 17.59 18.32 17.51 21.8 23.67 24.24 25.02 expose new mechanical and thermal needed to deliver increasingly complex Rich Rice ASE (US) Inc. device performance and improve reli- fab 16.86 18.17 21.7 25.08 24.19 17.75 23.05 24.19 24.35 25.72 issues. and integrated packaging technologies (866) 404-8800 ability at both the package-level and Totals may not add due to rounding. As new opportunities emerge in that will benefit the end consumer in an board-level. Advancements in materials Figure 1. supplying materials, there are changes ever more mobile and interconnected that will benefit the end consumer in an ever more mobile technology will continue as 3D packag- ◆ underway throughout the packaging world. www.MirrorSemi.com ing through silicon-via (TSV) technolo- Other Silicon gies ramp as key focus areas over the Packaging Wafers next several years and beyond. Materials From 2004 through 2011, the pack- Jim Walker Gartner aging materials market has grown at a compound annual growth rate of over 21% 20% 10 percent, which is a reflection of the material changes in packaging. The and interconnected world. packaging materials market is expected Underfi ll for Your Current to surpass $24 billion in 2012 and grow innovAtion to $25 billion in 2013. When compared 21% 30% and Future Requirements to wafer fab materials sold into the semi- AutomAted precision mAchining John Xie Altera Corporation conductor market, the share of packaging 8% At Treske, we specialize in the materials has increased over this time- impossible: efficiency in low volume, frame: from 41% in 2004 to almost 50% high mix runs with critical tolerances. share forecasted for 2012. Preliminary Our robotic cell-manufacturing process estimates show total packaging revenues leverages 30 years’ of semiconductor NAMICS is a leading source for high approaching $26 billion by 2014. (See Plastic expertise, while real-time quality technology underfi lls, encapsulants, Figure 1.) Other Fab Substrate control ensures predictable results. coatings and specialty adhesives used The growth in the share of packag- Leadframe Materials • by producers of semiconductor devic- ing materials consumed by the semi- Prototype and es. Headquartered in Niigata, Japan conductor industry parallels the ramp Figure 2. Estimated 2012 Market Breakdown by Materials Segment. Source: SEMI and TechSearch Production machining with subsidiaries in the USA, Europe, in laminate substrate based packaging. • Electromechanical assembly Singapore and China, NAMICS serves beginning in the late 1990s and into the substrates consumed in these technolo- market is forecasted to grow to $11.1 By DAN TRACY • Welded fabrication its worldwide customers with enabling 2000s, new package types based on lam- gies, the share of packaging materials billion in 2013 and up to $11.6 billion in Special Advisors products for leading edge applica- inate (plastic) substrate technology were consumption has increased. 2014. (See Figure 2.) Call today to realize an entirely new tions. introduced into the market. ball grid In terms of total material revenues, With 3D packaging and TSV, oppor- way of precision machining! array (bGA) and flip chip packaging laminate substrates now represent a tunities will grow for materials solu- were the early volume drivers, though market larger than that reported for sili- tions to packaging technologies that are For more information visit our website this technology was further developed con wafers. Total revenues for laminate increasing front-end/fab oriented such as or call 408-516-4611 for usage in chip-scale, stacked-die, and substrates are expect to reach $10.4 bil- wafer bumping redistribution and via for- (503) 625.2821 | treske.com SEMI package-on-package technologies. As a lion in 2012 compared to $9.7 billion for mation and filling. Solutions will require ISO9001:2008 | AS9100C (April 2013) | ITAR www.namics.co.jp result of the new materials and advanced silicon wafers. The laminate substrate newer materials and processes such as Bance Hom Consultech International, Inc. 14 MEPTEC REPORT WINTER 2012 meptec.org meptec.org WINTER 2012 MEPTEC REPORT 15 Ron Jones N-Able Group International Mary Olsson Gary Smith EDA

PROFILE Mike Pinelis MEMS Journal, Inc.

gave them insight into design teams’ At the same time, Altera’s volumes PROFILE – Altera continues to push forward on their needs, Hartman, Newhagen, and had grown to the point where the com- Magranet called in two more Fairchild pany no longer needed to shop around alumni, semiconductor process expert for the best deal on surplus capacity in Jim Sansbury and ex-Fairchild CFO Jim mature processes. Altera was ready to be Hazle, and set about forming a company. a partner with a first-tier foundry and be After the then-obligatory pilgrimage one of the first users of a new process Three Decades of Programmable Logic Innovations to Menlo Park, California, in search of node. This in turn meant that for the first venture capital, the new team received an time, FPGAs could offer something like Honorary Advisors initial $500,000 and in June, 1983 they parity with gate-arrays. The density and original promise: bringing system design teams the officially launched Altera Corporation to performance of an FPGA-based design in design and sell alterable logic devices. a leading-edge process could challenge process started over, with submitting a A half million dollars at that time, the density and performance of the same 20 Like several other Silicon new design and paying additional NRE. when as CEO design implemented with a contemporary Valley success stories, Altera These issues put gate arrays beyond TJ Rodgers put it, “Real men own fabs,” mainstream gate array process, which Corp. emerged from a leg- the reach of many design teams—a fact was a very small initial round for a would be about two nodes older. Seth Alavi Sunsil endary primordial broth: that particularly interested three Fairchild semiconductor company. But along with During the early 2000s, these two veterans. Bob Hartman, Paul Newhagen, being a pioneer in PLDs, Altera was shifts brought about a third change: alumni of Fairchild Semicon- ability to define just the silicon they need and implement it and Michael Magranet had formed a pioneering in another area as well: the inclusion of specific hard intellectual- ductor, a bedroom office, consultancy to help system design teams fables semiconductor model. The com- property (IP) blocks such as SRAM, MOS process technology, develop gate arrays. In a 1982 book on pany would design and sell chips, but serial transceivers, and multiply-accumu- and a profound shift in the the subject, the three speculated about would contract with other companies’ 2.5D test chip Altera developed leveraging lators. These functions were increasingly TSMC’s CoWoS process. electronics industry. But the imminence of a new approach: a gate fabrication facilities to actually fabricate necessary in FPGAs’ new role as sys- tems-on-chips (SoCs) and could be done unlike Intel – arguably the array that could be configured electrical- the wafers and do the packaging and Gary Catlin Plexus customer could specify how the metal ly, instead of during the manufacturing test. In principle, this approach would tively small fabless company, Altera had more efficiently in hard IP. As SoCs, most famous of these sto- layers on the chip should interconnect process. Such a device would eliminate give Altera access to the latest process been conservative about adopting new FPGAs were also pushing to higher pin ries – Altera’s mission has not the gates to form exactly the circuits the NRE, remove the long wait, mitigate the technology without the growing capital process nodes. Neither customer needs on-site, without delays or inordinate risks. But the company involved changing the world system required. risk, and delete the minimum-order limits investment necessary to stay near the nor the company’s resources advised an as we know it. Rather, Altera This gate-array approach offered of conventional gate arrays. leading edge in wafer manufacturing. aggressive move to an unproven new has worked profound chang- system designers substantial advantages Altera introduced its first PLDs in 1984. process. But by the mid-1990s the pic- in system performance, size, and power Later, in 1992, after process technology ture was changing. Customers increas- es in the invisible infrastruc- Altera is Born by packing just the digital logic circuits had moved forward several generations ingly used FPGAs not just in fixed-speed Rob Cole ture of electronics – altering the design needed into one chip (or a few the company returned to the founders’ interfaces and bridges, but also in control not what the industry pro- chips). In fact, such chips did appear as original vision of an electrically-alterable and data paths, where FPGA perfor- duced so much as the speed, But there were costs. Developing the commercial products shortly after this gate array with the FLEX 8000, the mance directly influenced system perfor- configuration for the gate array required prediction, but in a slightly different company’s first field-programmable gate mance. is carrying this to a new level... cost, and risk of the design workstations, design tools, and special process. form than the authors had anticipated. array (FPGA). skills, all of which were more familiar to At the then-current state of MOS tech- From the beginning, programmable chip design teams than to system design nology, it turned out that the logically logic offered a trade-off. Users could teams. The gate-array vendor charged a ideal structure—a vast array of gates that have exactly the logic they wanted—even Skip Fehr significant up-front fee, which came to would have the same basic topology as a in very low volumes—without the NRE, The Customer-Designed IC be called, rather ironically as it turned gate array—was impractical. Instead, the wait, and risk of gate arrays. But because out, non-recurring expense (NRE). The ideal solution for the time was a tree-like the devices use latches and switches The Altera story begins with an time between submitting the design and structure that produced logic functions: a in place of fixed metal lines, PLDs are early, seminal change in the way system receiving the chips was often months, Programmable Logic Device (PLD). necessarily less dense, slower, and less designers implemented digital elec- and sometimes many months, especially Not intending to be left out of the trend energy-efficient than the same logic tronics. In the 1970s, designers in IC if the customer was small. And if there they had identified, and believing that implemented in a gate array. At the same companies composed integrated circuits were a problem with the chip, the whole their experience in gate-array design time, the applications for programmable Anna Gualtieri Elle Technology by hand. System designers then cre- devices—initially in interfaces, bridges, ated digital systems by wiring together and controllers—tend to require large these standard-product ICs. But by 1980, numbers of pins. So Altera has from its altera corporation another approach had appeared: one that early days challenged packaging technol- allowed the system designers far greater ogy to provide high pin counts and good freedom. heat dissipation at reasonable prices. The semiconductor vendor didn’t, in this new approach, set the function of Marc Papageorge Semiconductor Outsourcing the IC in stone ahead of time. Instead, Three Transitions the chip company could create an IC that was simply a vast array of uncommitted Just over a decade ago Altera execut- 2.5D heterogeneous devices mixing programmable logic with a variety of other technologies, Member company profile logic gates. Then the system-designing Altera’s current 28nm portfolio of FPGAs. ed a change in strategy. Earlier, as a rela- in a single package.

20 MEPTEC REPORT WINTER 2012 meptec.org meptec.org WINTER 2012 MEPTEC REPORT 21

Contributors

TECHNOLOGY – The phrase “” was TECHNOLOGY Jianwei Dong Packaging Technology for the Internet of Things Dow Electronic Materials

Jayna Sheats, CTO coined in 1999 by Kevin Ashton at Proctor & Gamble Terepac Corporation 23 a b c THE PHrASE “InTErnET OF THInGS” Maybe even more so.”1 of these digital devices – soon to number Figure 2. Aerosol printing of conductor (often abbreviated IoT) was coined by This vision is very much on the in the trillions – are being connected precursor over nominal 25 μm chip edges. Ira Feldman Kevin Ashton (then – 1999 – a brand agenda of many companies, both large through the Internet. Some call this the Clockwise from upper left, the images manager at Procter and Gamble), in a and small, today. In January 2010 ‘Internet of Things.’” show a) NXP Mifare 1k; b) MSP430; c) 2x2 company presentation where he drew Samuel Palmisano, then CEO of IBM, The space is not only for the For- mm UHF radio, with test chip at the jog at in a presentation where he drew attention to the value of the bottom; d) 160x160 μm test chip (single attention to the value of having “things” addressed business and civic lead- tune 500. A few months ago I counted metal layer), 25 μm pads; e) NXP Mifare 1k be able to report information about them- ers at Chatham House in London with well over 25 early-stage startups with (95 μm pads). selves besides just their identity. Ten these words: “Enormous computational sensor technology explicitly directed years later, he acknowledges that rFID power can now be delivered in forms to the Internet of Things (not counting Feldman Engineering Corp. remains at center stage, and this misses so small, abundant and inexpensive that software, communications technology, e d a huge part of his vision: “It’s not just a it is being put into things no one would or computational systems for digest- “bar code on steroids” or a way to speed recognize as : cars, appliances, ing the data and extracting value from up toll roads, and we must never allow roadways and rail lines, power grids, it). And yet commercial success seems ogy which “will take at least another Packaging for Pervasive Computing would have the best chance of achieving having “things” be able to report information about them- our vision to shrink to that scale. The clothes; across processes and global sup- to be some distance away. The Gartner decade to unfold”, placing it slightly Joel Birnbaum, former head of r&D true pervasive permeation of all aspects Internet of Things has the potential to ply chains; and even in natural systems, Group’s “hype cycle” analysis last year more than halfway up to the “Peak of at Hewlett-Packard, has defined “per- of our surroundings (as well as our bod- change the world, just as the Internet did. such as agriculture and waterways. All characterizes it as an emerging technol Inflated Expectations” (which means that vasive technology” as one which is not ies). it is still confined to the earliest of early only ubiquitous, but is so much a part of In order to bring the power of silicon adopters). life that it is simply not noticed by most ICs into such label formats, thinness is people. The realization of this definition essential. Silicon becomes flexible at a Shashi Gupta (a) Pre-Press (b) Printing Requirements for Commercialization may take many specific forms, but it thickness of about 50 μm. Following What, then, is needed to move from seems evident that conventional PCBs, experimentation beginning in the late Diced, thin chips are transferred en masse to transfer Printhead is brought into this stage to a realization of the vision so even if “small” (such as a Bluetooth 1990s, processed wafer thinning is now selves besides just their identity. substrate coated with Digital Release Adhesive™. proximity of substrate. vividly articulated by Kevin Ashton and headset, for example) cannot fade into relatively commonplace and can be taken Samuel Palmisano? Many of the barriers the background if they are to be attached to less than 10 μm. However, such thin are not technological. Business manag- to the human skin as a wound monitor, or wafers, while readily and reversibly ers have to be convinced of the value for placed on or in food packaging (or even bent, are extremely fragile if subjected Henkel Electronic Materials, LLC them, which takes clearly demonstrated directly on food, such as fresh produce) to localized stresses, making it difficult successes. Different parts of an organiza- to report freshness and quality. Even to use conventional pick and place tools Light + heat causes vaporization of the DRA, leaving chip adhered to adjacent substrate. tion, and different organizations, perhaps in cases where extreme thinness and with their vacuum tips and ejector nee- in very different industries, have to learn flexibility are not apparently absolutely dles. to work together in new ways. Lack of essential, traditional electronic packaging A second problem with existing tech- fully developed standards for data format may be a poor fit. Suppose, for example, niques is chip size. ICs for the IoT can Thin, diced wafer (preferably <50 µm) on thermal or UV makes it difficult for a company to effec- that one wished to include some sort of be far smaller than nearly all chips made released adhesive on framed backing tape. tively insert itself into the supply chain. wireless sensor in building insulation. today: the complete for the nevertheless, there are important Installation of a conventional package original IBM PC would occupy a square technological limitations which must be requires a mechanical operation which of merely 160 μm in 90 nm lithography. eliminated to fully realize the vision. A is unlike any that is part of the current Such sizes are not amenable to high- Donald Hicks, Ph.D. BY JAYNA SHEATS perusal of IoT offerings shows that they production process; in a conservative throughput pick and place processing, typically cost in the range of tens to hun- industry such as that of building materi- but they have an even more serious dreds of dollars, and are nearly always als, this may present a major obstacle to problem: I/O pad dimensions would have provided on rigid circuit boards. Power widespread adoption. to be much smaller than are compatible requirements are such that AAA batteries Almost everything, however, has with the highest density flip chip pro- Printhead removes array of chips (on the underside of Only chips selected by optical exposure (shown in blue) are printed or lithium coin cells (e.g. Cr2032) are a label, including building insulation. cesses available. printhead; no charge in relative position from wafer). when the DRA is heated (T<150˚C). One or multiple chips can be required. All of this adds up to a pack- Even the aforementioned produce, down The University of Texas at Dallas printed simultaneously. age that is too bulky, rigid and costly for to the individual apple or banana, has a Terepac’s Photochemical Circuit TEREPAC CORPORATION many of the applications outlined above. label today. An electronic product which Assembly Process Figure 1. The PCA process. has the size, look and feel of a label Terepac approaches these problems

22 MEPTEC REPORT WINTER 2012 meptec.org meptec.org WINTER 2012 MEPTEC REPORT 23 Ron Jones N-Able Group International

PACKAGING PACKAGING – SATS providers face three key chal- Y. S. Kim TMD Those remaining voids are removed The added complexity to the stan- Multi Die Integration by the transfer pressure when the mold dard assembly processes demand that compound flows to fill the package at the SATS vendor have a process put in Signetics Corporation DAF molding. It can be difficult to remove the place specific to the needs of multi chip Y. S. Kim remaining voids at mold if the DAF has packages. A well systemized process flow Vice President of Engineering and R&D become too hardened at die attach cure and a custom control plan are absolutely Signetics Corporation and wire bonding. required to insure the yields are as good Trapped Void Another area to be aware of in relation as those of a single die package. Figure 2. DAF voids – stacked die package. to the DAF is the potential for top metal lenges when it comes to the assembly of multi chip damage. At molding, mold compound Summary / Conclusion flows to fill the entire mold cavity and The SATS provider must have a solu- Multi Chip paCkaging (MCp) processed from backgrind through wire then mold compound (including filler) tion for three primary challenges when 26 for memory devices as well as em- bonding process for multiple passes. So a will push the DAF by the pressure ex- assembling multi chip packaging. They Dr. Raj Pendse bedded Multi Media Cards (eMMC) more robust process flow system control erted by the mold compound. This pres- must have a unique assembly technology is required. sure on the DAF can create damage to the that is flexible for different variations of should be considered when discuss- One potential issue is the potential for top side of the bottom die. Removal of multi chip packages. Another challenge ing multi die integration based on the Typical Pyramid Stacked Die Package Same Size Die Stack die attach film (DAF) voids. DAF voids the voids and strong DAF adhesion help is thin wafers which keep the overall high volume manufacturing experi- can occur between the 1st die and the prevent this from causing the damage to package height at a minimum. The SATS packaging. Stacking multiple die in a package requires unique ence of semiconductor assembly Figure 1. Stacked die examples. substrate and can cause swelling which the top side metal. provider must have the equipment and and test services (SatS) providers. will cause a reliability failure. (See Another difference during the assem- knowledge of how to backgrind and STATS ChipPAC Both MCp and eMMC are widely because you are going from checking the is required such as DBG (Dicing Before Figure 2) To remove the DAF voids, a bly process for multi chip packages is the handle these ultra-thin wafers. Process used for Smartphones as a storage yields of one die to several in the same Grinding) or GAL (Grinding After stealth die attach cure process using a pressur- need for multiple die attach and wirebond flows must be made robust and yields ized cure oven is one solution. During passes. Processing the parts multiple must be monitored even more closely as solution. MCp is the package level package. Multi chip packages also have Laser sawing). the pressurized cure oven process step times through these process steps increas- multi chip packages have unique failure integration of heterogeneous memo- their own specific failure modes that must As SATS providers push the boundar- be monitored. And finally, you must have ies of how thin a wafer can be, there are the DAF voids are pushed out. However, es the potential for yield loss. The SATS modes. Multi chip packages require a ry chips, and eMMC is the further in- a very robust overall system to accept the trade-offs. One of the primary challenges not all DAF voids between the substrate provider must also be able to manage the well-planned strategy to overcome these ◆ assembly technology. Another challenge is backgrinding and tegration of nanD with a Flash Card challenge of assembling MCPs. for thin wafers is known as charge loss. and die are always completely removed. effect of heat during these passes. challenges. Controller and passives. the yield of Charge loss is an operating voltage shift multi chip packages becomes a criti- Stacked Die (Challenge 1) that can occur after repeated program cal consideration as the affected lot With the push from today and tomor- writing and reading. It can cause the row’s new technologies to be thinner, program to operate incorrectly and also Jayna Sheats size at the assembly step becomes smaller and more complex, there is a fast data loss. When thinning the die, the 2 to 5x larger than single chip pack- growing need to add multiple devices wafer back side should be polished to get ages if the low test yield is found at within the same package. One widespread strong enough die strength to prevent die the premier, US-based IC assembly and test subcontractor final test. additional critical steps solution for the memory device market level chip/crack during operation. How- handling. Finally, there are challenges for the process flow. that could affect the yield include the has been going in the vertical direction ever, this thinned/polished wafer isn’t IC Assembly I SIP & MCM I MIL/Aerospace I Wafer Thinning & Dicing I Environmental & Electrical Test I Engineering back grinding condition, Die attach by stacking the die. Depending on the protected from the Cu ion diffusion. type of devices, the types of interconnects To prevent charge loss, an optimized Terepac Corporation Film and its cure condition and po- tential filler damage during mold pro- and configurations of the interconnects, back grinding condition set up is abso- there are a few methods that the SATS lutely required. This can be controlled cess. the following information will industry has used to stack the die. These by selecting appropriate grinding wheel expand on what the key challenges can include many variations including and optimizing the wafer back surface are for the SatS provider when it pyramid stack, same die stack, same die roughness. comes to multi die integration. & pyramid stack and muti stack. (See There is a tradeoff between standard Figure 1) backgrinding and polishing. A finer polished wafer will give the die physical Key Challenges for Multi Chip Thin Wafers (Challenge 2) strength, however, it can be the cause of a Packaging With the requirement for thinner and charge loss. The traditional rough surface Wataru Tachikawa For the SATS provider there are three thinner end use applications and package grinding is better for preventing charge key challenges to be faced for the assem- thicknesses, the SATS provider must be loss, but, it can weaken the die strength. BY Y. S. Kim bly of multi chip packaging. Stacking also able to overcome the challenge of So the combination of an appropriate multiple die in a package requires unique working with thin wafers. polishing method and roughness control assembly technology that has to be flex- Typical wafer thickness was 200 to is key to preventing charge loss and keep- ible for different variations. Another chal- 250µm in the past. Now it is going down ing the die structurally sound. lenge is backgrinding and the handling of well below 100µm for the multichip Dow Electronic Materials thin wafers which keep the overall pack- package and those thin wafers required Assembly Process Flow (Challenge 3) age height at a minimum. Finally, there the wafer backgrinding surface to be The assembly process flow for www.corwil.com Excellent Quality and Superior Service 408.321.6404 are challenges for the process flow. Yields polished. As the wafer thickness is now multi die packages is more complex as Signetics Corporation must be monitored even more closely below 50µm, new thinning technology they have several different chips to be

26 MEPTEC REPORT WINTER 2012 meptec.org meptec.org WINTER 2012 MEPTEC REPORT 27 Dan Tracy SEMI

Francoise von Trapp DEPARTMENTS 3 Board Letter 11 Industry Insights Column 28 Henkel News 3D InCites 5 Member News 12 Coupling & Crosstalk Column 30 Dow Electronic Mtls. Howard Yun 18 Event Follow-Up 34 Opinion Henkel Electronic Materials, LLC

MEPTEC Report Vol. 16, No. 4. Published quarterly by MEPCOM LLC, P. O. Box 222, Medicine Park, OK 73557. Copyright 2012 by MEPTEC/MEPCOM LLC. All rights reserved. Materials may not be reproduced in whole or in part without written permission. MEPTEC Report is sent without charge to members of MEPTEC. For non-members, yearly subscriptions are available for $75 in the United States, $80US in Canada and Mexico, and $95US elsewhere. For advertising rates and information contact Gina Edwards at 408-858-5493, Fax Toll Free 1-866-424-0130.  MEMBER NEWS Plexus Expanding Design and Manufacturing  Advantest Operations in the UK Meeting Growing Demand Introduces T2000 8Gbps Digital for Product Realization Solutions Module for High- Plexus Corporation, ing 130 new jobs and a facility will be approximately Speed Testing the Product Realization new design, prototyping 47,000 sq ft and will include Advantest Corporation Company, has announced and manufacturing facility prototyping, manufacturing has introduced its new its intention to expand its in Bathgate. The Scottish and warehousing areas. The T2000 8GDM to address Livingston Design Centre to Government and our enter- site will complement Plexus’ the test requirements of larger premises at the Pyra- prise agencies are focused existing manufacturing system-on-chip (SoC) mids Business Park, in Bath- on securing new jobs, and facility in Kelso as well as devices with high-speed gate. Having worked closely investment and Plexus becoming a European centre serial, parallel and memory with Scottish Enterprise on expansion plans will receive of excellence for prototyping. interfaces such as PCI- funding support, Plexus will up to £1m of support through The co-location of design, expand its UK manufacturing Scottish Enterprise. News prototyping, and manufactur- Express and double data footprint by opening a new that this international design ing in one facility, enhances rate (DDR) connections. manufacturing facility at the and manufacturing firm the value proposition for The T2000 8GDM has the same location. is stepping up its Scottish Plexus customers and rein- versatility to test a wide Welcoming the news, operations is testament to the forces Plexus as the Product range of SoC interfaces First Minister Alex Salmond quality and skills of the West Realization Company in the while operating at data said: “Plexus’ decision to Lothian workforce and rein- UK. rates up to 8Gbps. Key invest £9 million in expand- forces Scotland’s reputation It is anticipated that both capabilities include clock ing their Scottish operations for excellence in innovation the design centre and manu- and data recovery (CDR), will provide a welcome boost and manufacturing.” facturing site will be opera- jitter injection, I/O dead to the local economy, creat- The new manufacturing tional in February 2013. ◆ band cancellation and multi-strobe operation. Advantest Develops Mask Defect Review SEM E5610 www.advantest.com For Next-Generation Photomasks  Entegris Named to List of 100 Most Advantest Corporation has Trustworthy U.S. announced that it has developed a new mask Companies defect review tool, the Mask DR-SEM E5610, Entegris, Inc. was named for reviewing and classifying ultra-small defects by Forbes Media to the in photomask blanks. The E5610 inherits the publisher’s list of America’s highly stable, fully automatic image capture 100 Most Trustworthy technology developed by Advantest for its acclaimed multi vision metrology SEM for pho- Companies. To develop tomasks, and features a newly developed beam the list, Forbes used data tilt mechanism that enables scanning at oblique generated by an indepen- angles. With its high-accuracy, high-throughput dent financial analytics firm defect review capability, the E5610 is expected up to 15°, enabling users to perform 3D defect called GMIRATINGS (GMI). to contribute to next-generation photomask reviews. GMI evaluated more than product quality improvement and shorter manu- Highly Stable, Fully Automatic Image 8,000 publicly held com- facturing turn-around times. Capture – Even when operating at high SEM panies on a broad range Photomask manufacturing processes require magnification, the E5610 performs stable, of metrics and company 100% eradication of fatal defects, which fully automatic defect imaging at a high rate of policies, including execu- adversely affect yield, in tandem with turn- throughput, thanks to its high-accuracy stage, tive compensation, man- around time reduction. Advantest’s new E5610 charge control function, and contamination promises to be an indispensable solution for reduction technology. agement turnover, insider mask manufacturers, satisfying both of these Compatible With Mask Inspection Systems – trading relative to corpo- requirements with fast, accurate technology The E5610 is compatible with mainstream mask rate peers, and short-term that classifies defects and diagnoses appropriate inspection systems: the tool imports defect loca- executive compensation. repair solutions with regard to type. tion data and automatically images the locations. While only three companies High Spatial Resolution & Oblique Scanning Elemental Composition Analysis Option – scored the highest score Capability – Advantest’s proprietary column The E5610 features an optional EDS (energy of 100, Entegris was one architecture delivers spatial resolution down dispersive X-ray spectrometry) module that per- of only two mid-cap com- to 2nm, even at the low acceleration voltages forms elemental analysis—an advanced method panies that scored a near appropriate for photomask screening. Moreover, of mapping mask blank defects. perfect 99. the E5610 features a unique, electrically con- for more information visit the Advantest  trolled tilt module that allows its beam to tilt by website at www.advantest.com. ◆ meptec.org WINTER 2012 MEPTEC REPORT 5 MEMBER NEWS

®  Amkor CEO Ken InvenSense Motion Interface Solutions for Windows Joyce to Retire 8 and Windows RT Shipping in High-Volume Amkor Technology, Inc. has announced that Ken Offering Two Microsoft Corporation Certified Options to Balance System Joyce intends to retire as Partitioning and Cost President and Chief Execu- InvenSense, Inc. has ing devices along with robust The UMD solution manages tive Officer and Director of announced that its HID and field-proven MotionApps Windows 8 protocols for the Company by the end of (Human Interface Device) software, providing OEMs low-power operation inside 2013, following more than and User-Mode Driver with a one-stop sensor sub- the intelligent MotionTrack- 15 years of service to the (UMD) motion sensing solu- system solution. ing hardware, without the Company. The Company’s tions for Windows 8 and InvenSense provides Win- need for a costly, discrete Board of Directors has Windows RT are in high- dows 8 and tablet sensor hub. created a search commit- volume production with manufacturers the option of Alternatively, the sensor hub ™ tee to identify Mr. Joyce’s multiple Tier-1 Ultrabook implementing either a sensor solution supports both HID- and tablet manufacturers. In hub solution inside a micro- over-USB and HID-over-I2C replacement. An executive collaboration with Micro- controller using the HID protocols running on popular recruiting firm has been soft, InvenSense ported its protocol, or the lower-cost microcontroller architectures. retained to conduct an MotionApps™ software to the option of a hub-less UMD InvenSense MotionTrack- outside search and also to new Windows 8 OS and its solution. Using InvenSense ing devices and MotionApps assist with the assessment solutions are now WHCK- intelligent MotionTracking software for Windows 8 and of internal candidates. certified for both Intel and devices, both solutions meet Windows RT are available www.amkor.com ARM architectures. This Microsoft’s requirements for today. For more informa- allows for rapid integration low-power screen orientation tion, please contact sales@ ◆  Quik-Pak of InvenSense MotionTrack- and connected standby mode. invensense.com. Expands New Open-molded Plastic Package STATS ChipPAC’s Advanced eWLB Provides Versatile Product Family Quik-Pak, a division of Integration Platform for 2.5D and 3D Technology Evolution Delphon, has announced eWLB Packaging Options Expanded to Include Interposer Technology, Flip Chip its 8-Lead SOIC (Small Interconnect and Complex 3D System-in-Package Configurations Outline ), the newest addition to STATS ChipPAC Ltd. has announced bump pitches, higher input/output (I/O) densities the Open-molded Plastic that its expanded packaging options for and the elimination of stress on extreme low-k Package (OmPP)™ product advanced embedded Wafer Level Ball Grid or ultra low-k (ELK/ULK) dielectric structures line. This 0.150” narrow Array (eWLB) technology provide a versatile at advanced silicon wafer nodes. eWLB’s fan- body package is built to platform for the semiconductor industry’s tech- out packaging approach with its inherently JEDEC standard MS-012 nology evolution from single or multi-die 2D lower stress, larger pad pitch, and redistribution and is RoHS compliant. package designs to 2.5D interposers and 3D layer (RDL) allows higher integration and rout- It is Ni/Au plated which is System-in-Package (SiP) configurations. ing density in less metal layers in an fcBGA The advancement of silicon scaling to 14 substrate. The fine line width and spacing capa- excellent for wire bonding. nanometer (nm) in support of higher perfor- bilities of eWLB provides more flexibility in the Quik-Pak’s 8-Lead SOIC mance, higher bandwidth and lower power package routing design and offers superior elec- has a standard 0.050” lead consumption in portable and mobile devices is trical performance, enabling the number of lay- pitch and a superior seal- pushing the boundaries of emerging packag- ers in the organic substrate of a standard fcBGA ing surface for air cavity ing technologies to smaller fan-out packag- device to be reduced. applications. Quik-Pak’s ing designs with finer line/spacing as well as STATS ChipPAC’s eWLB PoP solutions OmPP product family improved electrical performance and passive are available in either a single or double-sided includes pre-molded QFN embedded technology capabilities. With its configuration and provide a flexible integration (Quad Flat No-Lead) and continuous innovation and extensive manufac- platform for stacking a wide range of memory SOIC package configura- turing experience in eWLB technology, STATS packages on top with a final stacked package tions that are designed ChipPAC has established a flexible integration height below 1.0mm. The number of intercon- platform for 2.5D and 3D packaging at a lower nections between memory and processor can be to provide a high quality, overall cost with proven solutions that overcome up to 1024. The double-sided eWLB PoP tech- quick, and cost-effective manufacturing challenges pertaining to design, nology features a flexible redistribution layer solution for your IC pack- material compatibility and manufacturability. that can accommodate multiple active or passive aging and assembly needs. With the inherent performance and cost devices in complex 3D SiP structures which www.icproto.com advantages of eWLB, STATS ChipPAC is effec- enable very thin profiles, increased performance  tively addressing some of the challenges in high and superior warpage control. Further informa- end flip chip applications that require much finer tion is available at www.statschippac.com. ◆ 6 MEPTEC REPORT WINTER 2012 meptec.org MEMBER NEWS

 DigitalOptics Global Low-Cost Names New SVP of Sales & Marketing Tessera Technologies, Wafer Bumping Services Inc. has announced that its wholly owned subsidiary, • Europe – USA – Asia • DigitalOptics Corporation has appointed James N. “Jim” Chapman as senior vice president, sales and marketing. Chapman will report to Robert A. Young, the Company’s president and chief executive officer, and be responsible for DOC’s global sales and marketing initiatives. www.doc.com

Henkel’s  Quick-turn and Revolutionary mass-production Available Processes Loctite MAX 2 Highly competitive, Electroless Ni/Au under-bump metallization JEC Europe 2013 is the low-cost bumping biggest composites expo Ni/Au bump for ACF or NCP assembly technology in the world. Congregating Exceptional quality Solder paste stencil printing 250,000 professionals from through high-level Solder ball drop for wafer-level CSP 100 different countries, JEC expertise Europe 2013 will take place Solder jet for micro-ball placement this year from March 12 BGA and CSP reballing to 14 at the Porte de Ver- sailles, in Paris. Henkel, the Pac Tech GmbH Wafer backside thinning and wafer dicing Tel: +49 (0)3321/4495-100 world’s leading producer [email protected] Special Features/Technologies of adhesives, will present www.pactech.de Over 10 years experience composite solutions for the Pac Tech USA automotive and aerospace Tel: 408-588-1925, ext. 202 U.S. Government Certified industry. The main focuses [email protected] will be the innovative fast www.pactech-usa.com 4- to 12-inch wafer capability curing composite matrix Wafer pad metallization: Al and Cu Pac Tech Asia Sdn. Bhd. resin Loctite MAX 2 for Tel: +60 (4) 6430 628 Solder alloys: eutectic SnPb37, lead-free, [email protected] automotive and a complete www.pactech-asia.com low-alpha, and AuSn portfolio of Benzoxazine based composite products NAGASE & CO., LTD. Fluxless and contactless bumping for MEMS Tel: +81-3-5640-2282 for aerospace applications. [email protected] and optoelectronics Loctite MAX 2 is a polyure- www.nagase.co.jp Ni/Au interface for wire-bond applications thane based resin system that cures faster than traditional epoxy resins The leader in low-cost electroless wafer bumping. where as the Benzoxazine resin based composite and 450mm, 14nm Scaling Challenges to Highlight SEMICON Korea complementary products changes the paradigm of Technological and economic challenges to continued scaling and 450mm wafer development will highlight performance and tempera- conference programs and exhibitor displays at SEMICON Korea 2013, held from January 30-February 1 in Seoul. Co-located with LED Korea 2013, the largest exhibition in the world for LED manufacturing, the event ture profile of traditional will bring together global leaders in semiconductor manufacturing to share critical new technological develop- systems. ment and business opportunities. The events will feature over 500 exhibiting companies from 20 countries www.henkel.com and more than 45,000 attendees. Online pre-registration for visitors and programs is now in process for free  entrance to SEMICON and LED Korea 2012. For registration, please visit www.semiconkorea.org. ◆ meptec.org WINTER 2012 MEPTEC REPORT 7 MEMBER NEWS

 LSI Named One SonoSimulator Takes the Mystery Out of Stacked Die of the World’s Sonoscan, in Collaboration with T.U. Dresden, has Developed a Software Top Innovators Program that Creates a Virtual Model of the Echo Returns of the Die Stack LSI Corporation has announced that it has been Stacking die permits The stacked die manufac- named a Thomson Reuters designers to pack a great turing process or materials 2012 Top 100 Global deal of capacity and increase may evolve over time, which Innovator, recognizing its processing speed in a much may then require adjusted achievements as one of smaller volume. In the pro- parameters to properly image the world’s most innovative cess the die stack also cre- the stacked die levels. The companies. The program ates many internal interfaces SonoSimulator process honors corporations and where critical defects, such can be repeated to refine institutions worldwide that as voids and delaminations, the image(s) by adjusting are at the heart of inno- can lurk. Figure 1 the gate and recipe param- vation as measured by Makers of die stacks are eters on a revised virtual patent-related metrics. The very interested in using non- sample, and then moving the destructive acoustic micros- improved parameters back to Thomson Reuters 2012 copy, such as C-SAM®, to the C-SAM system to ana- Top 100 Global Innovator locate and image these criti- lyze the evolved sample. methodology is based on cal defects, but until recently figure 2 is the SonoSimu- four principal criteria: over- the die stacks have been lator derived C-SAM image all patent volume, patent far more difficult to image of a test stack sample having grant success rate, global clearly than other IC devices. 8 die with acoustically reflec- reach of the portfolio and The problem is that when tive numerals and bars etched patent influence as evi- ultrasound is pulsed into a on each die. In this image, denced by citations. The die stack, the numerous inter- Figure 2 the SonoSimulator provided Thomson Reuters 2012 Top nal interfaces create multiple the scan parameters to iso- 100 Global Innovator award return echoes in the A-Scan. defects act like real gap-type late and image the “known To speed up and sim- defects, reflecting >99.99% defect” specific to die 4 on recognizes companies for plify the task of assigning of the ultrasound energy. the left and die 8 on the right. significant, ongoing innova- each echo to its proper The user interacts with the SonoSimulator was tion, evaluated on patent interface within stacked die, SonoSimulator to perform originally designed to help metrics including the num- Sonoscan® has developed simulated imaging of the obtain C-SAM images for ber of successful patent over the last several years, virtual die stack at the levels stacked die, but other thin, filings, the global reach of in collaboration with T.U. of interest by adjusting gates multi-layer sample analysis the inventions and impact Dresden, a software program (precise depths from which can be done, too. In any on the industry. called SonoSimulator™ that echoes are used to make an sample with multiple, closely www.lsi.com creates a virtual model of the image; one gate is green in spaced interfaces the ultra- echo returns of the die stack. Figure 1) within the simu- sound echoes may be hard  DISCO CORP. The user of the program lated A-Scan. When the user to distinguish or separate for to Strengthen enters data about the dimen- is satisfied with an image of each interface, and/or may its Secondhand sions and materials of the the defect at a specific level, interfere with each other. Equipment stack and then the software they now know the precise With this integrated software, Business creates the virtual model for position and width of that a model of the sample can DISCO Corporation simulation of the A-Scan. gate. The imaging (gating) be built to simulate the echo has announced plans to To simulate defects for recipe is then transferred to patterns with known defects strengthen and develop its imaging, the operator uses a Sonoscan Gen6™ C-SAM at each layer of interest. the SonoSimulator software (C-Mode Scanning Acoustic Using a reference waveform, secondhand equipment to insert virtual defects at Microscope) system to scan a model of the A-Scan is business, which involves interfaces of interest. The and image a real die stack generated, which can be buying back and refurbish- virtual defects simulate air sample. In a production envi- captured and compared for ing used DISCO equip- gaps (example from Sono- ronment, a test die stack will each layer of interest. Trans- ment. There is growing Simulator in Figure 1) so that likely have a “known defect” ducer frequency, focus level demand for secondhand the interface between virtual planted between two die to and gate positions can then equipment in order to die 5 and 6, for example, can help identify a specific level. be established, tested and reduce the financial burden be identified by its position When the “known defect”, refined prior to transferring of capital investment to from left to right, position #5 which is an intentional reflec- the imaging recipe settings to improve production capa- in this case. The oscilloscope tive gap, is in focus any other the Gen6 for all future parts bilities and for early waveform at the top of Fig- unintended gap-type defects of the same construction.  ure 1 (known as the A-Scan) or features at that interface for more information is so realistic that the virtual will also be in focus. visit www.sonoscan.com. ◆ 8 MEPTEC REPORT WINTER 2012 meptec.org MEMBER NEWS

Every Second Car Produced Today Contains start-up of production Infineon lines, as well as for ma- chine purchases in emerg- The Company Has Just Delivered its 100 Millionth TriCore™ Microcontroller ing countries, small- and medium-sized factories, Infineon Technologies tion and in tire pressure universities, and R&D labo- AG has just delivered its control, in electric power ratories. The secondhand one hundred millionth Tri- windows, lighting control, in semiconductor manufactur- ™ Core microcontroller. That heating, ventilating and air- ing equipment market is ranks these microcontrollers conditioning systems, in seat worth an estimated US$6 among the most successful adjustment and keyless door billion (according to a 2010 in automotive electronics. opening. The TriCore-based micro- In 2011, around 75 mil- SEMI study) and continues controllers from Infineon are lion vehicles were manufac- to grow at a constant rate. assembled in over fifty auto- microcontroller architecture tured, of which 20 million Sales are especially strong motive brands. Statistically optimized for embedded real- were produced in Europe for non-semiconductor speaking, this means that time systems. It unifies real- alone. On average, each manufacturer third-party almost every second vehicle time capabilities, signal-pro- vehicle contains chips worth end-users, however many produced today includes a cessing functions and highly about USD 300. Infineon are reluctant to proceed TriCore-based microcon- efficient application-specific has a ten percent share of due to the disadvantages troller. It is responsible for interface functions. The core this market - and is thus one of unsupported mainte- keeping the fuel consumption has a super- of the world’s largest chip nance and parts. DISCO and exhaust emissions as low and is thus able to carry out manufacturers for automo- aims to achieve a sales as possible. a number of different com- tive electronics; what is TriCore-based microcon- mands simultaneously. The more, the company is also target of 500 million yen trollers are used in the central command set includes special the largest chip manufacturer within the first year and 2 control units for combustion mathematical functions for in Europe (with 15 percent billion yen in three years. engines and gearboxes to the efficient calculation of of the market). In 2011, the www.disco.co.jp control the injection, ignition complex algorithms. TriCore total value of the market for or exhaust gas recirculation: microcontrollers are ideal automotive chips amounted  MST opens Increasingly, they are also for automotive applications to approximately USD 23 sales office in being used in hybrid and by virtue of their high data billion (source: Strategy Ana- Singapore electric vehicle drives. Other rate and real-time capability, lytics, April 2011 – a market The Micro Systems Tech- areas of application include namely in the temperature research company). For its nologies Group (MST) has electric steering, braking range from -40 °C - 170 °C. microcontrollers in engine just opened a sales office and chassis control as well Besides the management management and transmis- in Singapore in September as body control. TriCore is and transmission control sion control units, Infineon of this year. With this new also used in other areas not systems, Infineon chips are holds a global market share branch office, existing cus- related to the automotive sec- used in airbags, driver assis- of over 30 percent. tor, for example in system tance systems, in electronic further information about tomers in the Asia/Pacific controls, solar inverters and steering support, in ABS, Infineon microcontrollers is region will be better served, for steering electric motors. Electronic Stability Programs available at www.infineon. and it will also be possible TriCore is a 32-bit (ESP), pedestrian protec- com/tricore. ◆ to meet the increasing demand in this region for innovative solutions from Altera Ships Its First SoC Devices the MST Group. www.mst.com dual-core ARM® Cortex™ A9 altera is the only FPGA processor system with FPGA vendor today shipping SoCs Signetics logic on a single device. Altera that offer 32-bit error correc-  Announces Plan SoCs include several distinctive tion code (ECC) support which to Double Their features that enable developers helps ensure data integrity Flip Chip Package in the wireless communica- throughout the embedded sys- Assembly Capacity tions, industrial, video surveil- tem. Other unique features Signetics Corporation lance, automotive and medical in the device family include equipment markets to create a high-bandwidth memory has announced that it has custom SoC variants optimized controller with built-in mem- approved capex plans for system power, board space, ory protection, flexible boot and has ordered equip- Altera Corporation performance and cost require- capability and integrated PCI ment that will double their has announced the first ments. The first devices Altera Express® (PCIe®) across all SoC capacity for Flip Chip shipments of its 28 nm SoC is shipping are low-power, low- devices. ◆  devices, which combine a cost Cyclone® V SoCs. meptec.org WINTER 2012 MEPTEC REPORT 9 MEMBER NEWS

Package Assembly at STATS ChipPAC Announces Expansion Plans in South Korea their factory in Paju, South Korea. The new Flip Chip STATS ChipPAC Ltd. has announced ing capabilities that extend back over 27 years to plans to expand its semiconductor assembly and when the factory was first established. We are very expansion will be qualified test operation in South Korea. The Company has confident that our expansion in South Korea will by January 2013 and will signed a non-binding memorandum of understand- increase our overall competitiveness in advanced be ready for volume pro- ing to invest in a new integrated facility in the flip chip, advanced wirebonding and three dimen- duction in February 2013. Incheon Free Economic Zone, an international sional (3D) packaging technologies where we The centerpiece of this new business district located in the Incheon metropoli- have established a strong leadership position in the equipment is the Quantum tan area that is adjacent to Seoul, South Korea. industry,” said Tan Lay Koon, President and CEO, 8800 Flip Chip bonder The integrated facility will include approxi- STATS ChipPAC. by Datacon. This bonder mately 95,000 square meters (1 million square STATS ChipPAC Korea’s sizeable flip chip allows for finer bump pitch- feet) of land with options for future expansion. The technology portfolio ranges from large single die es below 100µm and is integrated facility will be used for manufacturing, fcBGA packages with passive components used compatible with the 95mm research and development, and administration. for graphics, CPU and ASIC devices to smaller Construction is scheduled to begin in the third fcFBGA packages including single die, multi-die PCB format. quarter of 2013 and the new facility is expected to and stacked configurations that combine wire bond www.signetics.com be operational in the second half of 2015. STATS and flip chip technology within a single pack- ChipPAC intends to integrate its existing facili- age. In terms of 3D technology, STATS ChipPAC  DigitalOptics ties in South Korea into the new, larger facility to Korea provides advanced Package-on-Package to Focus on Core achieve a more efficient, cost effective manufactur- (PoP), Package-in-Package (PiP) and System-in- MEMS Camera ing flow and provide flexibility for future expan- Package (SiP) technologies that integrate one or Module Business sion. more integrated circuits or passives into a single Tessera Technologies, “STATS ChipPAC Korea is an important stra- solution for mobile, digital consumer and data stor- Inc. has announced that its tegic manufacturing operation with an illustrious age applications. wholly owned subsidiary, history of delivering the most advanced packaging further information is available at www. ◆ DigitalOptics Corporation and test technologies with proven manufactur- statschippac.com. will focus its efforts on its core MEMS camera module business, which targets the Altera and ARM Announce Industry’s First large and growing mobile FPGA-Adaptive Embedded Software Toolkit phone market. DOC plans ability to adapt to the logic within the SoC to seamlessly to reduce its workforce – contained in the FPGA, the extend embedded debugging not including those related new toolkit provides embed- capabilities across the CPU- to manufacturing opera- ded software developers an FPGA boundary and unify all tions in Zhuhai, China — by unprecedented level of full- software debugging informa- up to 40%. These actions chip visibility and control tion from the CPU and FPGA could result in annualized through the standard DS-5 domains with the standard operating expense savings user interface. The new DS-5 user interface. When of between $15 million and toolkit will be included in combined with the advanced $18 million by the second the Altera SoC Embedded multi-core debugging capa- quarter of 2013. As part Design Suite and will begin bility of the DS-5 Debugger, ® of this process DOC plans Altera Corporation shipping in early 2013. and the link to the Quartus and ARM have announced altera SoC devices com- II software SignalTap logic to cease operations at its that, with a unique agree- bine a dual-core ARM Cor- analyzer forcross-triggering facility in Tel Aviv, Israel ment, the companies have tex-A9 processor with FPGA capability, the toolkit deliv- and to pursue a possible jointly developed a DS-5 logic on a single device, giv- ers an unprecedented level of sale of, or other strategic embedded software develop- ing users the power and flex- debugging visibility and con- alternatives for, its facility ment toolkit with FPGA- ibility to create custom field- trol that leads to substantial in Charlotte, NC. These adaptive debug capabilities programmable SoC variants productivity gains. two facilities are not cen- for Altera SoC devices. The by implementing user-defined More information about ® tral to the MEMS camera ARM Development Studio 5 peripherals and hardware the Altera SoC EDS can be ™ module opportunity. Given (DS-5 ) Altera Edition tool- accelerators in the FPGA found at www.altera.com/ full effect, the planned kit is designed to remove the fabric. Altera is currently soc-eds. More information actions would reduce the debugging barrier between shipping initial samples of its about the ARM DS-5 Altera the integrated dual-core CPU Cyclone® V SoC devices. Edition toolkit can be found non-Zhuhai workforce of subsystem and FPGA fabric The ARM Development at www.altera.com/ds-5-ae. 450 by approximately 180 in Altera SoC devices. By Studio 5 (DS-5) Altera Edi- The Altera SoC EDS will employees. combining the most advanced tion toolkit dynamically start shipping in early 2013.◆ www.doc.com ◆ multi-core debugger for the adapts to unique customer ARM architecture with the configurations of the FPGA 10 MEPTEC REPORT WINTER 2012 meptec.org COLUMN

to be, varying size eruptions of very hot be used to protect microelectronics such INDUSTRY electrified gasses from the surface of the as faraday cages; however, their weakness sun called solar flares or coronal mass is that even cages must have “openings” INSIGHTS ejections. Currently, the timing and size where power and signals enter and exit, By Ron Jones of these events are unpredictable. Photons thus providing EMP entry points. Solar (light) from such an event reach earth after EMP does not present as big a risk to IC’s roughly 8 minutes and are harmless. A as does nuclear EMP. proton storm related to the eruption takes 1 as bad as the loss of power distribu- EMP and Us to 3 days to travel to earth. The scope is so tion and electronics sounds, it is only the massive that there is interaction with the very beginning of the real human disaster.  In my last column I looked magnetic fields of the earth, thus impact- The average city has about 3 days of food. at the myriad life changing devices and ing the entire surface, not just line of sight Without electricity, all the factories that technologies that the semiconductor indus- regions. The US has satellites deployed process food will no longer operate. The try has enabled through speed increases, between the earth and sun that can detect systems that purify and deliver most of the size reductions and power efficiencies. the magnitude of this proton barrage and drinking water will no longer work. The It is hard to image a negative side to relay the info to earth almost immediately. refineries that convert crude oil into gaso- these accomplishments, however, we will This potentially allows some time for line shut down. Most trucks and vehicles explore one here. The potential negative planes to be safely grounded, the grid to will not operate. People in populated areas effects apply not only to our industry, but be shut down in an orderly fashion and (possibly around the world) would rapidly also to us as inhabitants of this planet. other actions to be taken to minimize dam- run out of water and food and humans an Electro-Magnetic Pulse (EMP) is age. The largest recorded eruption event would begin to perish from thirst and star- a sudden burst of electromagnetic energy occurred in the summer of 1859. Electric- vation within a short period of time. which can be very damaging to almost ity was still in its infancy, yet telegraph Imagine the 600,000 inhabitants of Las everything that is electrical. In order to wires shorted and created a number of fires Vegas trying to find water and food in the provide a framework for this column, I and other electrical devices malfunctioned. middle of the desert that surrounds them. will separate the EMP sources into man- The Aurora Borealis was seen as far south Imagine 19 million Metro NY residents, made and naturally occurring. To further as Cuba and Hawaii. Similar to earth- packed into an area of 80x80 miles, trying structure in another dimension, I will break quakes, these will continue and inevitably to obtain food and water with no electric- the impacts into those to electrical power a “big one” is somewhere down the road. ity and no transportation. Rural areas are distribution systems and those to electronic one of the major risks from EMP is to only slightly better off as they will be circuits. Though these may seem arbitrary, electrical distribution systems such as the impacted by power loss and urban dwell- you’ll understand the logic as you read on. US Grid. The thousands of miles of high ers may come and strain what resources one potential source of an EMP is a voltage power lines act as huge antennas they have. man-made device such as nuclear bomb. for EMP radiation. Massive currents are a small country like Iraq or a well- The impact was known as early as US induced into the lines and flow toward funded terrorist group could essentially nuclear testing in 1945, with the first real both generators and transformers. When level the playing field with a strategically understanding of the impact from the the current arrives at the end of the line, placed SINGLE device attack against the Starfish Prime high altitude detonation it has no place to go and explodes the US. The effect of 9/11 could be multiplied over the Pacific in July 1962. Man-made attached generator or transformer. Some 10,000 fold. devices detonated in the atmosphere tend scientists estimate that a large burst from a This is a threat in which the world or to have line-of-site impact. Scientists man-made or natural source could destroy a significant part of it could be changed predict that a one megaton nuclear device the entire grid. It might take 10 years to in an instant and not be able to recover detonated at an elevation of 300 miles build back the distribution network since before there was massive loss of life. To over the center of the US, would impact with no power, it is difficult to manufac- think that, because it has never happened, the entire continental US. There are many ture anything, including generators and it never will is extremely naive. Had the devices of this size in existence around the transformers. 1859 solar storm occurred in 2012, all world. It would take a much smaller yield The second major risk is to any device indications are that there would have been device detonated at a lower altitude to dis- or system that contains microcircuits. major impacts to the world’s people. able a US metropolitan area, such as New Today’s high tech microelectronics runs our success in miniaturizing the York, or the State of Israel. People on the on supply voltages of less than 2 volts and world’s electronics has potentially pro- ground would not be directly harmed and are sensitive to ESD voltages in the range vided a way for all the progress we’ve might not even realize that the detonation of 50 volts or less. Gamma rays from an enabled to be undone. Surely there are took place. With such a short distance to EMP pulse can generate millions of volts. ways that our industry can help provide earth, the high energy burst would arrive A typical IC has dozens to hundreds of solutions to some of these problems. There immediately, delivering millions of volts antennas protruding from the package are also things we can do to help protect of energy in a short, high energy burst (leads) that can deliver energy from the our families. lasting a nanosecond. There would be no pulse directly to the chip. The device We need to pitch in and do our part for warning other than detection of the war- doesn’t stand a chance and is immediately our families, our country and mankind. head delivery vehicle. fried. Many groups are seeking ways to Much of the information for this article The second EMP source that has been harden manufacturing, control and com- came from the National Geographic DVD, around since time immemorial is our own munication systems that are based on Electronic Armageddon, and from various sun. There have been, and will continue sensitive chips. There are things that can Wikipedia entries. ◆ meptec.org WINTER 2012 MEPTEC REPORT 11 COLUMN

My father in-law’s rarely used six- Coupling & year-old DVD player died mid-movie, Crosstalk disappointing everyone. A Google search identified a (C318 in the power By Ira Feldman supply subsystem) as the most likely culprit. With new DVD players costing less than $50, I wasn’t too interested in Electronic coupling is the confirming root cause failure. However, transfer of energy from one circuit or I did have to disassemble the player to medium to another. Sometimes it is inten- retrieve the disc stuck inside. Clearly a tional and sometimes not (crosstalk). I system design failure since the unit did hope that this column, by mixing technol- not fail in a safe or convenient mode. ogy and general observations, is thought Upon opening the unit, it was clear that provoking and “couples” with your C318 was indeed blown. thinking. Most of the time I will stick My very small, and likely statistically to technology but occasional crosstalk insignificant, sample of failed devices diversions like this one may deliver a appeared to indicate a trend. Do capaci- message closer to home! tors have a higher failure rate than other more complex electronic parts? Capaci- Quality for the tors, if the circuit is designed and manufactured correctly, should have Long Haul? an extremely low failure rate. Some models predict the life of a capacitor  Does a manufacturer’s re- increases by the square of the difference sponsibility and interest in quality end of the maximum rated temperature minus when the warranty expires? operating temperature. By selecting When is death premature? People with a higher temperature rat- have life expectations based upon fam- ing, this can easily increase the expected ily and societal statistics as well as their life. Regardless of operating a capacitor health. Mechanical devices, especially well below its maximum specification to those with moving parts, have estimated extend its life, many formulas limit the lives and known wear out mechanisms. useful life of an electrolytic capacitor to Cars currently have an average age of 11 15 years due to material aging. If more to 13 years of useful life which allows of our electronics lasted 10 to 15 years, I consumers to set reasonable expectations doubt anyone would say they failed pre- of service life. What about electronics? maturely since their functionality would What is a reasonable expectation of likely be obsolete by that time. SMT, COB, COF, IC ASSEMBLY service life? Why the premature failure of capaci-

SAME DAY, 1 - 5 DAYS TURN I had a few devices at home fail tors in these products? Did you know recently which makes me wonder about there is a global epidemic of capacitors AmTECH is a leading the reliability of consumer electronics. failures that started in 1999 named the Silicon Valley provider for SMT, COB, COF and Have quality standards fallen and have “Capacitor Plague”? (Go ahead, Google IC Assembly. we reached the point of truly dispos- it – I’ll wait.) This has lead to a rash of Gold ball, aluminum able electronics? class action lawsuits with major electron- and gold wedge wire ics manufacturers going on the defensive. bonding, Automated Optical Inspection The Weakest Link? Some trace these failures to improperly (AOI) and XRAY. a four-year-old LCD manufactured capacitors from Taiwan- monitor intermittently failed to turn on. ese suppliers that undercut the price of — SMT ASSEMBLY, Lead-Free, 0201, uBGA, CSP A quick Internet search found several previously dominant Japanese suppliers. — COB, COF, IC ASSEMBLY, others with this same monitor who also As interesting as the claims of industrial Cleanroom ISO 7 (Class 10,000), had the exact issue. (Google is a fantastic espionage and theft of technology with Aluminum and Gold wire diagnostic tool: query the make, model the resulting lawsuits are, I doubt they — NPI - PROTOTYPE, 8, 24 to 72 hours turn number, and a description of the symp- will be the basis of the next John Grish- — Low to Medium Volume PRODUCTION, tom and you are likely to find others vic- am novel. MRP, IPC-A-610 Class 2 and 3, tims of the same issue plus often a solu- MIL-STD-883 tion.) People reported fixing the problem Quality Failure? Your NPI Manufacturing Solution! by replacing faulty surface mount chip Though these particular failures may Phone (408) 227-8885 capacitors on the . Since the have a root cause of improper compo- Email: [email protected] monitor was no longer under warranty, nent design and manufacture, I believe the cost to have someone diagnose let the Capacitor Plague is indicative of www.amtechmicro.com alone repair this problem far exceeded fundamental failures in product qual- the cost of replacing it. ity as a result of the dis-integration of 12 MEPTEC REPORT WINTER 2012 meptec.org the global supply chain. Even worse two years) required for the promotional Advanced are some brands whose sole involve- price? Most wireless carriers aggres- ment in the product is the receipt of a sively market an extended warranty plan Component royalty check. I’ve had several cordless instead of working to increase the hard- Labs, Inc. telephones branded “AT&T” and “RCA” ware warranty. that were designed and manufactured by capital equipment companies, includ- third parties with little to no involvement ing commercial computing and net- from these formerly pioneering electron- working companies, do track their field ics companies. In fact, “RCA” is simply failures since much of their equipment a trademark licensed by RCA Trademark is on a support contract after the initial Management to others who actually build warranty period. These failures directly and sell electronic products. impact the equipment company’s bottom for some companies, the only qual- line, so they keep careful track both to ity concern appears to be whether they improve new designs and to set sup- “Time Critical” can get through the ever-shrinking war- port pricing for older equipment. Rather Organic Substrates ranty period without a rash of expen- direct feedback on quality is received sive returns. Formerly, most vertically when a prospective customer calculates BGA, CSP, Flip Chip, High Frequency, integrated companies did an analysis total cost of ownership including quoted High Speed, Rigid, Cavity and between engineering, manufacturing, support costs. Flex Packages and quality organizations to determine consumer brands, excluding perhaps - 20µm Lines and Spaces - the required quality and reliability lev- products such as cars with long warran- ACL is the only els. The objective in setting these levels ties and service plans paid for by the North American company was achieving a field failure rate below manufacturer, have much smaller direct focusing exclusively a given limit that supported the prod- incentives to manage their post warranty on the fabrication of uct’s financial (warranty) objectives. failure rates. Marketing should join the High Density Interconnects. These levels translated into reliability conversation with engineering, manu- goals, test and qualification plans, and facturing, and quality to set appropriate ITAR Registered vendor management plans for each quality goals. Yes, the product might Phone: 408.327.0200 Email: [email protected] component in the system. With the survive the warranty period but if it increased use of outsourced manufactur- dies prematurely, before the customer www.aclusa.com ing, fragmented supply chains, and high- is ready to move on, the brand will er levels of sub-system integration, accu- become synonymous with junk. rate quality level planning has become let us continue the discussion on my exceedingly difficult if not impossible to blog http://hightechbizdev.com. I wel- ICIC Assembly Assembly achieve. come your comments! ◆

Extended warranty plans have AdvancedAdvanced PackagingPackaging become profit centers for consumer products. Only a few plans are offered IRA FELDMAN (ira@feldmanen- gineering.com) is the Principal by manufacturers themselves, so there is Consultant of Feldman Engineering little incentive to improve product qual- Corp. which guides high technol- ity. Most plans are sold by retailers at ogy products and services from a substantial profit and underwritten by concept to commercialization. He insurance companies. Therefore, there is follows many “small technologies” little pressure for retailers to push manu- from semiconductors to MEMS to facturers for longer warranties. Doesn’t nanotechnology engaging on a wide it seem odd that most smartphones come range of projects including product with a hardware warranty (typically one QFN’s, QFN’s,Leaded LeadedPackages, Packages Modules, SiP’s generation, marketing, and business 2, 2.5 & 3DModules, Advanced SiP’s Packaging year) less than the length of the wire- development. less carrier contract obligation (typically Quick2, 2.5 Turns, & 3D Development, Advanced NPI, Packaging Production ISO 13485:2003 Medical Certified ITAR Registered IPC-A-610Quick Class 3Turns, Assembly Development, Class 100 Clean Room Upcoming 2013 MEPTEC Events NPI, Production n WEDNESDAY, FEBRUARY 13 n TUESDAY, APRIL 9 ISO 13485:2003 Medical Certified ITAR Registered MEPTEC Luncheon IMS 2013 IPC-A-610 Class 3 Assembly Class 100 Clean Room Biltmore Hotel & Suites, Santa Clara, CA Intelligent Medical Systems Conference The University of Texas at Dallas Silicon Valley’s Packaging Foundry n MONDAY, MARCH 18 In Association with MEPTEC www.promex-ind.com SEMI-THERM Executive Briefing: Thermal n Management Market Visions & Strategies WEDNESDAY, MAY 22 In Association with MEPTEC and 11th Annual Silicon Valley’s Packaging Foundry Electronics Cooling Magazine MEPTEC MEMS Technology Symposium DoubleTree Hotel, San Jose, CA Holiday Inn, San Jose, CA www.promex-ind.com meptec.org WINTER 2012 MEPTEC REPORT 13 ANALYSIS

Packaging Materials Outlook

Dan Tracy, Senior Director Industry Research & Statistics, SEMI $50.74 $47.86 $48.59 $50 $44.84 $42.67 $42.52

$40 For a number of years now, $37.25 the semiconductor industry has been $35.26 $30.94 described as being in an “Age of Materi- $28.81 als” as new elements, compounds, and $30 molecules have been integrated into both device structures and packaging tech- $20 nology. The latter has seen significant US $ B illions changes in material sets as lead-free and halogen-free requirements have required $10 new formulations and chemistries to meet new demands in semiconductor packaging. In addition, new and increas- $0 ingly complex packaging form factors 2004 2005 2006 2007 2008 2009 2010 2011 2012F 2013F require materials that deliver enhance Packaging 11.95 12.77 15.54 17.59 18.32 17.51 21.8 23.67 24.24 25.02 device performance and improve reli- fab 16.86 18.17 21.7 25.08 24.19 17.75 23.05 24.19 24.35 25.72 ability at both the package-level and Totals may not add due to rounding. board-level. Advancements in materials technology will continue as 3D packag- Figure 1. ing through silicon-via (TSV) technolo- Other Silicon gies ramp as key focus areas over the Packaging Wafers next several years and beyond. Materials from 2004 through 2011, the pack- aging materials market has grown at a compound annual growth rate of over 21% 20% 10 percent, which is a reflection of the material changes in packaging. The packaging materials market is expected to surpass $24 billion in 2012 and grow to $25 billion in 2013. When compared 21% 30% to wafer fab materials sold into the semi- conductor market, the share of packaging 8% materials has increased over this time- frame: from 41% in 2004 to almost 50% share forecasted for 2012. Preliminary estimates show total packaging revenues approaching $26 billion by 2014. (See Plastic Figure 1.) Substrate Other Fab The growth in the share of packag- Leadframe Materials ing materials consumed by the semi- conductor industry parallels the ramp Figure 2. Estimated 2012 Market Breakdown by Materials Segment. Source: SEMI and TechSearch in laminate substrate based packaging. Beginning in the late 1990s and into the substrates consumed in these technolo- market is forecasted to grow to $11.1 2000s, new package types based on lam- gies, the share of packaging materials billion in 2013 and up to $11.6 billion in inate (plastic) substrate technology were consumption has increased. 2014. (See Figure 2.) introduced into the market. Ball grid In terms of total material revenues, With 3D packaging and TSV, oppor- array (BGA) and flip chip packaging laminate substrates now represent a tunities will grow for materials solu- were the early volume drivers, though market larger than that reported for sili- tions to packaging technologies that are this technology was further developed con wafers. Total revenues for laminate increasing front-end/fab oriented such as for usage in chip-scale, stacked-die, and substrates are expect to reach $10.4 bil- wafer bumping redistribution and via for- package-on-package technologies. As a lion in 2012 compared to $9.7 billion for mation and filling. Solutions will require result of the new materials and advanced silicon wafers. The laminate substrate newer materials and processes such as 14 MEPTEC REPORT WINTER 2012 meptec.org temporary bonding materials, new gen- material supplier base. Consolidation eration of underfill and encapsulants, is occurring at some levels. Leadframe dielectrics, and chemical mechanical plants have closed in recent years, espe- Open Cavity planarization (CMP) slurries. While not cially following the flood in Thailand new to the semiconductor industry, CMP in 2011. Hitachi Chemical has acquired QFN is new to packaging. For TSV related Nitto Denko’s mold compound busi- processing, slurry suppliers can leverage ness, while Sumitomo Metal Mining and their existing know-how developed for Hitachi Cable recently announced an copper interconnects, though control of agreement to integrate their leadframe dishing in the larger TSV feature sizes businesses. In addition, earlier this year and the higher copper removal rate are a Sumitomo Metal Mining announced its new challenges to be addressed. exit from the bonding wire market. any new material must be compat- counter to some of the consolidation, ible with high-volume manufacturing of material suppliers in Korea and China Your Die high yielding and high reliability pack- seek a more prominent position in the Here ages. Material suppliers need to address market. Korean companies are focusing trade-offs when optimizing material on providing solutions to address oppor- chemistries and formulations regarding tunities in the advanced and 3D packag- Fabless • MEMS • RF • Sensors stress performance, moisture absorption, ing segment of the market. Some domes- adhesion strength, cure temperature, tic suppliers in China are boosting their and other properties. While the industry capacity and technological capabilities to recognizes that thermal and stress man- serve the growing package & assembly agement are key in integrating packaging operations located there. material solutions, it is expected that Though market challenges exist for volume ramp of 3D configurations will suppliers, new material solutions will be expose new mechanical and thermal needed to deliver increasingly complex issues. and integrated packaging technologies (866) 404-8800 as new opportunities emerge in that will benefit the end consumer in an supplying materials, there are changes ever more mobile and interconnected ◆ underway throughout the packaging world. www.MirrorSemi.com

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For more information visit our website (503) 625.2821 | treske.com or call 408-516-4611 ISO9001:2008 | AS9100C (April 2013) | ITAR www.namics.co.jp meptec.org WINTER 2012 MEPTEC REPORT 15 SYMPOSIUM

SEMI-THERM® EXECUTIVE BRIEFING: Thermal Management Market Visions & Strategies

Monday, March 18, 2013 DoubleTree Hotel, San Jose, CA, USA

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In Association with MEPTEC & Electronics Cooling Magazine

REGISTER ONLINE TODAY AT WWW.MEPTEC.ORG

Media Sponsors SEMI-THERM

SEMI-THERM® EXECUTIVE BRIEFING: Thermal Management Market Visions & Strategies

In Association with MEPTEC & Electronics Cooling Magazine The Executive Briefing will be  co-located with the 29th annual SEMI-THERM conference and Monday, March 18, 2013 • DoubleTree Hotel, San Jose, CA, USA exposition. SEMI-THERM 29 program According to multiple market highlights include: analyst firms, the world mar- EVENING TUTORIAL ket for thermal management 7:30-9:00 pm products will grow from Tuesday, March 19 nearly $8 billion in 2011 to Microfluidic Thermal Management and Thermal- over $10 billion by 2015-16. Electronic Co-Design for Factors driving such growth Chip Stacks include LED lighting, porta- Dr. Avram Bar-Cohen, Distin- guished University Professor and bles and the infrastructure to Dr. Ankur Srivastava, Associate support them – smart phones, Professor, University of Maryland tablets, cellular and wifi, data Three-dimensional chip stack- ing is poised to become the next centers, etc. packaging paradigm in the elec- With such encouraging tronic industry. While this para- digm can provide significant numbers projected for ther- improvements in device density, mal management technolo- interconnect delays, and system The DoubleTree Hotel is located at 2050 Gateway Place in San Jose, integration, it can be expected gies, it is imperative that CA and is adjacent to San Jose International Airport. to lead to higher heat densities information on thermal man- and decreased access to chip hot spots and surfaces. Intrachip and agement visions & strategies Valley, SEMI-THERM is Opportunities for Exhibiting interchip microfluidic cooling, with be made available to engi- and Sponsorship low boiling-point, inert, dielec- perfectly poised to offer this tric liquids, is a most promising neering leaders, management new information stream to There are several oppor- thermal management technique and executive branches of for this packaging paradigm, but the industry. ◆ tunities to promote your aggressive thermal-electronic co- industry. Where in the market company at the SEMI- design is needed to achieve im- are the opportunities, direc- proved performance and energy Symposium Committee THERM Executive Briefing. efficiency. This tutorial will present tions and challenges over A Sponsorship will provide a brief review of the emerging 3D Martin Goetz the next few years? SEMI- many benefits, including form factors, application of micro- Design Manager fluidic cooling, a co-design, heu- THERM hopes to answer ristic, and a case study exploring Northrop Grumman extensive marketing exposure that question and provide the benefits of co-optimization of Corporation through partnerships with micro-channel allocation and ther- some market and technology mal TSV planning on chip stack George A. Meyer IV other industry organizations insight in a new event Ther- performance. CEO and publications. Options mal Management Market Celsia Technologies to exhibit include just the EMBEDDED TUTORIAL Visions & Strategies. SEMI- 8:00-9:00 am Bhavesh Muni Executive Briefing, or a spe- Wednesday, March 20 THERM has been very Global Marketing Manager cial discounted price to have Multi-Die Integration – successful at disseminating Dow Electronic Materials an exhibit table at the Execu- Drivers and Challenges information at the engineer- Ivor Barber Thomas Tarter tive Briefing and a booth at ing level, but it strongly feels Director Package Technology President SEMI-THERM 29. Please Xilinx that the market issues, new Package Science Services LLC visit the event page at www. Across the industry, packaging products and technology meptec.org for details. ◆ engineers are facing new chal- and advances in the state-of- lenges associated with Multi Die packaging. Multi Die packaging the-art must be propagated can be in the form of stacked die, to keep industry leaders Who Should Attend: package on package (PoP), 2.5D and 3D TSV or a combination of informed and motivated to n Technology and Technical Leaders some or all of these approaches. fund research and develop- n Engineering Managers These emerging package formats and their associated thermal and ment for thermal manage- n Product Line Managers mechanical challenges will be re- ment of all products. With n NPI/Product Development Managers viewed in this tutorial. nearly 30 years of direct n Business Managers For complete program details industry involvement and its n Strategic Level VPs please visit www.semi-therm.org long-time location in Silicon n C-Level Executives who manage internal R&D spending meptec.org WINTER 2012 MEPTEC REPORT 17 FOLLOW-UP

Multi-Die Integration Provides Multifaceted Solutions

Francoise von Trapp 3D InCites

manufacturer of high-performance mem- This year’s Roadmaps for Multi-Die MEPTEC PRESENTS ory, seconded the motion on the critical Integration Symposium, hosted by need for proven reliability. Chapman’s MEPTEC on November 14, 2012 at interest is in non-commodity memory in the Biltmore Hotel in Santa Clara, Roadmaps networking, because the tasks required of CA, offered some interesting and dif- for Multi Die Integration networking require more bandwidth. “All ferent perspectives than the garden- Strategies and Drivers the techniques used to make commod- variety 2.5D and 3D IC conferences Participating Companies: ity memory higher bandwidth just don’t of late. While there were a number n Altera Corporation n LSI Corporation n ASE (U.S.) Inc. n Maxim Integrated work in the networking world.” he ex- of process-focused presentations, n Cadence Design Systems Inc. n Electro-Mechanics Co., Ltd. n GSI Technology n Signetics Corporation plained. As much as we think reliability what I found most interesting were n Huawei Technologies n STATS ChipPAC n Kyocera America, Inc. n TechSearch International, Inc. in our smartphones is critical, Chapman those that stuck to the symposium n Unimicron Technology Corp. n Universal Scientific Industries, Co., Inc. pointed out that in reality, smartphones sub-topic of strategies and drivers, Diamond Sponsor Gold Sponsor Silver Sponsor Association Sponsor are consumable products. Reliable serv- and looked beyond the silicon to ad- ers are much more crucial, as that’s the dress these technologies from the place where all our smartphone data is module and system perspective. NOVEMBER 14, 2012 • SANTA CLARA, CALIFORNIA stored. He even smashed his phone to Media Sponsors smithereens right in front of us for added emphasis. But no worries, as soon as he Own the Profit, Own the Problem picks up a replacement (assuming he one ongoing debate that seems to end-to-end approach won’t co-exist right purchased the insurance) his backed-up have everyone talking in circles is the alongside the collaborative models being data will be restored. Device reliability, combined discussion of supply chain promoted by the other fabless, foundries, he explained, is especially critical for business model and who owns the liabil- OSATS, IDMS and OEMS. the high bandwidth memory (HBM) and ity of the device. Harrison Chang, Ph.D, networking applications that GSI targets, VP of Universal Scientific Industries, Reliability is an Issue Not to Be Ignored and at this point 3D ICs aren’t reliable the module manufacturing division of Many have predicted that high-end enough to take that risk. ASE Group, offered a fairly elegant and servers in data storage centers will be the 2.5D interposer is one solution, noted simple solution, which he illustrated by killer app for Wide I/O DRAM on Mem- Chapman, but there’s a limitation with showing iPhone teardown examples. ory 3D ICs (think hybrid memory cube) the reticle area because silicon substrates “Who owns the multi-die integration?” because the cost isn’t as big an issue as limit the maximum RAM compliment. he asked. “The die vendors? The module it is with consumer products when you “Organic interposers will be an interest- maker? The device owner? What about consider the performance improvements. ing option once they have been fully the gross margin? Whose trademark This, we’ve been told, is how we will developed and are available,” concluded will be stamped on the module?” Quite solve the bandwidth issue. But the hard Chapman. simply, whoever stands to gain the gross truth is that until reliability is proven, margin of the device owns the liability. 3D ICs are unlikely to be the solution for Organically Grown Solutions This, explained Chang, allows for any server applications. chapman’s announcement must have business model to be used. Ultimately, Jan Vardaman talked about this in her been music to the ears of all the organic the decision lies with the customer. (Rich presentation, Alternatives on the Road to substrate manufacturers in the room. Rice drove this point home further during 3D TSV. Still on her 3D IC “to do” list is There were several companies repre- his talk at the Known Good Die Sympo- a thermal design tool, proven reliability sented offering solutions in the session, sium, which MEPTEC co-located with with the data to support it, and a sorted- Emerging Technologies for Multi-die Multi-Die on November 15.) If your logo out business infrastructure, which, in her Packaging, including Unimicron Tech- is on top of the package, than you procure words “has as much drama as a teenage nology Corp, Kyocera America, and the components and own it through the girls sleepover.” (Now there’s something Samsung Electro-Mechanics. supply chain. With this as the ultimate I can identify with!) guideline, there’s no reason that TSMC’s David Chapman of GSI Technology, continued on page 22  18 MEPTEC REPORT WINTER 2012 meptec.org FOLLOW-UP

MEPTEC PRESENTS Known “Known Good Die” Good die KGD 2012 Has a New Name 20Reducing12 Costs Through Yield Optimization

diamond Sponsor Gold Sponsor Silver Sponsor Association Sponsor Francoise von Trapp 3D InCites NOVEMBER 15, 2012 • SANTA CLARA, CALIFORNIA

Media Sponsors

chain to handle. “One of the most suc- memory and get twice the number of After 20 years of chasing elusive cessful solutions is to avoid it altogether.” memory cells,” says Patti. The results: Known Good Die (KGD) to achieve Says Caskey. “and design around it with All the performance of high-speed logic high yielding advanced interconnect Monolithic SoCs and package on package with all the retention characteristics of technologies, the semiconductor in- (PoPs).” the DRAM process. It’s repairable and dustry has come to the conclusion While all eyes are on the TSV solu- gets good yield. that it’s time to take a different ap- tion for processor-memory stacks, KGD “We are better yielding in 3D than we proach. It’s called Probably Good problems need to be solved. At Inven- are in 2D,” says Patti. “3D allows us to Die, and when it comes to 2.5D and sas, they’re doing something different. do something that 2D doesn’t; if we have 3D ICs, particularly for Memory, it’s They’ve developed the Bond Via Array a failure we can borrow repair structures a means to an end. At Known Good PoP (BVA PoP); a standard 14mm PoP from other layers. The bigger I make the Die 2012: Reducing Costs through assembly using the existing infrastructure memory, the more repairable it is.” We Yield Optimization, this message but allows for higher I/O. have to change the way we think about rang loud and clear throughout many Built in redundancy helps with design, and 2.5D and 3D have to drive of the presentations, and during the KGD in memory devices noted Richard new solutions. panel discussion. Otte or Promex Industries. He suggests Test capabilities are getting there instead of demanding KGD, we build the to ensure lower cost, says Herb Reiter, assembly for rework. This will require a eda2 asic. This is a clear win for 3D, and The bulk of requirement for KGD different design philosophy than the one he says he’s happy to see the progress is in Memory, says Abe Yee, of NVidia, in place today. Rather than starting at of test in the past few years. What’s manufacturer of graphics processors. the die level and throwing the ball to the missing, he says, is engagement from the The company’s next-generation high next, we should approach it from the sys- EDA community to make cost effective performance GPU is a 28nm device with tem level and design systems that tolerate designs for 3D. System designers assess an enormous amount of vias connecting defects and failures. what 3D can do for you. Pathfinding is the chip at the smallest feature sizes pos- otte also noted that the whole KGD extremely important. There should be sible. “The process window for contact issue is a function of application. We a capability to design in redundancy. vias is very small,” says Yee. “It’s chal- always talk about leading-edge applica- “Why are we refusing to design in redun- lenging and not getting easier. The bad tions. But what about the automotive dancy when its clear how efficient and ef- news is EUV won’t be ready for 10nm.” industry, which is large but everything fective it is to have redundancy designed Calling the graphics processor “GPU on is not leading edge. “There are lots of in?” He asks. steroids”, he noted that it doesn’t work applications where you can make KGD Not everyone is giving up on KGD by itself, but memory bandwidth has not by picking technology that is very robust, quite yet. Gary Fleeman, of Advantest kept up. “We need Wide I/O memory and move away from advanced nodes.” says that the industry is getting closer to to feed the engine,” said Yee. “We need But 3D is something you can’t get KGD and known good stacks (KGS). “I known good stacked die. 2.5D is not another way, says Bob Patti. It precludes don’t like ‘probably good die,” he says. enough for NVidia’s needs. “ safe nodes of technology. While we’re at “I believe in KGD and we’re going to try But die yield loss limits manufactur- it, design for test isn’t good enough any- and get there. Each interim product must ability for 3D ICs, and it’s expensive more either. What we need, says Patti, be a Known Good Product” Fleeman be- to do wafer-level burn-in test says Terry is a new concept: Design for Repair. He lieves that KGD are essential to making Caskey, of Invensas. He explained that should know, his company is the only 2.5 and 3D stacking cost effective. At it’s not just a yield problem, it’s associ- one who is already producing 3D stacked Advantest, they are working on a non- ated with liability issues, which makes it memory using fine-grain TSVs filled with conventional test methodology that en- a business problem. Multi-chip module Tungsten rather than Copper because ables KGD. He talked about work being (MCM) yield loss lands on the assembly “Tungsten just performs better,” says done by IEEE and Erik Jan Marinissen’s houses. Alternatively, monolithic system- Patti. team at imec. There are many new test on-chip (SOC) yield loss is assigned into “Memories are the poster child for the fab, which is easier for the supply design for repair, We disintegrate the continued on page 22  meptec.org WINTER 2012 MEPTEC REPORT 19 PROFILE

Three Decades of Programmable Logic Innovations

process started over, with submitting a Like several other Silicon new design and paying additional NRE. Valley success stories, Altera These issues put gate arrays beyond Corp. emerged from a leg- the reach of many design teams—a fact endary primordial broth: that particularly interested three Fairchild veterans. Bob Hartman, Paul Newhagen, alumni of Fairchild Semicon- and Michael Magranet had formed a ductor, a bedroom office, consultancy to help system design teams MOS process technology, develop gate arrays. In a 1982 book on and a profound shift in the the subject, the three speculated about electronics industry. But the imminence of a new approach: a gate unlike Intel – arguably the array that could be configured electrical- customer could specify how the metal ly, instead of during the manufacturing most famous of these sto- layers on the chip should interconnect process. Such a device would eliminate ries – Altera’s mission has not the gates to form exactly the circuits the NRE, remove the long wait, mitigate the involved changing the world system required. risk, and delete the minimum-order limits as we know it. Rather, Altera This gate-array approach offered of conventional gate arrays. has worked profound chang- system designers substantial advantages in system performance, size, and power es in the invisible infrastruc- by packing just the digital logic circuits Altera is Born ture of electronics – altering the design needed into one chip (or a few not what the industry pro- chips). In fact, such chips did appear as duced so much as the speed, But there were costs. Developing the commercial products shortly after this cost, and risk of the design configuration for the gate array required prediction, but in a slightly different workstations, design tools, and special process. form than the authors had anticipated. skills, all of which were more familiar to At the then-current state of MOS tech- chip design teams than to system design nology, it turned out that the logically teams. The gate-array vendor charged a ideal structure—a vast array of gates that significant up-front fee, which came to would have the same basic topology as a The Customer-Designed IC be called, rather ironically as it turned gate array—was impractical. Instead, the out, non-recurring expense (NRE). The ideal solution for the time was a tree-like The Altera story begins with an time between submitting the design and structure that produced logic functions: a early, seminal change in the way system receiving the chips was often months, Programmable Logic Device (PLD). designers implemented digital elec- and sometimes many months, especially Not intending to be left out of the trend tronics. In the 1970s, designers in IC if the customer was small. And if there they had identified, and believing that companies composed integrated circuits were a problem with the chip, the whole their experience in gate-array design by hand. System designers then cre- ated digital systems by wiring together these standard-product ICs. But by 1980, another approach had appeared: one that allowed the system designers far greater freedom. The semiconductor vendor didn’t, in this new approach, set the function of the IC in stone ahead of time. Instead, the chip company could create an IC that was simply a vast array of uncommitted logic gates. Then the system-designing Altera’s current 28nm portfolio of FPGAs. 20 MEPTEC REPORT WINTER 2012 meptec.org gave them insight into design teams’ at the same time, Altera’s volumes needs, Hartman, Newhagen, and had grown to the point where the com- Magranet called in two more Fairchild pany no longer needed to shop around alumni, semiconductor process expert for the best deal on surplus capacity in Jim Sansbury and ex-Fairchild CFO Jim mature processes. Altera was ready to be Hazle, and set about forming a company. a partner with a first-tier foundry and be After the then-obligatory pilgrimage one of the first users of a new process to Menlo Park, California, in search of node. This in turn meant that for the first venture capital, the new team received an time, FPGAs could offer something like initial $500,000 and in June, 1983 they parity with gate-arrays. The density and officially launched Altera Corporation to performance of an FPGA-based design in design and sell alterable logic devices. a leading-edge process could challenge a half million dollars at that time, the density and performance of the same when as Cypress Semiconductor CEO design implemented with a contemporary TJ Rodgers put it, “Real men own fabs,” mainstream gate array process, which was a very small initial round for a would be about two nodes older. semiconductor company. But along with During the early 2000s, these two being a pioneer in PLDs, Altera was shifts brought about a third change: pioneering in another area as well: the inclusion of specific hard intellectual- fables semiconductor model. The com- property (IP) blocks such as SRAM, pany would design and sell chips, but serial transceivers, and multiply-accumu- would contract with other companies’ 2.5D test chip Altera developed leveraging lators. These functions were increasingly fabrication facilities to actually fabricate TSMC’s CoWoS process. necessary in FPGAs’ new role as sys- the wafers and do the packaging and tems-on-chips (SoCs) and could be done test. In principle, this approach would tively small fabless company, Altera had more efficiently in hard IP. As SoCs, give Altera access to the latest process been conservative about adopting new FPGAs were also pushing to higher pin technology without the growing capital process nodes. Neither customer needs investment necessary to stay near the nor the company’s resources advised an leading edge in wafer manufacturing. aggressive move to an unproven new Altera introduced its first PLDs in 1984. process. But by the mid-1990s the pic- Later, in 1992, after process technology ture was changing. Customers increas- had moved forward several generations ingly used FPGAs not just in fixed-speed the company returned to the founders’ interfaces and bridges, but also in control original vision of an electrically-alterable and data paths, where FPGA perfor- gate array with the FLEX 8000, the mance directly influenced system perfor- company’s first field-programmable gate mance. array (FPGA). from the beginning, programmable logic offered a trade-off. Users could have exactly the logic they wanted—even in very low volumes—without the NRE, wait, and risk of gate arrays. But because the devices use latches and switches in place of fixed metal lines, PLDs are necessarily less dense, slower, and less energy-efficient than the same logic implemented in a gate array. At the same time, the applications for programmable devices—initially in interfaces, bridges, and controllers—tend to require large numbers of pins. So Altera has from its early days challenged packaging technol- ogy to provide high pin counts and good heat dissipation at reasonable prices.

Three Transitions

Just over a decade ago Altera execut- 2.5D heterogeneous devices mixing programmable logic with a variety of other technologies, ed a change in strategy. Earlier, as a rela- in a single package. meptec.org WINTER 2012 MEPTEC REPORT 21 PROFILE

counts—a 1508-pin package was in the generations of PLDs – descendents of (TSVs) and TSMC’s Chip-on-Wafer-on- product line by 2004—substantial power those first tree-structured logic devices – Substrate (CoWoS) 2.5D technology. dissipation, and the ability to handle and five generations of FPGAs. The most The advent of 2.5D brings opportuni- transceivers operating at 3-6 Gbits/s. recent products represent three families ties and challenges. Heterogeneous 2.5D The move from bridge to sub-system of 28 nm FPGAs spanning a range from will offer the ability to greatly expand or system-on-chip brought another the industry’s largest and fastest single- the resources available to an FPGA: change as well. Customers began to find chip devices to low-power/low-cost a huge increase in SRAM, wide-I/O uses for FPGAs as a way of encapsulat- FPGAs used in cost-critical industrial DRAM, hard-IP subsystems, or even ing a subsystem that didn’t require the and consumer applications. customer-defined ASICs. full resources of the largest parts. And needless to say, this product line con- But this advance will require not so Altera’s FPGA product line divided tinues to push the envelope in packaging. just CoWoS, but also known-good-die into three branches: high-end, mid-range, At the high end Altera uses 45x45 mm, techniques to ensure that the completed and low-cost. In the low-cost area in par- 1932-pin FBGAs, often with both pas- assemblies are functional, and novel ticular, customers needed very compact sive and active heat management provi- interconnect architectures to deliver at packages, adding another dimension to sions. In their smallest devices they offer system level the performance and power the company’s packaging needs. an 11x11 mm, 281-pin, 0.5 mm-pitch benefits that 2.5D brings to the circuit MBGA. Many of these packages must level. Altera will continue to push for- support transceivers operating at up to 28 ward on the original promise: bringing Today and Tomorrow Gbits/s, so the company has developed system design teams the ability to define considerable internal expertise in pack- just the silicon they need and implement The trends that defined Altera’s age signal integrity. it on-site, without delays or inordinate early growth have continued. Today, the yet today Altera stands at the thresh- risks. But the company is carrying this company is publicly-traded, with 2011 old of its greatest packaging challenge: promise into a level of performance and revenues over $2 billion. There are 2,600 the dawn of 2.5D. In the future lie not system complexity undreamed of in the Altera employees in 19 countries, while just new process nodes – Altera has founders’ home-office in 1982. ◆ the headquarters remains in San Jose, announced that it is developing products California. in TSMC’s 20 nm CMOS—but multi- altera’s current catalog includes three die packages using through-silicon vias

FOLLOW-UP

 ROADMAPS continued from page 18 test. Steve Smith, of Synopsys, called  KNOWN GOOD DIE continued from page 19 Here are the key takeaways I got test for 2.5D and 3D ICs a “new learning from listening to the speakers and dur- experience,” and that we’re still learning points that will be selectively implement- ing the panel discussion. On one hand, more about configurations being put into ed. Each flow will use different points. silicon interposers are very expensive, interposers and stacked die. He added No flow will use all the points. The key is and organic interposers offer a balance that it’s all boiling down to a solution for tooling, flexibility and integration. between cost and performance. There’s a memory built in self-test (BIST). “All cascade Microtech is also in the well-established infrastructure and supply the components are there,” he said. “The KGD cheering section, and Ken Smith chain, and we don’t have to start from methodology is still being figured out.” of Cascade presented an update on the scratch. However, it’s important to under- Dave Love, of GenapSys, predicts that company’s 3D TSV probe card architec- stand that organic interposers are limited we are going to see more failures at the ture. The cornerstone of this work for to 5µm line and spacing. Anything lower system level that didn’t show up at test. probing TSVs is what the company calls is a function of silicon and not applicable. Joseph Dang at Kyocera said that organic rocking beam interposer (RBI). While However, organic interposers show prom- interposers will be shipped 100% electri- this technology is still in early stages ise from performance and cost perspec- cally tested. Testing an interposer spurred of development, Smith says this work tive to fill a gap where coarse TSVs are some interesting dialogue. Does it need to proves probing microbumps is feasible. required. “Organic substrates are really be tested on both sides? It’s not a circuit, But the bottom line is this: We need promising, but its not here yet,” said Alex so how do you test it? Tsai said there’s 3D ICs, so we’re going to have to do it Tsai, TSMC North America. “What is no way to test every TSV and that in his without relying on KGD. Building in re- here today is a qualified silicon interposer experience at TSMC interposer yield is dundancy, self-test, and repair will make solution.” He was referring, of course, high. “We test to see if we can save cost PGD good enough. I predict that next to TSMCs Chip on Wafer on Substrate not assembling bad die. ‘Pretty good die’ year, this conference will have changed (CoWoS) solution. testing is very good.” Vardaman noted its name to the Probably Good Die Sym- that while lots of progress has been made posium. Has a nice ring to it, don’t you But Can You Test It? in test areas, she doesn’t think there’s think? ◆ During the panel, the topic turned to enough being communicated about it. ◆ 22 MEPTEC REPORT WINTER 2012 meptec.org TECHNOLOGY

Packaging Technology for the Internet of Things

Jayna Sheats, CTO Terepac Corporation

The phrase “Internet of Things” Maybe even more so.”1 of these digital devices – soon to number (often abbreviated IoT) was coined by This vision is very much on the in the trillions – are being connected Kevin Ashton (then – 1999 – a brand agenda of many companies, both large through the Internet. Some call this the manager at Procter and Gamble), in a and small, today. In January 2010 ‘Internet of Things.’” company presentation where he drew Samuel Palmisano, then CEO of IBM, The space is not only for the For- attention to the value of having “things” addressed business and civic lead- tune 500. A few months ago I counted be able to report information about them- ers at Chatham House in London with well over 25 early-stage startups with selves besides just their identity. Ten these words: “Enormous computational sensor technology explicitly directed years later, he acknowledges that RFID power can now be delivered in forms to the Internet of Things (not counting remains at center stage, and this misses so small, abundant and inexpensive that software, communications technology, a huge part of his vision: “It’s not just a it is being put into things no one would or computational systems for digest- “bar code on steroids” or a way to speed recognize as computers: cars, appliances, ing the data and extracting value from up toll roads, and we must never allow roadways and rail lines, power grids, it). And yet commercial success seems our vision to shrink to that scale. The clothes; across processes and global sup- to be some distance away. The Gartner Internet of Things has the potential to ply chains; and even in natural systems, Group’s “hype cycle” analysis last year change the world, just as the Internet did. such as agriculture and waterways. All characterizes it as an emerging technol-

(a) Pre-Press (b) Printing

Diced, thin chips are transferred en masse to transfer Printhead is brought into substrate coated with Digital Release Adhesive™. proximity of substrate.

Light + heat causes vaporization of the DRA, leaving chip adhered to adjacent substrate.

Thin, diced wafer (preferably <50 µm) on thermal or UV released adhesive on framed backing tape.

Printhead removes array of chips (on the underside of Only chips selected by optical exposure (shown in blue) are printed printhead; no charge in relative position from wafer). when the DRA is heated (T<150˚C). One or multiple chips can be printed simultaneously.

Figure 1. The PCA process. meptec.org WINTER 2012 MEPTEC REPORT 23 TECHNOLOGY

a b c

Figure 2. Aerosol printing of conductor precursor over nominal 25 μm chip edges. Clockwise from upper left, the images show a) NXP Mifare 1k; b) MSP430; c) 2x2 mm UHF radio, with test chip at the jog at the bottom; d) 160x160 μm test chip (single metal layer), 25 μm pads; e) NXP Mifare 1k (95 μm pads).

e d ogy which “will take at least another Packaging for Pervasive Computing would have the best chance of achieving decade to unfold”, placing it slightly Joel Birnbaum, former head of R&D true pervasive permeation of all aspects more than halfway up to the “Peak of at Hewlett-Packard, has defined “per- of our surroundings (as well as our bod- Inflated Expectations” (which means that vasive technology” as one which is not ies). it is still confined to the earliest of early only ubiquitous, but is so much a part of In order to bring the power of silicon adopters). life that it is simply not noticed by most ICs into such label formats, thinness is people. The realization of this definition essential. Silicon becomes flexible at a Requirements for Commercialization may take many specific forms, but it thickness of about 50 μm. Following What, then, is needed to move from seems evident that conventional PCBs, experimentation beginning in the late this stage to a realization of the vision so even if “small” (such as a Bluetooth 1990s, processed wafer thinning is now vividly articulated by Kevin Ashton and headset, for example) cannot fade into relatively commonplace and can be taken Samuel Palmisano? Many of the barriers the background if they are to be attached to less than 10 μm. However, such thin are not technological. Business manag- to the human skin as a wound monitor, or wafers, while readily and reversibly ers have to be convinced of the value for placed on or in food packaging (or even bent, are extremely fragile if subjected them, which takes clearly demonstrated directly on food, such as fresh produce) to localized stresses, making it difficult successes. Different parts of an organiza- to report freshness and quality. Even to use conventional pick and place tools tion, and different organizations, perhaps in cases where extreme thinness and with their vacuum tips and ejector nee- in very different industries, have to learn flexibility are not apparently absolutely dles. to work together in new ways. Lack of essential, traditional electronic packaging a second problem with existing tech- fully developed standards for data format may be a poor fit. Suppose, for example, niques is chip size. ICs for the IoT can makes it difficult for a company to effec- that one wished to include some sort of be far smaller than nearly all chips made tively insert itself into the supply chain. wireless sensor in building insulation. today: the complete processor for the nevertheless, there are important Installation of a conventional package original IBM PC would occupy a square technological limitations which must be requires a mechanical operation which of merely 160 μm in 90 nm lithography. eliminated to fully realize the vision. A is unlike any that is part of the current Such sizes are not amenable to high- perusal of IoT offerings shows that they production process; in a conservative throughput pick and place processing, typically cost in the range of tens to hun- industry such as that of building materi- but they have an even more serious dreds of dollars, and are nearly always als, this may present a major obstacle to problem: I/O pad dimensions would have provided on rigid circuit boards. Power widespread adoption. to be much smaller than are compatible requirements are such that AAA batteries almost everything, however, has with the highest density flip chip pro- or lithium coin cells (e.g. CR2032) are a label, including building insulation. cesses available. required. All of this adds up to a pack- Even the aforementioned produce, down age that is too bulky, rigid and costly for to the individual apple or banana, has a Terepac’s Photochemical Circuit many of the applications outlined above. label today. An electronic product which Assembly Process has the size, look and feel of a label Terepac approaches these problems 24 MEPTEC REPORT WINTER 2012 meptec.org Photochemical Component Assembly by replacing the mechanical component Ultrasmall Flexible Ultrasmall placement process with a purely chemi- Products Design Products cal one, but (unlike some competitors) one which retains complete control over the position of each object at all times. Faster, Cheaper Cheaper Flexible The process is illustrated in Figure 1. It Design Cycle begins with a polymer-coated transparent (Less Si Area) (e.g. Wearable) plate, whose surface is sticky enough to Uses Smaller, → Higher- easily pick up thin components when it is Yielding IC Components laminated against them. This plate is then Lower Power Fits product Easily positioned in close proximity over the (Fewer Transistors (e.g. Label) Optimum Match to target substrate in an aligner (very much Customer Needs like the proximity aligners used in low- Fits into Small Spaces resolution photolithography); irradiation More Reliable Printed (Body Implants, Any Technology – No of the polymer behind a chosen chip, plus Interconnect Plants, etc.) heating to a temperature below 150˚C, Fabrication Incompatibility causes complete and rapid vaporization of the polymer, leaving the chip without Small Product Runs are adhesion and allowing it to fall into place Economical on the substrate. Because the forces on the chips are Figure 3. Terepac’s PCA process advantages. uniform at all times, the fragility of very thin silicon is accommodated. There is ing for several reasons. Thin, flexible Conclusions and Outlook no lower limit on lateral size other than labels may use polymer substrates which The advantages of Terepac’s PCA that imposed by optics, which is on the cannot withstand the temperature of process are summarized in Figure 3. micron scale. Throughput depends on solder reflow (especially Pb-free solder); The goal for the future is not merely to the required accuracy of placement. In expensive polyimide would be the only cluster small ICs as traditionally fabri- general the chip will be connected to common exception. Flip-chip solder con- cated, but to actually dis-integrate more other objects (other chips, passive com- nections require the use of epoxy under- complex circuits into submodules (which ponents, or the leads of an antenna). fill, leading to a stiff if not rigid product might be only tens of microns on a side) Terepac uses direct writing of curable despite the thin Si. Finally, as already which can be made in extremely high conductor precursors for this purpose, noted, such processes are not capable of volume and combined into an optimally and so modest misalignment is tolerable achieving the very high pad densities that configured SiP for each application. Such since the direct writing process can adjust will accompany the desired lateral chip a capability offers valuable advantages in for these errors. As a result, the process shrinkage. terms of design flexibility, thereby lower- allows for multiple simultaneous transfers A flip-chip structure using conduc- ing cost, and the minimization of power (by simultaneous irradiation), potentially tive adhesives in place of solder can consumption (a critical factor for the dramatically increasing throughput as overcome the first problem, and to IoT) by minimizing total . compared to any type of mechanical pick some extent the second, but not the The cost of traditional packaging and place transfer. However, even in the third. Therefore, direct interconnection technologies has for some time now event that one were constrained to single of face-up components is an attractive depressed the growth of microelectronic transfers for maximum accuracy, greater option. This could be accomplished by and RF applications (which tended to mechanical simplicity is achieved by the electroplating (or electroless plating) double in number with each 30%-40% having a large array of chips positioned technique advocated by Joe Fjelstad at cost reduction). PCA enables a gen- over the substrate, so that only a small Verdant Electronics in his “Occam” pro- eral transformation of packaging cost, amount of motion of the plate is required cess. It can also be addressed by direct size and flexibility leading to a first in between successive placements. writing, using such techniques as inkjet order, sustainable reduction in cost and or aerosol printing. Figure 2 shows some size while correspondingly increasing Interconnects early examples of this approach using an throughput and flexibility. It has already for products such as RFID tags Optomec aerosol printer at the University demonstrated the capacity to greatly in which there are only two I/O pads, of Waterloo. While some preparation accelerate application growth in many interconnection is relatively simple. of the sidewall in order to avoid shunt- sectors of sensing, actuation, computa- However, wireless sensors typically ing through the remaining silicon and to tion, near field communication and dis- include a and associated minimize the potential for thin spots and tributed intelligence. It will continue to passive components as well as the sen- discontinuities is necessary, these images do so in the future. ◆ sor (which may itself be an IC); separate show that direct interconnect printing is memory and/or communication ICs may feasible with thin (~25 μm) chips; this 1. RFID Journal, 22 July 2009 (article 4986) also be present. For these connections, it is no longer feasible as thickness rises is desirable to avoid traditional solder- above about 50 μm. meptec.org WINTER 2012 MEPTEC REPORT 25 PACKAGING

Multi Die Integration

Y. S. Kim Vice President of Engineering and R&D Signetics Corporation

Multi Chip Packaging (MCP) for memory devices as well as em- bedded Multi Media Cards (eMMC) should be considered when discuss- ing multi die integration based on the Typical Pyramid Stacked Die Package Same Size Die Stack high volume manufacturing experi- ence of semiconductor assembly Figure 1. Stacked die examples. and test services (SATS) providers. Both MCP and eMMC are widely because you are going from checking the is required such as DBG (Dicing Before used for SmartPhones as a storage yields of one die to several in the same Grinding) or GAL (Grinding After stealth solution. MCP is the package level package. Multi chip packages also have Laser sawing). integration of heterogeneous memo- their own specific failure modes that must as SATS providers push the boundar- be monitored. And finally, you must have ies of how thin a wafer can be, there are ry chips, and eMMC is the further in- a very robust overall system to accept the trade-offs. One of the primary challenges tegration of NAND with a Flash Card challenge of assembling MCPs. for thin wafers is known as charge loss. Controller and passives. The yield of Charge loss is an operating voltage shift multi chip packages becomes a criti- Stacked Die (Challenge 1) that can occur after repeated program cal consideration as the affected lot With the push from today and tomor- writing and reading. It can cause the size at the assembly step becomes row’s new technologies to be thinner, program to operate incorrectly and also smaller and more complex, there is a fast data loss. When thinning the die, the 2 to 5x larger than single chip pack- growing need to add multiple devices wafer back side should be polished to get ages if the low test yield is found at within the same package. One widespread strong enough die strength to prevent die final test. Additional critical steps solution for the memory device market level chip/crack during operation. How- that could affect the yield include the has been going in the vertical direction ever, this thinned/polished wafer isn’t back grinding condition, Die Attach by stacking the die. Depending on the protected from the Cu ion diffusion. Film and its cure condition and po- type of devices, the types of interconnects To prevent charge loss, an optimized tential filler damage during mold pro- and configurations of the interconnects, back grinding condition set up is abso- there are a few methods that the SATS lutely required. This can be controlled cess. The following information will industry has used to stack the die. These by selecting appropriate grinding wheel expand on what the key challenges can include many variations including and optimizing the wafer back surface are for the SATS provider when it pyramid stack, same die stack, same die roughness. comes to multi die integration. & pyramid stack and muti stack. (See There is a tradeoff between standard Figure 1) backgrinding and polishing. A finer polished wafer will give the die physical Key Challenges for Multi Chip Thin Wafers (Challenge 2) strength, however, it can be the cause of a Packaging With the requirement for thinner and charge loss. The traditional rough surface for the SATS provider there are three thinner end use applications and package grinding is better for preventing charge key challenges to be faced for the assem- thicknesses, the SATS provider must be loss, but, it can weaken the die strength. bly of multi chip packaging. Stacking also able to overcome the challenge of So the combination of an appropriate multiple die in a package requires unique working with thin wafers. polishing method and roughness control assembly technology that has to be flex- Typical wafer thickness was 200 to is key to preventing charge loss and keep- ible for different variations. Another chal- 250µm in the past. Now it is going down ing the die structurally sound. lenge is backgrinding and the handling of well below 100µm for the multichip thin wafers which keep the overall pack- package and those thin wafers required Assembly Process Flow (Challenge 3) age height at a minimum. Finally, there the wafer backgrinding surface to be The assembly process flow for are challenges for the process flow. Yields polished. As the wafer thickness is now multi die packages is more complex as must be monitored even more closely below 50µm, new thinning technology they have several different chips to be 26 MEPTEC REPORT WINTER 2012 meptec.org TMD Those remaining voids are removed The added complexity to the stan- by the transfer pressure when the mold dard assembly processes demand that compound flows to fill the package at the SATS vendor have a process put in DAF molding. It can be difficult to remove the place specific to the needs of multi chip remaining voids at mold if the DAF has packages. A well systemized process flow become too hardened at die attach cure and a custom control plan are absolutely and wire bonding. required to insure the yields are as good Trapped Void another area to be aware of in relation as those of a single die package. Figure 2. DAF voids – stacked die package. to the DAF is the potential for top metal damage. At molding, mold compound Summary / Conclusion flows to fill the entire mold cavity and The SATS provider must have a solu- processed from backgrind through wire then mold compound (including filler) tion for three primary challenges when bonding process for multiple passes. So a will push the DAF by the pressure ex- assembling multi chip packaging. They more robust process flow system control erted by the mold compound. This pres- must have a unique assembly technology is required. sure on the DAF can create damage to the that is flexible for different variations of one potential issue is the potential for top side of the bottom die. Removal of multi chip packages. Another challenge die attach film (DAF) voids. DAF voids the voids and strong DAF adhesion help is thin wafers which keep the overall can occur between the 1st die and the prevent this from causing the damage to package height at a minimum. The SATS substrate and can cause swelling which the top side metal. provider must have the equipment and will cause a reliability failure. (See another difference during the assem- knowledge of how to backgrind and Figure 2) To remove the DAF voids, a bly process for multi chip packages is the handle these ultra-thin wafers. Process die attach cure process using a pressur- need for multiple die attach and wirebond flows must be made robust and yields ized cure oven is one solution. During passes. Processing the parts multiple must be monitored even more closely as the pressurized cure oven process step times through these process steps increas- multi chip packages have unique failure the DAF voids are pushed out. However, es the potential for yield loss. The SATS modes. Multi chip packages require a not all DAF voids between the substrate provider must also be able to manage the well-planned strategy to overcome these and die are always completely removed. effect of heat during these passes. challenges. ◆

The premier, US-based IC assembly and test subcontractor IC Assembly I SIP & MCM I MIL/Aerospace I Wafer Thinning & Dicing I Environmental & Electrical Test I Engineering

Excellent Quality and Superior Service www.corwil.com 1635 McCarthy Blvd., Milpitas, CA 95035 408.321.6404 meptec.org WINTER 2012 MEPTEC REPORT 27 Groundbreaking Conductive Die Attach Film Takes Thin Die Processing to a New Level

Shashi Gupta and Howard Yun Henkel Electronic Materials, LLC

Semiconductor packages plies with most existing equipment and continue to add even more functionality processes for both lamination and back- to ever-thinner devices and meeting these grinding. (For manufacturers that may demands requires solutions that allow need to invest in lamination equipment for robust processing of thinner, smaller, for pre-cut films, there are multiple pre- higher density packages. Central to pro- cut lamination platforms from which to gressing device miniaturization are the select.) Because of its unique two-in-one materials used to build today’s ultra-small format, LOCTITE ABLESTIK CDF 200P semiconductor devices. This goes not streamlines manufacturing by facilitating only for laminate-based (non-conductive) locTITE ABLESTIK CDF 200P is an in-line process (backgrinding and lami- devices, but for leadframe (conductive) the latest innovation from Henkel’s expert nation) for thin and ultra-thin wafers and applications as well – the miniaturization materials development team. A two-in- also allows for a single lamination process trend extends to multiple package types. one, pre-cut conductive die attach film, in one, combined step. Manufacturers of laminate-based pack- LOCTITE ABLESTIK CDF 200P com- flexibility and extreme capability is ages have long relied on die attach film bines dicing tape and die attach material at the heart of Henkel’s latest conductive technology to enable incorporation of into single, pre-cut 6” or 8” wafer-sized die attach film. Proven effective on a wide much thinner die and to ensure consistent, film formats for easy application. Compat- range of die sizes (from 0.2mm x 0.2mm uniform bondlines with no die tilt. But, ible with lamination equipment commonly to 5.0mm x 5.0mm currently and a 9.0mm this same technology has been unavailable used in the field, LOCTITE ABLESTIK x 9.0mm capable formula in develop- for conductive applications until recently. CDF 200P requires no capital equipment ment), a variety of wafer metallizations When Henkel introduced the first-ever investment, as it has been specifically including bare silicon, TiNiAg and Au, conductive die attach film materials two designed for equipment adaptability. With and multiple leadframe metallizations years ago it was, indeed, welcome news a lamination temperature requirement for the semiconductor packaging market. of 65°C, Henkel’s conductive film com- continued on page 32  LOCTITE ABLESTIK C100 debuted to widespread validation, with major semi- conductor device manufacturers publicly stating the advantages of the material’s ability to enable package scalability. With a viable alternative to traditional paste- based die attach materials, leadframe device specialists could now capitalize on the inherent benefits of film-based medi- ums – namely, the ability to incorporate thinner wafers, realize uniform bondlines and integrate more die per package due to the tighter die to pad clearance afforded by film. Originally available in roll for- mat, where both the die attach film and dicing tape are laminated onto the wafer in two separate lamination processes, Henkel has now extended the portfolio to also include a pre-cut version of the breakthrough conductive film technology that is ideal for use with ultra-thin wafers.

28 MEPTEC REPORT WINTER 2012 meptec.org

Better Reliability Through Chemistry

Wataru Tachikawa and Jianwei Dong Dow Electronic Materials

The semiconductor industry including micro-bumps for TSV applica- (WID) is required for Cu pillars. In addi- is approaching a pivotal point where tions, which could increase the percent- tion, maintaining tight control of total there will be no other way to achieve age further. Target applications include indicator reading (TIR) – the index for the performance, bandwidth and storage mobile devices, memory and high-end pillar top flatness – is critical to avoid required of next-generation data centers logic chips. (Source: Prismark’s Semi- dropping the tin silver solder bumps and mobile devices without 2.5D and 3D conductor and Packaging Report, Q2 during the subsequent pillar cap reflow integration technologies. As such, the 2012.) process. entire ecosystem is collectively rolling up There are several technical reasons Dow’s INTERVIA™ 8700 Cu chem- its sleeves and real work is being done to why transitioning from traditional solder istry features excellent WID and TIR overcome the remaining challenges. bumps to Cu pillars capped with SnAg with a high-speed plating rate of ~14 One remaining hurdle is assuring reli- makes sense. In 100% of controlled ASD. This product has excellent physi- ability of these devices, particularly for collapse chip connection (C4) bump cal properties and bonding reliability as use in high-end server applications where fabrication, reflowable solders collapse a result of its pure deposition capabili- part failures are much more catastrophic and spread during reflow. Therefore, ties (~5 ppm total organic impurities). than in consumer mobile devices. Reli- to prevent bridging, bump pitch must When combined with SOLDERON™ BP able device performance can be linked be limited to 140µm. Additionally, the TS4000 SnAg chemistry, which features directly to materials used in advanced reduced bump stand-off height inhibits high-speed, uniform, fine-grain deposi- packaging assembly processes. In fact, the flow of underfill. Alternatively, Cu tions with void-free reflow performance, reliability is such a concern for data cen- pillars allow for tighter bump pitch, the resulting SnAg-capped Cu pillars ters that they are still exempt from RoHS and because Cu is not reflowable it will have uniform, void-free inter-metallic requirements, and rely on legacy tin-lead maintain good stand-off height. Another compound (IMC) layers (Figure 1). for bumping processes. However, that advantage of Cu is its better thermal con- exemption is set to expire in 2015, and ductivity than solder, which is critical for solutions will need to be ready to put in high-speed and high-frequency devices, place by then. This is a two-fold chal- such as MPUs. Finally, compared with lenge with 3D ICs, which require fine- tin-based lead-free solder materials, Cu is pitch microbumps that are difficult to a lower cost lead-free option. achieve with standard solder materials, in addition to needing to be reliable. Until Just Good Chemistry this is sorted out, 3D ICs are unlikely to Dow Electronic Materials is address- be used to solve the data center band- ing the 2.5D and 3D IC reliability and width solution. process issues head on, making great Figure 1. Cross-section of Cu pillars capped strides in materials for, among other with SnAg capped pillar shows IMC com- The Copper Pillar Advantage things, advanced packaging with bump patibility. copper (Cu) pillars with tin-silver plating for flip chip targeting not only (SnAg) caps are emerging as a viable reliability challenges but process chal- A Seamless Process alternative to traditional bumping tech- lenges as well. The company has devel- An added benefit of Dow’s Cu and nologies. According to Prismark Part- oped Cu and SnAg plating chemistries SnAg chemistries is that they demon- ners, in 2011, bumped wafer production and processes that are exceptionally com- strate great compatibility, which trans- reached 10.5M (300 mm equivalent) patible and work well in tandem when lates into higher yield and mitigated wafers, of which only 3% were Cu/SnAg used in Cu pillar applications. manufacturing risk. Unlike other materi- capped pillars. By 2016, the market first-generation Cu pillars use solder als suppliers that supply either Cu or research firm predicts that the total num- paste, but in 3D stacking, this will give SnAg plating chemistry, Dow supplies ber of bumped wafers being produced way to Cu posts with SnAg caps as the both chemistries with a good under- will more than double to 21.9M (300 mm preferred method. Because Cu is not standing of how to optimize the process equivalent) with 20% of those using Cu/ reflowable, as previously mentioned, integration specifically for SnAg-capped SnAg capped pillars, and that’s not even excellent thickness control within die continued on page 32  30 MEPTEC REPORT WINTER 2012 meptec.org

 DOW continued from page 30  HENKEL continued from page 28  OPINION continued from page 34

Cu pillar applications. In the end, highly such as Cu, Ag or Au, LOCTITE ABLES- es (21%). U.S. hospitals are world-class reliable Cu-SnAg interfaces are achieved TIK CDF 200P offers superior process and contribute enormously to performing (Figure 2). adaptability. Not only can the material miracles – saving and extending lives. At manage such a wide die range, but its the same time, hospitals are extremely effectiveness has now been proven on die expensive hotels and restaurants. More- as thin as 50µm! Internal testing confirms over, hospitals can be dangerous places. LOCTITE ABLESTIK CDF 200P’s abil- The longer the patient is confined to ity to achieve lamination, dicing, pick-up the hospital, the risks of infection, side- and die bond processing on 50µm thick effects, and chronic pain increase. There- wafers with die sizes ranging from 0.2mm fore, part of a systemic reform would x 0.2mm to 2.0mm x 2.0mm. And, be to devise solutions that diminish the Henkel’s not stopping there: the company demand (need) for hospital admissions is currently testing the new material’s and hospital-based delivery of services. capability on 50µm thin 9.0mm x 9.0mm new health ICT offers the prospect of die, as well as its laser dicing perfor- reworking information flows inside the mance. Results of these evaluations are hospital while at the same time redefin- expected by year-end. ing health care facilities to include the not only are these new materials provision of a “virtual blanket of care” process-friendly, they also offer all of the for customers to reduce the eventual advantages of film technology. Henkel’s demand for onsite services. This includes Figure 2. Schematic of process flow for Cu pillar fabrication and SnAg capping. portfolio of conductive die attach films early detection, diagnosis and decision- provide greater design leverage by allow- making tools that can eliminate the need ing tighter clearance between the die and for services and/or move patients back the die pad due to the elimination of the into their homes and workplaces more fillet. This means that packaging design- quickly following treatment. ers can incorporate more die and/or more The April IMS 2013 conference will functionality into a single package. With examine the concept of Intelligent Medi- no fillet and higher density chip designs, cal Systems (IMS). It will look “beyond” packaging specialist can also lower costs the biomedical device to define the scope because the amount of gold wire, sub- and organization of an IMS and consider strate and mold compound required per the integration of key components. It unit package is significantly reduced. will emphasize the importance of view- As compared to alternative materials, ing discrete components – biomedical LOCTITE ABLESTIK CDF 200P’s total drugs, devices, diagnosis, and delivery cost of ownership (TCoO) is measurably technologies – as elements in a coher- Figure 3. 20 μm Cu pillars capped with lower. ent and responsive networked system. In SnAg (40 μm pitch). Henkel’s portfolio of conductive die addition it will explore the implications attach films – both LOCTITE ABLES- and opportunities associated with adding Conclusion TIK C100 in roll format and LOCTITE “intelligence” into devices and enabling compatible materials for forming ABLESTIK CDF 200P in pre-cut, two-in- them to make decisions, as well as for Cu pillars with SnAg bumps is just one one format – are set to accelerate effective the addition of connectivity – especially small part of Dow Chemical’s solutions implementation of highly miniaturized, wireless connectivity – to overcome the for emerging 3D TSVs. The company has multi-die device designs which are simply limitations of time and distance in care developed a whole family of enabling unachievable with paste- or liquid-based delivery. Finally, it will attempt to pro- materials engineered to improve the reli- mediums. vide solutions to the barriers and chal- ability of next-generation interconnect To find out more about Henkel’s line lenges to, and to escalate the growth of, technologies. Dow’s process chemistries of conductive die attach film materials, IMS in healthcare. We hope you join us include bump plating photoresists, etch- log onto www.henkel.com/electronics, at this exciting inaugural event. ing photoresists, ancillaries and bonding send an e-mail to [email protected] for more information and to register layers, all of which are formulated for or call 1-888-943-6535 in the Americas, today, visit the MEPTEC website at compatibility to provide solutions for +44 1442 278 000 in Europe and +86 21 www.meptec.org. For information about each step of the process, to ensure that 3898 4800 in Asia. ◆ sponsorship and exhibiting opportuni- the end device meets the reliability stan- ties contact Bette Cooper at bcooper@ dards required by the industry now and meptec.org or call 650-714-1570. ◆ in the future. For more information about Dow Electronic Materials’ portfolio, visit www.dowelectronicmaterials.com. ◆ 32 MEPTEC REPORT WINTER 2012 meptec.org CONFERENCE & EXHIBITION

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IPC APEX EXPO provided my company with valuable information and contacts to move us into the next generation of products. Charlie Davis Quality Engineer Electronics Assembly Crown Equipment Corporation

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Join thousands of your colleagues from more than 50 countries and more than 400 exhibitors at IPC APEX EXPO 2013 in beautiful San Diego. Learn about new technologies and processes, see new products, work on industry standards, network with industry experts and participate in the world’s premier technical conference for electronics manufacturing. Register today! Find solutions that will help you save time and money and gain a competitive advantage. www.IPCAPEXEXPO.org Scan for your chance to win a three-night hotel stay or an MVP registration. design | printed boards | electronics assembly | test and printed electronics OPINION

The Coming Era of Intelligent Medical Systems (IMS): Bringing Biomedical Devices to Life

Donald Hicks, Ph.D., Professor of Political Economy and Public Policy The University of Texas at Dallas, and Special Assistant to University President David E. Daniel, Ph.D.

In April 2013 MEPTEC will join the hoped-for patient outcomes. Many fac- ered on a fee-for-service basis via 3rd- University of Texas at Dallas in pre- tors (hospital/physician culture; organi- party payments that result in errors of senting an event titled “IMS 2013 – zational, regulatory, etc.) are implicated, omission and commission, inefficiency, The Coming Era of Intelligent Medical with perhaps the majority being nontech- and high costs. A seemingly sensible Systems: Bringing Biomedical Devices nical. solution would be to transform the cur- to Life”. A co-chair of the event, Don- rent mosaic of siloed service providers ald Hicks, Ph.D., Professor of Political into a coherent “horizontal” system Economy and Public Policy, The Uni- Today, the essential capable of generating improved access, versity of Texas at Dallas and Special better patient outcomes and extending the reach of today’s health care facili- Assistant to University President David activities – clinical and ties into the spaces beyond hospitals and E. Daniel, Ph.D. shares his thoughts clinics. We see at least some of this logic on the subject. operational – by which emerging in the Accountable Care Orga- health care is delivered nization and Medical Home initiatives In 1987, Robert Solow, a Nobel taking shape around the nation. These prize-winning economist, observed “You have largely remained restructurings improve the prospects for can see the computer age everywhere adoption of varieties of disease manage- these days except in the productivity untouched by networked ment and remote patient monitoring that, statistics”. His observation – the Solow theoretically at least, could enable early Paradox – captured the puzzling reality ICT (information and disease detection and response…that is, that despite abundant evidence of myriad anticipatory and preventative interven- technical advances ushering in the so communication tions. called “Computer Revolution,” there was However, because health ICT threat- scant evidence of expected measurable technologies) advances. ens (promises) to put downward pres- benefits. Steady advances in memory sure on the need to “go to the doctor/ (later logic) chips and related capabilities hospital,” ICT upends the conventional may have expanded the form and func- business model of the hospital (or physi- tion of essentially stand-alone devices, u.S. health care services are deliv- cian practice). Therefore, the opportunity but they had little impact on the context ered through a hodge-podge of legacy presented to ICT service companies and within which they were introduced. A arrangements that lack coordination and its allies is to offer ICT-intensive solution few years later, however, that began to integration. As a result, this “system,” suites that are compatible with a new change. The key impetus? Computer – composed of the world’s best biomedi- business model, a transformed enterprise, then communications – networking and cal advances (drugs, diagnostics and and new paths to value creation. They the beginning convergence of the two. devices); best-trained medical personnel; can bundle metered and subscription In some respects, one could argue and best-equipped health care facili- wireless services to help transform its that we are at a similar junction in the ties, fails to produce world-class patient enterprise customers in ways that will evolution of health care and our ability outcomes at prices that enable access by facilitate the flow of ICT innovations into to deliver it. Today, the essential activi- large portions of the population. While 21st-century health care. ties – clinical and operational – by which there is much talk of system reform, it is Where do we begin? One suggestion health care is delivered have largely often difficult to find the hand-holds for is to follow the money. The major cost remained untouched by networked ICT proceeding. buckets for U.S. heath care are hospital (information and communication tech- The general problem in health care is care (32%) and physician/clinical servic- nologies) advances. As a result, we see distorted markets. These take the form of rising costs and evidence of less-than- redundant or gap-filled services, deliv- continued on page 32  34 MEPTEC REPORT WINTER 2012 meptec.org Platform Provides: • Lower cost system packaging • Ultra-fine pitch, ultra-thin die • 28nm node • Controlled stress for ULK • 2.5/3D Through Silicon Via (TSV) enablement • Enhanced electromigration resistance • Superior thermal performance • Pb-free / Low alpha solution • High manufacturing throughput Cu pillar PB-free With proven reliability in µbumps fc bumps volume manufacturing! Bump • Assembly • Test Si Interposer & TSVs

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