Traveo™ II Direct Memory Access (DMA)

Customer Training Workshop Traveo™ II Direct Memory Access (DMA)

Q4 2020 Target Products

› Target product list for this training material

Family Category Series Code Flash Memory Size Traveo™ II Automotive Body Controller Entry CYT2B6 Up to 576KB Traveo II Automotive Body Controller Entry CYT2B7 Up to 1088KB Traveo II Automotive Body Controller Entry CYT2B9 Up to 2112KB Traveo II Automotive Body Controller Entry CYT2BL Up to 4160KB Traveo II Automotive Body Controller High CYT3BB/CYT4BB Up to 4160KB Traveo II Automotive Body Controller High CYT4BF Up to 8384KB Traveo II Automotive Cluster CYT3DL Up to 4160KB Traveo II Automotive Cluster CYT4DN Up to 6336KB

› DMA is part of the CPU subsystem Hint Bar

CPU Subsystem CYT2BL Review TRM chapter 7 for

MXS40-HT SWJ/ETM/ITM/CTI SWJ/MTB/CTI

P P

92 Channel 44 Channel

eCT Flash 4 Channel CRYPTO additional details - ASIL-B -

- Arm Cortex

DMA0 DMA1

SRAM0 SRAM1 DMA0 ROM Arm Cortex M4 4160 KB Code-flash + AES, SHA, CRC, 128 KB Work-flash 256 KB 256 KB TRNG, RSA, M0+ 32 KB 160 MHz ECC 100 MHz System Resources 8 KB $ 8 KB $ FPU, NVIC, MPU FLASH Controller SRAM Controller SRAM Controller Initiator/MMIO MUL, NVIC, MPU ROM Controller Power Sleep Control POR BOD OVD LVD System Interconnect (Multi Layer AHB, IPC, MPU/SMPU) REF PWRSYS-HT LDO PCLK Peripheral Interconnect (MMIO, PPU)

Clock Clock Control

2xILO WDT Prog. CAN IMO ECO Analog TIMER, CTR, QD, PWM

FLL CSV Generator Event

83x TCPWM

I2C, SPI, UART I2C, SPI, UART

CXPI Interface 8xCANFD

1xPLL SAR EVTGEN

4x CXPI4x

12x LIN

1xSCB 7xSCB

LIN/UART

eFUSE FD Interface

ADC 1024 bit IOSS GPIO Reset (12-bit) Reset Control XRES Test TestMode Entry x3 Digital DFT Analog DFT

SARMUX WCO 64 ch RTC

Power Modes High-Speed I/O Matrix, Smart I/O, Boundary Scan Active/Sleep LowePowerActive/Sleep 5x Smart I/O DeepSleep Up to 148x GPIO_STD, 4x GPIO_ENH Hibernate I/O Subsystem

› DMA is part of the CPU subsystem Hint Bar

ITCM DTCM CPU Subsystem ITCM16 KB DTCM16 KB SWJ/ETM/ITM/CTI CYT4BF 16 KB 16 KB Review TRM chapter 7 for MXS40-HT SWJ/ETM/ITM/CTI SWJ/MTB/CTI

Cortex M7 143 Channel

P P 65 Channel

ASIL-B eCT FLASH 8 Channel additional details

- -

350 MHz - CRYPTO DMA0 Cortex M7 SRAM0 SRAM1 SRAM2 DMA1 ROM 8384 KB Code flash DMA0 AES,SHA,CRC, 350 MHz 512 KB 256 KB 256 KB Cortex M0+ 64 KB FPU D$ I$ + 256 KB Work flash TRNG,RSA,ECC (SP/DP) 16KB 16KB 100 MHz System Resources FPU D$ I$ AHBP NVIC, MPU, AXI AHBS (SP/DP) 16 KB 16 KB 8 KB $ SRAM SRAM SRAM Power Initiator/MMIO ROM Controller AHBP NVIC, MPU, AXI AHBS FLASH Controller Controller Controller Controller MUL, NVIC, MPU Sleep Control POR BOD OVP LVD System Interconnect (Multi Layer AXI/AHB, IPC, MPU/SMPU) REF PWRSYS-HT

LDO PCLK Peripheral Interconnect (MMIO,PPU) Serial Memory Interface (Hyperbus, Single SPI, Clock

Clock Control Dual SPI, Quad SPI, Octal SPI) 10/100/1000 Ethernet + AVB

2xILO WDT Prog. TIMER,CTR,QD, PWM

IMO ECO Analog SD/SDIO/eMMC

Event Generator Event

115x TCPWM

I2S/TDM In/Out I2S/TDM

I2C,SPI,UART,LIN I2C,SPI,UART,LIN

1x FLEXRAY1x

CAN

FlexRay Interface

3xAUDIOSS

1xSMIF 10x CANFD

FLL CSV ETH2x

SAR SDHC

EVTGEN

10x SCB

20x LIN

1x SCB1x

EFUSE LIN/UART

4xPLL -

ADC FDInterface IOSS GPIO (12-bit) Reset Reset Control XRES x3 Test TestMode Entry Digital DFT SARMUX Analog DFT 96 ch

WCO RTC High Speed I/O Matrix, Smart I/O, Boundary Scan 5x Smart IO Power Modes Active/Sleep Up to 196x GPIO_STD, 4x GPIO_ENH, 40xHSIO LowPowerActive/Sleep DeepSleep I/O Subsystem Hibernate

› DMA is part of the CPU subsystem Hint Bar

ITCM DTCM CPU Subsystem GFX Subsystem Review TRM chapter 7 for ITCM64 KB DTCM64 KB CYT4DN SWJ/ETM/ITM/CTI 64 KB 64 KB additional details MXS40-HT SWJ/ETM/ITM/CTI SWJ/MTB/CTI

Cortex M7 Gfx Vector

P 76 ASIL-B 84

eCT FLASH 8 Channel

- -

- CRYPTO

320 MHz

DMA0

DMA1 Channel Cortex M7 SRAM0 SRAM1 SRAM2 Channel ROM DMA0 VRAM 6336 KB Code-flash AES,SHA,CRC, 320 MHz 256 KB 256 KB 128 KB Cortex M0+ 64 KB 4096 KB FPU D$ I$ + 128 KB Work-flash TRNG,RSA,ECC (SP/DP) 16KB 16KB 100 MHz FPU D$ I$ AHBP NVIC, MPU, AXI AHBS (SP/DP) 16 KB 16 KB 8 KB $ SRAM SRAM SRAM System Resources Initiator/MMIO ROM Controller VRAM Controller AHBP NVIC, MPU, AXI AHBS FLASH Controller Controller Controller Controller MUL, NVIC, MPU Power Sleep Control POR BOD OVP LVD System Interconnect (Multi Layer AXI/AHB, IPC, MPU/SMPU) GFX Interconnect (AXI) REF

PWRSYS-HT 2x RGB/LVDS Output RGB/LVDS 2x

LDO PCLK Peripheral Interconnect (MMIO,PPU) Serial Memory Interface (Hyperbus, Single SPI, 1x RGB/MIPI Input RGB/MIPI 1x

Clock Engine 2.5D Dual SPI, Quad SPI, Octal SPI)

Clock Control 10/100

2xILO WDT Prog. TIMER,CTR,QD, PWM, SMC

IMO ECO Analog

Event Generator Event

/1000

2 I2C,SPI,UART,LIN

FLL CSV I2C,SPI,UART,LIN

CAN

2x SMIF2x

x PCM

1xETH

Audio DAC

4x CANFD4x CXPI Interface

SAR EVTGEN

8xPLL LPECO 11x SCB

2x CXPI2x

x TCPWM

1x SCB1x

EFUSE

LIN/UART

2x LIN2x

5x SG5x

x Mixer

Ethernet + AVB x TDM

ADC FD Interface IOSS GPIO Reset (12-bit) x I2S

Reset Control - XRES PWM Test TestMode Entry x1 Digital DFT Analog DFT

SARMUX WCO 48 ch RTC

Power Modes High Speed I/O Matrix, Smart I/O, Boundary Scan Active/Sleep 1x Smart IO LowePowerActive/Sleep 52x GPIO_STD, 8x GPIO_ENH, 26x GPIO_SMC, 70x HSIO_STD, 22x HSIO_ENH, 4x HSIO_ENG_DIFF DeepSleep Hibernate IO Subsystem

› Traveo II has two types of DMA Hint Bar – Peripheral DMA (P-DMA) Feature P-DMA M-DMA Focus Low latency High memory bandwidth Review TRM chapter 7 for – Memory DMA (M-DMA) additional details Used for Transfer between peripheral and Transfer between memories2 memory1 Features highlighted in Transfer Shared between all channels Dedicated for each channel blue are the main engine difference between P-DMA and M-DMA. Transfer size 8-bit/16-bit/32-bit 8-bit/16-bit/32-bit Channel Four levels Four levels Refer to the Protection priority Preemptable Units training section for additional details Transfer mode - Single - Single - 1D/2D - 1D/2D - CRC transfer - Memory copy - Scatter Descriptor - Source and destination address - Source and destination address - Transfer size - Transfer size - Channel action - Channel action - Data transfer mode - Data transfer mode - Activation trigger type (4 types) - Activation trigger type (4 types) - Output trigger type (4 types) - Output trigger type (4 types) - Interrupt type (4 types) - Interrupt type (4 types) - Descriptor chaining - Descriptor chaining Access-control - Privileged/Unprivileged - Privileged/Unprivileged attributes3 - Secure/Non-secure - Secure/Non-secure 1 P-DMA can also be used to transfer data between memories. - Protection contexts - Protection contexts 2 M-DMA can also be used to transfer data between peripheral and memory. 3 P-DMA and M-DMA channels inherit the access attributes of the bus transfer that programmed the channel.

› Trigger Multiplexers Hint Bar – Connect each channel to one specific system trigger Review TRM section 7.1.6 – Include hardware1 (HW) and software (SW) system triggers and chapter 29 for additional details – Trigger output (tr_out) Refer to Descriptor – Each trigger output can be used as its own active trigger using trigger multiplexers Chaining for Chain Transfer details – They can be used to trigger different transfers as input triggers for other channels2

Trigger P-DMA Multiplexer

tr_in[] tr_in[0] Pending Priority Hardware triggers CH 0 Data Transfer Engine tr_out[] Software triggers Triggers Decoder tr_in[1] CH 1 ・・・・・・tr_in[n] CH n

status control

Interrupts[] Interrupt Bus MMIO Bus Master I/F Logic Slave I/F Registers

Memory 1 Refer to the device datasheet for available hardware triggers. 2 tr_out can execute a chain transfer. Descriptor chaining can also execute a chain transfer.

› Use Case: CRC calculation of serial communication data 1 4 Hint Bar P-DMA Destination – Combined operation of Descriptors 0 and 1 Memory SCB Refer to CRC Transfer for – P-DMA: Source (FIFO) CRC calculation d7 d5 d3 d1 3 d4 d5 d5 d6 Channel 1 3 d0 d1 d2 d3 1– Is triggered by SCB when data reception d6 d4 d2 d0 is complete == == CH 0: Descriptor 0 Descriptor 1 2– Loads Descriptor 0 from memory - Input Trigger = SCB 2 Descriptor 0 3– Transfers from FIFO to memory - Output Trigger = End of Descriptor - Next Descriptor Pointer = Null 4– Outputs tr_out after completing Descriptor 0 transfer CH 1: Descriptor 1 - Input Trigger = Output Trigger of CH 0 P-DMA 5– Loads Descriptor 1 by tr_out - Interrupt = End of Descriptor 7 9 - Next Descriptor Pointer = Null CRC 6– Activates CRC Transfer mode Calculation Destination SCB Memory – Runs CRC calculation Source (FIFO) 7 8 d7 d5 d3 d1 Result 8– Transfers CRC result to destination address Channel 1 6 d4 d5 d5 d6 d6 d4 d2 d0 d0 d1 d2 d3

9– Generates interrupt to CPU by end of descriptor == ==

5 Descriptor 1

› Advantage Descriptor 0 – Multiple data transfers can be executed continuously by one trigger

› Pending Triggers › Priority Decoder Hint Bar – Keeps track of activated triggers by storing – Determines the highest-priority channel triggers Review TRM section 7.1.6 channel of pending triggers for additional details – Manages multiple pending channel triggers – Has four priority levels › Available Pre-emptive Setting – Performs round-robin arbitration – If set, the higher-priority pending channel can within the same priority group pre-empt the current channel between single transfers Trigger P-DMA Multiplexer tr_in[] tr_in[0] Pending Priority Hardware triggers CH 0 Data Transfer Engine tr_out[] Software triggers Triggers Decoder tr_in[1] CH 1 ・・・・・・tr_in[n] CH n

status control

Interrupts[] Interrupt Bus MMIO Bus Master I/F Logic Slave I/F Registers

Memory

› Data Transfer Engine Hint Bar – Shared by each channel Review TRM section 7.1.6 – Transfers data from source to destination according to descriptor for additional details – Reads channel descriptor from memory – Generates the trigger out to trigger multiplexers

Trigger P-DMA Multiplexer tr_in[] tr_in[0] Pending Priority Hardware triggers CH 0 Data Transfer Engine tr_out[] Software triggers Triggers Decoder tr_in[1] CH 1 ・・・・・・tr_in[n] CH n

status control

Interrupts[] Interrupt Bus MMIO Bus Master I/F Logic Slave I/F Registers

Memory

› Descriptor Hint Bar – Stored in memory Review TRM chapter 7.1.3 – Supports descriptor chaining Trigger P-DMA Multiplexer and Register TRM for tr_in[] tr_in[0] Pending Priority additional details – Descriptor types Hardware triggers CH 0 Data Transfer Engine tr_out[] Software triggers Triggers Decoder tr_in[1] CH 1 System RAM is used store – Single transfer ・・・・ the descriptor ・・ tr_in[n] – 1D transfer CH n – 2D transfer status control Interrupts[] Interrupt Bus MMIO Bus Master I/F – CRC transfer Logic Slave I/F Registers – Descriptor structure – Descriptor control:

Memory Trigger type, transfer size, descriptor type +14 Next Descriptor Pointer – Source address/destination address +10 Y(Outer) Loop Control +0c X(Inner) Loop Control – X(Inner) loop/Y(Outer) loop control +08 Destination Address – Next descriptor pointer +04 Source Address – The descriptor pointer position for Descriptor Pointer +00 Descriptor Control each channel is stored in the register

› Descriptor Chaining Hint Bar – Descriptors are chained by storing the next descriptor pointer in the Descriptor 0 - Data transfer to Buffer0 from FIFO current descriptor - Chained to Descriptor 1 A descriptor chaining group is also referred to – “0” (NULL pointer) is stored at the end of the descriptor list as a descriptor list – It is possible to have a circular list. It will stop when: P-DMA Interrupt to CPU 1 The address of the current – A transfer error occurs descriptor is indicated in – The controller or channel is disabled by software Descriptor 0 Destination the CH_CURR_PTR Memory SCB 2 register d4 d5 d6 d7 Source (FIFO) Buffer1 d0 d1 d2 d3 d7 d5 d3 d1 The next descriptor – Use Case: Double buffer storing d4 d5 d6 d7 Buffer0 address is updated after d6 d4 d2 d0 d0 d1 d2 d3 using two descriptors the execution of the – Descriptors 0 and 1 are chained together Descriptor 1 current descriptor - Data transfer to Buffer1 from FIFO P-DMA is triggered by SCB - Chained to Descriptor 0 M-DMA also has the same 1 register Descriptor 0: Data transfer from SCB to Buffer0 P-DMA Interrupt to CPU 2 3 ⇒ Descriptor chaining to Descriptor 1 Descriptor 1 Destination –3 P-DMA is triggered by SCB Memory SCB 4 d4 d5 d6 d7 – Descriptor 1: Data transfer from SCB to Buffer1 Source (FIFO) Buffer1 4 d0 d1 d2 d3 d7 d5 d3 d1 ⇒ Descriptor chaining to Descriptor 0 d4 d5 d6 d7 Buffer0 d6 d4 d2 d0 d0 d1 d2 d3

+0c Next Descriptor Pointer › Single Transfer Hint Bar Y(Outer) Loop Control – Single data element (8-bit, 16-bit, or 32-bit) transfer X(Inner) Loop Control Review TRM chapter 7.1.3 – Uses four-word descriptor and Register TRM for +08 Destination Address additional details

– Transfer example: +04 Source Address

DST_ADDR = (DATA_SIZE) SRC_ADDR +00 Descriptor Control › Use Case: Transfer A/D conversion results with A/D trigger

–1 Move stored conversion data to data register –2 Activate P-DMA with Channel Done trigger –3 Transfer data from SRC_ADDR to DST_ADDR 2 4 4 P-DMA – Generate interrupt to CPU Channel Done Trigger Interrupt

Destination 3 Memory Source A/D Convertor SRC_ADDR DST_ADDR 1 ADC Data Data

SRC_SIZE: 32-bit DATA_SIZE: 16-bit DST_SIZE: 16-bit

+10 Next Descriptor Pointer › 1D Transfer Hint Bar Y(Outer) Loop Control – One-dimensional “for loop” transfer +0c X(Inner) Loop Control Review TRM section 7.1.3 – Uses five-word descriptor and Register TRM for +08 Destination Address additional details

– Transfer example: +04 Source Address for (X_IDX =0; X_IDX <= COUNT; X_IDX++){ DST_ADDR[DST_INCR] = (DATA_SIZE) SRC_ADDR[SRC_INCR] +00 Descriptor Control } *DST_INCR/SRC_INCR depend on X_INCR

› Use Case: Transfer SCB reception data in FIFO 3 P-DMA Interrupt –1 Activate P-DMA by receiving a completion trigger 1

–2 Repeat data transfer from SRC_ADDR Descriptor 0 Destination to DST_ADDR by COUNT SCB SRC_ADDR = FIFO Address 2 DST_INCR = 1 COUNT –3 Generate interrupt to CPU +0 +1 +2 +3

d7 d6 d5 d4 d3 d2 d1 d0 d4 d5 d6 d7 d0 d1 d2 d3 DST_ADDR SRC_INCR = 0

SRC_SIZE: 8-bit DATA_SIZE: 8-bit DST_SIZE: 8-bit

+14 Next Descriptor Pointer › 2D Transfer Hint Bar +10 Y(Outer) Loop Control – Two-dimensional “for loop” transfer +0c X(Inner) Loop Control Review TRM section 7.1.3 – Uses six-word descriptor and Register TRM for +08 Destination Address additional details – Transfer example: +04 Source Address for (Y_IDX =0; Y_IDX <= Y_COUNT; Y_IDX++){ for (X_IDX =0; X_IDX <= X_COUNT; X_IDX++){ +00 Descriptor Control DST_ADDR[DST_INCR] = (DATA_SIZE) SRC_ADDR[SRC_INCR] } } *DST_INCR/SRC_INCR depend on X/Y_INCR › Use Case: Transfer SCB reception data in FIFO (1/2)

– Handling multiple FIFO data as one data P-DMA 1 Interrupt to CPU 1 Activate P-DMA by receiving a completion trigger 2 Repeat data transfer from Descriptor 0 Destination SCB SRC_ADDR = FIFO Address SRC_ADDR to DST_ADDR X_COUNT 2 X_DST_INCR

by X_COUNT 1st +0 +1 +2 +3

Reception d7 d6 d5 d4 d3 d2 d1 d0 Y_COUNT

DST_ADDR d4 d5 d6 d7

+14 Next Descriptor Pointer › 2D Transfer Hint Bar – Two-dimensional “for loop” transfer +10 Y(Outer) Loop Control +0c X(Inner) Loop Control Review TRM section 7.1.3 – Uses six-word descriptor and Register TRM for – Transfer example: +08 Destination Address additional details for (Y_IDX =0; Y_IDX <= Y_COUNT; Y_IDX++){ +04 Source Address for (X_IDX =0; X_IDX <= X_COUNT; X_IDX++){ +00 Descriptor Control DST_ADDR[DST_INCR] = (DATA_SIZE) SRC_ADDR[SRC_INCR] } } *DST_INCR/SRC_INCR depend on X/Y_INCR › Use Case: Transfer SCB reception data in FIFO (2/2) P-DMA – Handling multiple FIFO data as one data 3 Interrupt to CPU –1 Activate P-DMA by receiving a completion trigger Descriptor 0 –2 Repeat data transfer from Destination SCB SRC_ADDR = FIFO Address SRC_ADDR to DST_ADDR 4 X_COUNT X_DST_INCR by X_COUNT 2nd +0 +1 +2 +3 Reception d15 d14 d13 d12 d11 d10 d9 d8 DST_ADDR d12 d13 d14 d15

–3 Activate P-DMA by receiving a d8 d9 d10 d11 Y_DST_INCR completion trigger, when the Y_COUNT+1 d4 d5 d6 d7 d0 d1 d2 d3 second data is received SRC_INCR = 0 –4 Repeat data transfer from SRC_ADDR to DST_ADDR by X_COUNT

+10 Next Descriptor Pointer › CRC Transfer Hint Bar Y(Outer) Loop Control – Execute the CRC calculation of the specified area +0c X(Inner) Loop Control – CRC-32, CRC-16, CRC-16-CCITT Review TRM section 7.1.3 +08 Destination Address and Register TRM for – Byte ordering/remainder bit reverse additional details +04 Source Address – Set CRC seed value +00 Descriptor Control – CRC result is stored to the destination address – This mode does not transfer data P-DMA CPU 1 3 5 › Use Case: Initial CRC check for program data CRC in Flash Calculation Source Destination 6 –1 Activate P-DMA with software trigger Flash Memory 2 4 –2 Transfer data from SRC_ADDR COUNT Code Area –3 CRC calculation (code area) SRC_ADDR DST_ADDR Result –4 Transfer CRC result to DST_ADDR –5 Generate interrupt to CPU SRC_SIZE: 32-bit DATA_SIZE: 32-bit DST_SIZE: 32-bit –6 The CPU checks the CRC result with the expected value › Advantage: Performs high-speed CRC calculation without a CPU

› Input Trigger Hint Bar – Four types of input trigger action Review TRM sections 7.1.3 – Type 0: Executed by a single transfer and 7.2.3 and Register TRM for additional details – Type 1: Executed by a single 1D transfer – Type 2: Executed by the current descriptor – Type 3: Executed by a descriptor list › Output Trigger/Interrupt – Four types of output trigger/interrupt generation – Type 0: Generated by a single transfer – Type 1: Generated by single 1D transfer – Type 2: Generated by the current descriptor – Type 3: Generated by descriptor list › Input Trigger, Output Trigger, and Interrupt can be set individually

› Example of trigger action – Descriptor input trigger Type 0: Executes a single transfer – Descriptor output trigger/interrupt Type 0: Generated by a single transfer

Execute Single Transfer || || Trigger Input || || || || Single Single Single Single Single Single || || Data Transfer || || || ||

|| || Trigger Output/ || || Interrupt || ||

Transfer Status 1D

2D ( =Descriptor 0) 1D

› Example of trigger action – Descriptor input trigger Type 1: Executed by a single 1D transfer – Descriptor output trigger/interrupt Type 1: Generated by a single 1D transfer

Execute 1D Transfer || || Trigger Input || || || || Single Single End of 1D Single Single End of 1D || || Data Transfer || || || ||

|| || Trigger Output/ || || Interrupt || ||

Transfer Status 1D

2D ( =Descriptor 0) 1D

› Example of trigger action – Descriptor input trigger Type 2: Executed by the current descriptor – Descriptor output trigger/interrupt Type 2: Generated by the current descriptor Execute Descriptor Transfer || || || Trigger Input || || || || || || Single Single End of 1D Transfer End of Descriptor 0 Single Single End of Descriptor 1 || || || Data Transfer || || || || || ||

|| || || Trigger Output/ || || || Interrupt || || ||

Transfer Status 1D 2D ( =Descriptor 1)

Descriptor Chaining

1D 2D ( =Descriptor 0)

Execute Descriptor Transfer Descriptor Trigger Types (5/5)

› Example of trigger action – Descriptor input trigger Type 3: Executed by a descriptor list – Descriptor output trigger/interrupt Type 3: Generated by a descriptor list Execute Descriptor Transfer || || || Trigger Input || || || || || || Single Single End of 1D Transfer End of Descriptor 0 Single Single End of Descriptor 1 || || || Data Transfer || || || || || ||

|| || || Trigger Output/ || || || Interrupt || || ||

Transfer Status 1D 2D ( =Descriptor 1)

Descriptor Chaining

1D 2D ( =Descriptor 0)

› Trigger Multiplexers Hint Bar – Connect each channel to one specific system trigger Review TRM section 7.2.6 – Software (SW) system triggers1 and chapter 29 for additional details – Trigger output (tr_out) – Each trigger output can be used as its own active trigger using trigger multiplexers – They can be used to trigger different transfers as input triggers for other channels

Trigger M-DMA Multiplexer Channel logic tr_in[] tr_in[0] Pending Trigger Data Transfer Software triggers Engine Channel State tr_out[] Priority Decoder tr_in[1] Channel Logic

tr_in[CH_NR-1] Channel Logic

Interrupt Bus Master Interrupts[] Bus Slave I/F MMIO Registers Logic I/F

Memory 1 This is different from P-DMA.

› Pending Triggers Hint Bar – Keeps track of activated triggers by storing channel triggers Review TRM section 7.2.6 – Manages multiple pending channel triggers for additional details › Priority Decoder – Determines the highest priority channel of transfer request from each transfer engine1 – Has four priority levels – Performs round-robin arbitration within the same priority group

Trigger M-DMA Multiplexer Channel Logic tr_in[] tr_in[0] Pending Trigger Data Transfer Software triggers Engine Channel State tr_out[] Priority Decoder tr_in[1] Channel Logic

tr_in[CH_NR-1] Channel Logic

Interrupt Bus Master Interrupts[] Bus Slave I/F MMIO Registers Logic I/F

1 This is different from P-DMA. Memory

› Data Transfer Engine Hint Bar – Dedicated engine for each channel1 Review TRM section 7.2.6 – Transfers data from source to destination according to descriptor for additional details – Reads channel descriptor from memory – Generates the trigger out to trigger multiplexers

Trigger M-DMA Multiplexer Channel Logic tr_in[] tr_in[0] Pending Trigger Data Transfer Software triggers Engine Channel State tr_out[] Priority Decoder tr_in[1] Channel Logic

tr_in[CH_NR-1] Channel Logic

Interrupt Bus Master Interrupts[] Bus Slave I/F MMIO Registers Logic I/F

Memory

1 This is different from P-DMA.

› Descriptor Trigger M-DMA Multiplexer Hint Bar Channel logic tr_in[] tr_in[0] Pending – Stored in memory Trigger Data Transfer Software triggers Engine Channel State tr_out[] Review TRM section 7.2.6 – Descriptor chaining Priority and Register TRM for Decoder tr_in[1] Channel Logic additional details – Descriptor types tr_in[CH_NR-1] Channel Logic Descriptor size is different – Single transfer from P-DMA, but the

Interrupt Bus Master setting items are the same – 1D transfer Interrupts[] Bus Slave I/F MMIO Registers Logic I/F – 2D transfer System RAM is used as a memory to store the – Memory copy1 descriptor – Scatter1 Memory – Descriptor structure +1c Next Descriptor Pointer +18 Y(Outer) Loop Control – Descriptor control: +14 Y(Outer) Loop Count Trigger type, transfer size, descriptor type +10 X(Inner) Loop Control – Source address/destination address +0c X(Inner) Loop Count +08 Destination Address – X(Inner) loop/Y(Outer) loop control +04 Source Address – Next descriptor pointer Descriptor Pointer +00 Descriptor Control – The descriptor pointer position for each channel is stored in the register

1 This is different from P-DMA.

+10 Next Descriptor Pointer › Memory copy Y(Outer) Loop Control Hint Bar – One-dimensional “for loop” transfer Y(Outer) Loop Count X(Inner) Loop Control Review TRM section 7.2.3 – Uses five-word descriptor1 and Register TRM for +0c X(Inner) Loop Count additional details – Transfer example: +08 Destination Address for (X_IDX =0; X_IDX <= X_COUNT; X_IDX+){ +04 Source Address DST_ADDR[IDX] = SRC_ADDR[IDX] +00 Descriptor Control } › Use Case: Interrupt vector copy M-DMA or program copy for RAM execution 1 3 –1 Activate M-DMA by software trigger

–2 Copy the data from Flash to SRAM Source 2 Destination Flash SRAM –3 Generate interrupt to CPU COUNT Copy Area Copy Data SRC_ADDR DST_ADDR

SRC_SIZE: 32-bit DATA_SIZE: 32-bit DST_SIZE: 32-bit

1 SRC_SIZE, DST_SIZE, and DATA_SIZE fields are not used for memory copy. Memory copy transfers the number of bytes specified by X Loop Count in the optimum size. For example, when “Source Address” = 0x08000001, “X Loop Count” = 10, first transfer size is 8-bit, second transfer size is 16-bit, and third transfer size is 32-bit.

002-22194 *E 2020-12-07 Copyright © Infineon Technologies AG 2020. All rights reserved. 27 Descriptor Type (2/3) +0c Next Descriptor Pointer Y(Outer) Loop Control › Scatter Y(Outer) Loop Count Hint Bar – Writes a set of 32-bit data elements, which has X(Inner) Loop Control addresses “scattered” around +08 X(Inner) Loop Count Review TRM section 7.2.3 Destination Address and Register TRM for – Writes the specified data to the specified address additional details +04 Source Address 1 – Uses four-word descriptors +00 Descriptor Control – Transfer example: for (X_IDX =0; X_IDX <= X_COUNT; X_IDX +=2){ address = SRC_ADDR[IDX] data = SRC_ADDR[IDX+1] M-DMA Source Destination *address = data Memory Memory

} +20 Data D +1c Data D Address +1c +18 Data C +14 Data B Address +08 +10 COUNT Data B +0c Address +14 +08 Data C Data A +04 SRC_ADDR Address +00 Address +00 Data A

1 SRC_SIZE, DST_SIZE must be set to word (32-bit) for scatter. SRC_SIZE: 32-bit DATA_SIZE: 32-bit DST_SIZE: 32-bit

M-DMA 2 4 Destination › Use Case: Quick initial setting or Source Peripheral x 1 setting change of peripheral registers Memory +10 Data 2x +0c without CPU Data 2x 3 +08 –1 Write the address and data to be set Peripheral x Base Adr +10 +04 Data 1x in the peripheral to the memory Peripheral x Base Adr +00 Data 1x Peripheral x Base Adr +00 –2 Activate M-DMA using software trigger ・・・・ Data 3b –3 Write the data from the memory Peripheral B to peripheral registers Peripheral B Base Adr +0c Data 2b –4 Generate an interrupt to CPU when +0c Data 3b COUNT Peripheral B Base Adr +08 +08 Data 2b the transfer is complete Data 1b +04 Peripheral B Base Adr +00 Peripheral B Base Adr +00 Data 1b Data 3a

Peripheral A Base Adr + 08

Data 2a Peripheral A

Peripheral A Base Adr +04 +08 Data 3a

Data 1a +04 Data 2a SRC_ADD Peripheral A Base Adr +00 Peripheral A Base Adr +00 Data 1a

SRC_SIZE: 32-bit DATA_SIZE: 32-bit DST_SIZE: 32-bit

Revision ECN Submission Description of Change Date ** 6136162 04/17/2018 Initial release *A 6351891 16/10/2018 Added slide 2. Updated slides 3, 4, and 5. Added slide 29: Descriptor Type (3/3) Updated figures on slides 7, 9-11, and 23-26 *B 6633414 7/22/2019 Updated slide 2-4, 9. Added slide 5. *C 6825576 03/06/2020 Updated slide 12, 15,16 *D 6952165 08/20/2020 Update slide 8, 27, 28 *E 7039675 11/26/2020 Updated page 2. Merged page 3 for Traveo II Body Controller Entry.