Cpre 281 1 CMOS Realization of a NAND Gate CMOS Realization of a and Gate

Voltage Representation NMOS Transistor as a Switch • MOSFET: Metal Oxide Semiconductor Field-Effect Transistor of Logic Values V DD • NMOS: n-channel MOSFET by Voltage Levels Logic value 1 x = "low" x = "high" (Positive logic V (a) A simple switch controlled by the input x system) 1,min Gate Undefined VG Source Drain V 0,max Substrate (Body) VS VD

V SS (Gnd) 1 2

PMOS Transistor as a Switch Structure of a CMOS Circuit V • PMOS: p-channel MOSFET •CMOS: DD Complementary MOS Technology x = "high" x = "low"

(a) A switch with the opposite behavior of previous slide Pull-up network PMOS (PUN)

Gate V G V f

Drain Source V V V S D x 1 V DD Substrate (Body) Pull-down network NMOS (c) Simplified symbol for (PDN) V (b) PMOS transistor an PMOS transistor x n

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CMOS Realization of a NOT Gate CMOS Realization of a NOR Gate V DD

VDD

V x 1 T 1

V V x Vf x 2 T 2 x T T f 1 2 x x T T T T f T2 1 2 1 2 3 4 V f 0 onoff 1 1 off on 0 0 0 on on off off 1 T 3 T 4 0 1 on off off on 0 off on on off (a) Circuit (b) Truth table and transistor states 1 0 0 1 1 off off on on 0

(a) Circuit (b) Truth table and transistor states

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CprE 281 1 CMOS Realization of a NAND Gate CMOS Realization of a AND Gate

V DD V DD V DD

T 1 T 2

V f V f

V x x x T T T T f 1 T 3 1 2 1 2 3 4 V x 1 0 0 on on off off 1 0 1 on off off on 1 V x 2 T 4 1 0 off on on off 1 V x 1 1 off off on on 0 2

(a) Circuit (b) Truth table and transistor states

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Implement Compound Function Directly Types of Integrated Circuits (ICs) V • All variables need to DD • Standard Chips appear in their • Programmable Logic Devices (PLDs): complemented form. – Programmable Logic Array (PLA) • PUN can be derived by – Programmable Array Logic (PAL) looking at f directly. – Complex Programmable Logic Device (CPLD) • PDN can be derived by – Field-Programmable Gate Array (FPGA) looking at f’. V f • Non-Programmable Devices: V – Custom Design • Example: x 1 – Standard-Cell Design f = x1’ + x2’ x3’ • Application Specific Integrated Circuit (ASIC)

V x f’ = x1 (x2 + x3) 2 – Gate-Array Design V x 3

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Standard Chips Implementation of f = x1x2 + x2’x3 • A collection of specific gates in a chip VDD • Popular until mid-80s • 7400-Series Standard Chips

– 7404 : NOT gates 7404

VDD

Gnd

– 7408 : AND gates 7408 7432 – 7432 : OR gates – 74244 : Tri-State Buffers x1 x2 x3 f 11 12

CprE 281 2 Programmable Logic Array (PLA) Gate-Level Diagram of a PLA x1 x2 x3 x1 x2 xn

Programmable connections

OR plane Input buffers P and 1 inverters

P2 x1 x1 xn xn

P1 P3

AND plane OR plane Pk P4

AND plane

f1 fm 13 f1 f2 14

Customary Schematic for PLA Programmable Array Logic (PAL) x x x 1 2 3 x1 x2 x3

OR plane

P1 P1

P2 f1 P2

P3 P3

P 4 f2 P4

AND plane AND plane f f 1 2 15 16

x Field-Programmable Gate Array (FPGA) Lookup Table 1 0/1 Logic block Interconnection switches (LUT) x x 0/1 1 2 f 1 I/O block f 0/1 0 0 1 0 1 0 0/1 1 0 0 x 2 1 1 1

(a) Circuit for a two-input LUT (b) f 1 = x 1 x 2 + x 1 x 2 I/ O ck block block o

x 1 I/O bl 1

0 f 1 0

1 x I/O block 2

CprE 281 3