Questions? ESE 570: Digital Integrated Circuits and VLSI Fundamentals ! Use chat panel to type question " Scroll to bottom of zoom window and click “chat” button Lec 1: September 2, 2020 ! Or just type “I have a question” and I will call on Introduction and Overview you to unmute
" Just like raising your hand in person
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Your First Priority Advice for Remote Learning Success
! Your first priority is your health ! Attend lecture in real time and stay on schedule " Rewatch recorded lectures, attend virtual office hours " You should abide by all health guidelines " We are here to help, but you need to let us know you need help " Wear a mask ! " Wash your hands Start homework early! " " Don’t touch your face Cadence is tricky, takes time to learn how to use it efficiently " " Maintain social physical distancing Will give advice in lectures, but it won’t help if you haven’t started
" Virtual social interaction is encouraged!
" Stay home if you’re sick ! Useful study habits reference:
" Part of your health is your mental and emotional health " https://lsa.umich.edu/content/dam/rll-assets/rll-docs/ Study%20Habits.pdf " See https://caps.wellness.upenn.edu/selfhelp/ for help
" For more: https://coronavirus.upenn.edu/content/resources
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I want to hear from you… Where I come from
! Accessibility Survey in Canvas ! Analog VLSI Circuit Design (analog design) " Submit by Friday for full HW credit ! Convex Optimization (system design)
! Will you be in a different time zone? " System Hierarchical Optimization ! Will you have trouble seeing or hearing video ! Biomedical Electronics lectures? ! Biometric Data Acquisition (signal processing)
! Are there any other accessibility issues I should " Compressive Sampling know about? ! ADC Design (mixed signal)
! Low Energy Circuits (digital design)
! Let me know any concerns -- I will do everything I " Adiabatic Charging can to ensure you achieve the learning objectives
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1 Where I come from Lecture Outline
! Analog VLSI Circuit Design (analog design) ! Course Topics Overview ! Convex Optimization (system design) ! Learning Objectives " System Hierarchical Optimization ! Course Structure
! Biomedical Electronics ! Course Policies ! Biometric Data Acquisition (signal processing) ! Course Content " Compressive Sampling ! Industry Trends ! ADC Design (mixed signal) ! Design Example ! Low Energy Circuits (digital design)
" Adiabatic Charging CIRCUITS, CIRCUITS, CIRCUITS
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Course Topics Overview Learning Objectives
Course Topics ! Apply principles of hierarchical digital CMOS VLSI, from the transistor up to the system level, to the understanding of CMOS circuits and systems that System-Related Issues are suitable for CMOS fabrication. Reliability Design Manufacturability ! Apply the models for state-of-the-art(ish) VLSI components, fabrication Testability steps, hierarchical design flow and semiconductor business economics to judge μPs, Custom Logic the manufacturability of a design and estimate its manufacturing costs. VLSI Sub-systems Course Progression ! Design digital circuits that are manufacturable in CMOS. Regular Structures ! Design simulated experiments using Cadence to verify the integrity of a ROMs, RAMs, PLAs Implementation/ Fabrication CMOS circuit and its layout. Logic Circuits, Gates, Latches ! Apply the Cadence VLSI CAD tool suite layout digital circuits for CMOS fabrication and verify said circuits with layout parasitic elements. Two Transistor Logic Circuits (Inverters) Static Dynamic ! Apply course knowledge and the Cadence VLSI CAD tools in a team based capstone design project that involves much the same design flow they would MOS Transistor, Capacitor and Interconnect Models encounter in a semiconductor design industrial setting. Capstone project is presented in a formal report due at the end of the semester. CMOS Fabrication
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Learning Objectives What is Cadence?
! In other words… ! Industry standard CAD software for IC design ! Schematic capture
" Create netlist (software code describing schematic)
! SPECTRE/SPICE simulator ! Design in CADENCE* " Mathematical solver of differential equations describing fundamentals (Ex. KCL/KVL, Ohm’s law, etc.) ! Design physical mask layers used for fabrication
! Extract parasitics from physical layout for simulation *All the way to layout/manufacturability
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2 Schematic Capture Schematic Capture
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Layout in Cadence Course Structure
! MW Lecture, 4:30-6:00pm in Zoom
" Start 5 minutes after, end 5 minutes early (~75-80min)
" Recordings posted in Canvas afterwards ! Website (http://www.seas.upenn.edu/~ese570/)
" Course calendar is used for all handouts (lectures slides, assignments, and readings)
" Canvas used for assignment submission and grades
" Piazza used for announcements and discussions
" Use for Zoom links for lectures and OHs
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Course Structure Additional TAs
! Course Staff (complete info on course website) ! Instructor: Tania Khanna
" Office hours – WF 1-3 pm or by appointment
" See Piazza for OH Zoom link
" Email: [email protected]
" Best way to reach me
! TAs:
" Yuanlong Xiao
" Office hours: T 3-4:40pm, Th 9-10:30am
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3 Course Structure Course Structure
! Lectures ! Cadence
" Statistically speaking, you will do better if you come to " Technology: AMI .6u C5N (3M, 2P, high-res)
lecture " Schematic simulation (SPECTRE simulator)
" Better if interactive, everyone engaged " Design, analysis and test
" Asking and answering questions " Layout and verification " Actively thinking about material " Analog extracted simulation ! Textbook " Verilog
" CMOS Digital Integrated Circuits Analysis and Design, " HW 8 For Extra Credit Kang, Leblebici, and Kim, 4th edition
" Class will follow this text structure
" Additional useful texts on course website
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Course Structure - Assignments/Exams Course Policies
! Homework – 1 week long (8 total) [30%] See web page for full details " Due Fridays at midnight ! Turn homework in Canvas
" HW 1 out now " Anything handwritten/drawn must be clearly legible
! Projects – 2+ weeks long [50%] " Submit CAD generated figures, graphs, results when
" Design oriented specified
" Projects " Late Policy – allowed 4 late days for whole semester
" " Two projects combine to design and layout combinational logic Can only use a max of one day on projects block used in FPGAs ! Individual work " Proj 1 – 20%, Proj 2 – 30% " CAD drawings, simulations, analysis, writeups ! Midterm exam [20%] " May discuss strategies, but acknowledge help
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Course Content Course Content
! Introduction ! Sequential Logic ! Fabrication ! Dynamic Logic ! MOS Transistor Theory and ! VLSI design and Scaling
Models ! Memory Design
! MOS Models and IV ! I/O Circuits and Inductive characteristics Noise ! Inverters: Static Characteristics ! CLK Generation and Performance ! Transmission Lines ! Inverters: Dynamic Characteristics and Performance ! Combinational Logic Types (CMOS, Ratioed, Pass) and Performance
https://www.seas.upenn.edu/~ese570/fall2020/syllabus.html
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4 Microprocessor Trans Count 16-Core1971-2015 SPARC T3 6-Core6-Core i7 i7 10-Core Xenon IBM 4-Core z196 2-Core Itanium 2 IBM 8-Core POWER7 4-Core Itanium Tukwilla Industry Trends AMD K10 AMD 6-Core Opteron Curve shows 4-Core i7 2400
transistor count AMD K8 doubling every Pentium 4 AMD K7 two years Pentium III Pentium II Pentium AMD K5 80486
80386 80286 Mot 68000 80186 8086 Mot 6800 8080 Zilog Z80 8006 MOS 6502 2015: Oracle SPARC M7, 20 nm CMOS, 4004 32-Core, 10B 3-D FinFET transistors.
Kenneth R. Laker, University of Pennsylvania, updated 2015 Penn ESE 570 Fall 2020 - Khanna 26 Penn20Jan15 ESE 570 Fall 2020 - Khanna 27
Intel Cost Scaling Trend – “Minimum” Feature Size vs. Year
Process Node/”Minimum” Feature 100 µm
10 µm Integrated Circuit History
1 µm ITRS Roadmap 0.18 µm in 1999 0.1 µm
10 nm Transition Region “Distant” Future?
1 nm Quantum Devices
Atomic Dimensions 0.1 nm Year 1960 1980 2000 2020 2040
http://www.anandtech.com/show/8367/intels-14nm-technology- “Minimum” Feature Measure = line/gate conductor width or half-pitch (adjacent in-detail 1st metal layer lines or adjacent transistor gates) Penn ESE 570 Fall 2020 - Khanna 28 Penn ESE 570 Fall 2020 - Khanna 29
More Moore # Scaling 22nm 3D FinFET Transistor
! Geometrical Scaling
" continued shrinking of horizontal and vertical physical feature sizes ! Equivalent Scaling
" 3-dimensional device structure improvements and new materials that affect the electrical performance of the chip even if no geometrical scaling
! Design Equivalent Scaling High-k Tri-Gate transistors with multiple " design technologies that enable high performance, low gate fins connected together power, high reliability, low cost, and high design dielectric increases total drive strength for productivity even if neither geometrical nor equivalent higher performance scaling can be used http://download.intel.com/newsroom/kits/22nm/pdfs/22nm- Penn ESE 570 Fall 2020 - Khanna 30 Penn ESE 570 Fall 2020 - Khanna Details_Presentation.pdf 31
5 ITRS 2.0 Report 2015 BUT…
! “After 2021, the report forecasts, it will no longer be economically desirable for companies to continue traditional transistor miniaturization in microprocessors.”
Source:https://newsroom.intel.com/newsroom/wp-content/uploads/sites/11/2020/09/mark-bohr-on-continuing-moores-law.pdf
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BUT… More than Moore # Functional Diversification
! Interacting with the outside world
" Electromagnetic/Optical
" Radio-frequency domain up to the THz range
" Optical domain from the infrared to the near ultraviolet
" Hard radiation (EUV, X-ray, γ-ray)
" Mechanical parameters (sensors/actuators)
" MEMS/NEMS position, speed, acceleration, rotation, pressure, stress, etc.
" Chemical composition (sensors/actuators)
" Biological parameters (sensors/actuators)
! Power/Energy Source:https://newsroom.intel.com/newsroom/wp-content/uploads/sites/11/2020/09/mark-bohr-on-continuing-moores-law.pdf " Integration of renewable sources, Energy storage, Smart metering, Efficient consumption Penn ESE 570 Fall 2020 - Khanna 34 Penn ESE 570 Fall 2020 - Khanna 35
More-than-Moore “More-than-Moore”
! Components Complement Digital Processing/
Storage Elements in an Integrated System Scaling Scaling
“More-than-Moore”, International Road Map (IRC) White Paper, 2011. International Technology Roadmap for Semiconductors
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6 MicroImplant: An Electronic Platform for Semiconductor System Integration – More Minimally Invasive Sensory Monitors Than Moore's Law
1010 1010
9 109 SOP law for system integration. 10 As components shrink and boards all but Transistors/cm 108 108 disappear, component density will double Components/cm
107 every year or so. 107
106 106
105 105 2
104 104 2 System-
3 in-package 3 10 Multichip System- 10 (SIP) on-package 2 Module 2 10 (SOP) 10
10 10 1970 1980 1990 2000 2010 2020 R. Tummala, “Moore's Law Meets Its Match”, IEEE Spectrum, June, 2006 Penn ESE 570 Fall 2020 - Khanna 38 Penn ESE 570 Fall 2020 - Khanna 39
Improvement Trends for VLSI SoCs Enabled Societal Needs by Geometrical and Equivalent Scaling
! TRENDS: ! CONSEQUENCES: ! Higher Integration level ! Higher Speed
" exponentially increased " CPU clock rate at multiple number of components/ GHz + parallel processing. transistors per chip/package. ! Increased Compactness & ! Performance Scaling less weight
" combination of Geometrical " increasing (shrinking of dimensions) system integration. and Equivalent (innovation) Scaling. ! Lower Power " Decreasing energy ! System implementation requirement per function. " SoC + increased use of SiP - > SOP ! Lower Cost " Decreasing cost per function. Penn ESE 570 Fall 2020 - Khanna 40 Penn ESE 570 Fall 2020 - Khanna 41
Trends in Practice at ISSCC (HW 1)
Design Example
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7 VLSI Design Cycle or Flow VLSI Design Cycle or Flow
Functional Specification:
Verilog/SPICE Verilog/SPICE
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Illustrative Circuit Design Example: VLSI Design Illustrative Circuit Design Example: System Requirements
! 8-bit Ripple Adder
Functional Specification:
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Illustrative Circuit Design Example: Architecture Definition Illustrative Circuit Design Example: Logic Design
! Gate Level Schematic of One-Bit Full Adder Circuit
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8 VLSI Design Cycle or Flow Illustrative Circuit Design Example: System Requirements
Verilog/SPICE Design Specifications: Functional Specification:
Design Specifications (in 0.8 twin-well CMOS):
1. Propagation Delay Times of SUM and CARRY_Out signals: ≤ 1.2 ns 2. Rise and Fall Times of SUM and CARRY_Out signals: ≤ 1.2 ns 3. Circuit Die Area: ≤ 1500 um2
4. Dynamic Power Dissipation (@ VDD = 5 V and f max = 20 MHz): ≤ 1 mW
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Illustrative Circuit Design Example: VLSI Design Illustrative Circuit Design Example: VLSI Design and Layout
! Transistor Level Schematic of One-Bit Full Adder Circuit
COUT SUMOUT N1 N2
COU T
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Illustrative Circuit Design Example: VLSI Design and Layout Post Layout Simulation (Analog extracted)
! Initial Layout of One-Bit Full Adder Circuit
Schematic COU to layout T
≤ 1500 um2
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9 Post Layout Simulation (Analog extracted) Illustrative Circuit Design Example: Design Verification
Layout to schematic Spec NOT met
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Admin
! Find web, get text, assigned reading…
" http://www.seas.upenn.edu/~ese570
" https://piazza.com/upenn/Fall2020/ese570/
" https://canvas.upenn.edu/
! Submit Accessibility Survey ! HW 1 posted now
" Due next week Sept 11
! If you’re outside the US email me ASAP to test access to Cadence
! Remaining Questions?
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