DOCSLIB.ORG

Sunway Taihulight Supercomputer Makes Its Appearance Jack Dongarra

Total Page：16

File Type：pdf, Size：1020Kb

Download full-text PDF Read full-text
Sunway Taihulight Supercomputer Makes Its Appearance Jack Dongarra RESEARCH HIGHLIGHTS Dongarra 265 The OX-ZEO process, with its super- Mingyuan He1,2 REFERENCE selectivity, low H /CO ratio in the syn- 1School of Chemistry and Molecular Engineering, 2 1. Jiao F, Li J and Pan X et al. Science 2016; 351: gas feedstock and rather mild operating East China Normal University, China 1065–8. conditions, is a very attractive system and 2Research Institute of Petroleum Processing, National Science Review shows promise with regard to eventual in- SINOPEC, China 3: 264–265, 2016 dustrial applications. E-mail: [email protected] doi: 10.1093/nsr/nww038 COMPUTER SCIENCE Sunway TaihuLight supercomputer makes its appearance Jack Dongarra The Sunway TaihuLight System1 [ ]is of data from memory on the SW26010 four Management Processing Elements very impressive with over 10 million is 22.4 Flops(DP)/Byte transfer, which (MPEs), four Computing Processing El- cores and a peak performance of just over shows an imbalance or an overcapacity of ements (CPEs) (a total of 260 cores), 125 Pflop/s. The Top500 list has the floating point operations per data trans- four memory controllers (MC), and a Sunway TaihuLight as the fastest com- fer from memory. By comparison the In- Network on Chip connected to the Sys- puter. The Sunway is almost three times tel Knights Landing processor with 7.2 tem Interface. Each of the four MPE, (2.75 times) as fast and three times as ef- Flops(DP)/Byte transfer. So for many CPE, and MC have access to 8 GB of ficient as the system it displaces inthe ‘real’ applications the performance on the DDR3 memory, see Fig. 1.Thereare number one spot. In fact, the sum of TaihuLight will be nowhere near the peak 40 960 nodes in the complete system. the performance for computers in posi- performance rate. Also the primary mem- The Sunway TaihuLight System is us- tion 2 through 7 is just barely greater ory for this system is on low side at 1.3 PB ing Sunway Raise OS 2.0.5 based on than the performance of the Sunway sys- (Tianhe-2 has 1.4 PB and Cray Titan sys- Linux as the operating system. The basic tem. The HPL Benchmark results at93 tem at Oak Ridge National Laboratory software stack for the many-core proces- Pflop/s or 74% of theoretical peak per- has .71 PB). sor includes basic compiler components, formance is impressive, with an efficiency The Sunway TaihuLight system, such as C/C++ and Fortran compilers, of 6 Gflops per Watt; this is the high- based on a homegrown processor, an automatic vectorization tool, and basic est efficiency of all the top computers. demonstrates the significant progress math libraries. There is also the Sunway The HPCG benchmark performance at that China has made in the domain of OpenACC, a customized parallel compi- only 0.3% of peak performance shows the designing and manufacturing large-scale lation tool that supports OpenACC 2.0 weakness of the Sunway TaihuLight ar- computation systems. A computer node syntax and targets the SW26010 many- chitecture with slow memory and mod- of this machine is based on one many- core processor. est interconnect performance. The ra- core processor chip called the SW26010 The Gordon Bell Prize [2]isawarded tio of floating point operations per byte processor. Each processor is composed of each year to recognize outstanding Figure 1. Basic layout of a node, the SW26010. 266 Natl Sci Rev, 2016, Vol. 3, No. 3 RESEARCH HIGHLIGHTS achievement in high-performance com- will develop an exascale computer during puting. The purpose of the award isto the 13th Five-Year-Plan period (2016– track the progress over time of parallel 2020). It is clear that they are on a path computing, with particular emphasis on which will take them to an exascale com- rewarding innovation in applying high- puter by 2020, well ahead of the US plans performance computing to applications for reaching exascale by 2023. in science, engineering, and large-scale data analytics. Financial support of the Jack Dongarra $10 000 award is provided by Gordon Innovative Computing Laboratory, EECS Bell, a pioneer in high-performance and Figure 2. Distribution of supercomputers. Department, University of Tennessee, USA parallel computing. There are three sub- E-mail: [email protected] missions which are finalists for the Gor- running real applications and not just a don Bell Award at SC16 that are based ‘stunt machine’. on the new Sunway TaihuLight system. China has made a big push into These three applications are as follows: high-performance computing. In 2001, REFERENCES (1) a fully implicit non-hydrostatic dy- there were no supercomputers listed on 1. Fu HH, Liao JF and Yang JZ et al. Sci China Inf namic solver for cloud-resolving atmo- the Top500 list [3] in China. Today Sci 2016; 59: 072001; doi:10.1007/s11432-016- spheric simulation; (2) a highly effective China has 167 systems on the June 2016 5588-7. global surface wave numerical simulation Top500 list compared to 165 systems 2. Gordon Bell Prize. https://en.wikipedia.org/ with ultrahigh resolution; and (3) large- in the USA, see Fig. 2. China has one- wiki/Gordon Bell Prize scale phase-field simulation for coars- third of the systems, while the num- 3. Top500 List. https://www.top500.org/lists/2016 ening dynamics based on Cahn-Hilliard ber of systems in the USA has fallen to /06/ equation with degenerated mobility. The the lowest point since the TOP500 list fact that there are sizeable applications was created. No other nation has seen and Gordon Bell contender applications such rapid growth. According to the Chi- National Science Review running on the system is impressive and nese national plan for the next generation 3: 265–266, 2016 shows that the system is capable of of high-performance computers, China doi: 10.1093/nsr/nww044.
Load more

Recommended publications
  • Interconnect Your Future Enabling the Best Datacenter Return on Investment
    Interconnect Your Future Enabling the Best Datacenter Return on Investment TOP500 Supercomputers, November 2016 Mellanox Accelerates The World’s Fastest Supercomputers . Accelerates the #1 Supercomputer . 39% of Overall TOP500 Systems (194 Systems) . InfiniBand Connects 65% of the TOP500 HPC Platforms . InfiniBand Connects 46% of the Total Petascale Systems . Connects All of 40G Ethernet Systems . Connects The First 100G Ethernet System on The List (Mellanox End-to-End) . Chosen for 65 End-User TOP500 HPC Projects in 2016, 3.6X Higher versus Omni-Path, 5X Higher versus Cray Aries InfiniBand is the Interconnect of Choice for HPC Infrastructures Enabling Machine Learning, High-Performance, Web 2.0, Cloud, Storage, Big Data Applications © 2016 Mellanox Technologies 2 Mellanox Connects the World’s Fastest Supercomputer National Supercomputing Center in Wuxi, China #1 on the TOP500 List . 93 Petaflop performance, 3X higher versus #2 on the TOP500 . 41K nodes, 10 million cores, 256 cores per CPU . Mellanox adapter and switch solutions * Source: “Report on the Sunway TaihuLight System”, Jack Dongarra (University of Tennessee) , June 20, 2016 (Tech Report UT-EECS-16-742) © 2016 Mellanox Technologies 3 Mellanox In the TOP500 . Connects the world fastest supercomputer, 93 Petaflops, 41 thousand nodes, and more than 10 million CPU cores . Fastest interconnect solution, 100Gb/s throughput, 200 million messages per second, 0.6usec end-to-end latency . Broadest adoption in HPC platforms , connects 65% of the HPC platforms, and 39% of the overall TOP500 systems . Preferred solution for Petascale systems, Connects 46% of the Petascale systems on the TOP500 list . Connects all the 40G Ethernet systems and the first 100G Ethernet system on the list (Mellanox end-to-end) .
    [Show full text]
  • The Sunway Taihulight Supercomputer: System and Applications
    SCIENCE CHINA Information Sciences . RESEARCH PAPER . July 2016, Vol. 59 072001:1–072001:16 doi: 10.1007/s11432-016-5588-7 The Sunway TaihuLight supercomputer: system and applications Haohuan FU1,3 , Junfeng LIAO1,2,3 , Jinzhe YANG2, Lanning WANG4 , Zhenya SONG6 , Xiaomeng HUANG1,3 , Chao YANG5, Wei XUE1,2,3 , Fangfang LIU5 , Fangli QIAO6 , Wei ZHAO6 , Xunqiang YIN6 , Chaofeng HOU7 , Chenglong ZHANG7, Wei GE7 , Jian ZHANG8, Yangang WANG8, Chunbo ZHOU8 & Guangwen YANG1,2,3* 1Ministry of Education Key Laboratory for Earth System Modeling, and Center for Earth System Science, Tsinghua University, Beijing 100084, China; 2Department of Computer Science and Technology, Tsinghua University, Beijing 100084, China; 3National Supercomputing Center in Wuxi, Wuxi 214072, China; 4College of Global Change and Earth System Science, Beijing Normal University, Beijing 100875, China; 5Institute of Software, Chinese Academy of Sciences, Beijing 100190, China; 6First Institute of Oceanography, State Oceanic Administration, Qingdao 266061, China; 7Institute of Process Engineering, Chinese Academy of Sciences, Beijing 100190, China; 8Computer Network Information Center, Chinese Academy of Sciences, Beijing 100190, China Received May 27, 2016; accepted June 11, 2016; published online June 21, 2016 Abstract The Sunway TaihuLight supercomputer is the world’s first system with a peak performance greater than 100 PFlops. In this paper, we provide a detailed introduction to the TaihuLight system. In contrast with other existing heterogeneous supercomputers, which include both CPU processors and PCIe-connected many-core accelerators (NVIDIA GPU or Intel Xeon Phi), the computing power of TaihuLight is provided by a homegrown many-core SW26010 CPU that includes both the management processing elements (MPEs) and computing processing elements (CPEs) in one chip.
    [Show full text]
  • It's a Multi-Core World
    It’s a Multicore World John Urbanic Pittsburgh Supercomputing Center Parallel Computing Scientist Moore's Law abandoned serial programming around 2004 Courtesy Liberty Computer Architecture Research Group Moore’s Law is not to blame. Intel process technology capabilities High Volume Manufacturing 2004 2006 2008 2010 2012 2014 2016 2018 Feature Size 90nm 65nm 45nm 32nm 22nm 16nm 11nm 8nm Integration Capacity (Billions of 2 4 8 16 32 64 128 256 Transistors) Transistor for Influenza Virus 90nm Process Source: CDC 50nm Source: Intel At end of day, we keep using all those new transistors. That Power and Clock Inflection Point in 2004… didn’t get better. Fun fact: At 100+ Watts and <1V, currents are beginning to exceed 100A at the point of load! Source: Kogge and Shalf, IEEE CISE Courtesy Horst Simon, LBNL Not a new problem, just a new scale… CPU Power W) Cray-2 with cooling tower in foreground, circa 1985 And how to get more performance from more transistors with the same power. RULE OF THUMB A 15% Frequency Power Performance Reduction Reduction Reduction Reduction In Voltage 15% 45% 10% Yields SINGLE CORE DUAL CORE Area = 1 Area = 2 Voltage = 1 Voltage = 0.85 Freq = 1 Freq = 0.85 Power = 1 Power = 1 Perf = 1 Perf = ~1.8 Single Socket Parallelism Processor Year Vector Bits SP FLOPs / core / Cores FLOPs/cycle cycle Pentium III 1999 SSE 128 3 1 3 Pentium IV 2001 SSE2 128 4 1 4 Core 2006 SSE3 128 8 2 16 Nehalem 2008 SSE4 128 8 10 80 Sandybridge 2011 AVX 256 16 12 192 Haswell 2013 AVX2 256 32 18 576 KNC 2012 AVX512 512 32 64 2048 KNL 2016 AVX512 512 64 72 4608 Skylake 2017 AVX512 512 96 28 2688 Putting It All Together Prototypical Application: Serial Weather Model CPU MEMORY First Parallel Weather Modeling Algorithm: Richardson in 1917 Courtesy John Burkhardt, Virginia Tech Weather Model: Shared Memory (OpenMP) Core Fortran: !$omp parallel do Core do i = 1, n Core a(i) = b(i) + c(i) enddoCore C/C++: MEMORY #pragma omp parallel for Four meteorologists in the samefor(i=1; room sharingi<=n; i++) the map.
    [Show full text]
  • Challenges in Programming Extreme Scale Systems William Gropp Wgropp.Cs.Illinois.Edu
    1 Challenges in Programming Extreme Scale Systems William Gropp wgropp.cs.illinois.edu Towards Exascale Architectures Figure 1: Core Group for Node (Low Capacity, High Bandwidth) 3D Stacked (High Capacity, Memory Low Bandwidth) DRAM Thin Cores / Accelerators Fat Core NVRAM Fat Core Integrated NIC Core for Off-Chip Coherence Domain Communication Figure 2.1: Abstract Machine Model of an exascale Node Architecture 2.1 Overarching Abstract Machine Model We begin with asingle model that highlights the anticipated key hardware architectural features that may support exascale computing. Figure 2.1 pictorially presents this as a single model, while the next subsections Figure 2: Basic Layout of a Node describe several emergingFrom technology “Abstract themes that characterize moreMachine specific hardware design choices by com- Sunway TaihuLightmercial vendors. In Section 2.2, we describe the most plausible set of realizations of the singleAdapteva model that are Epiphany-V DOE Sierra viable candidates forModels future supercomputing and architectures. Proxy • 1024 RISC June• 19, Heterogeneous2016 2.1.1 Processor 2 • Power 9 with 4 NVIDA It is likely that futureArchitectures exascale machines will feature heterogeneous for nodes composed of a collectionprocessors of more processors (MPE,than a single type of processing element. The so-called fat cores that are found in many contemporary desktop Volta GPU and server processorsExascale characterized by deep pipelines, Computing multiple levels of the memory hierarchy, instruction-level parallelism
    [Show full text]
  • Optimizing High-Resolution Community Earth System
    https://doi.org/10.5194/gmd-2020-18 Preprint. Discussion started: 21 February 2020 c Author(s) 2020. CC BY 4.0 License. Optimizing High-Resolution Community Earth System Model on a Heterogeneous Many-Core Supercomputing Platform (CESM- HR_sw1.0) Shaoqing Zhang1,4,5, Haohuan Fu*2,3,1, Lixin Wu*4,5, Yuxuan Li6, Hong Wang1,4,5, Yunhui Zeng7, Xiaohui 5 Duan3,8, Wubing Wan3, Li Wang7, Yuan Zhuang7, Hongsong Meng3, Kai Xu3,8, Ping Xu3,6, Lin Gan3,6, Zhao Liu3,6, Sihai Wu3, Yuhu Chen9, Haining Yu3, Shupeng Shi3, Lanning Wang3,10, Shiming Xu2, Wei Xue3,6, Weiguo Liu3,8, Qiang Guo7, Jie Zhang7, Guanghui Zhu7, Yang Tu7, Jim Edwards1,11, Allison Baker1,11, Jianlin Yong5, Man Yuan5, Yangyang Yu5, Qiuying Zhang1,12, Zedong Liu9, Mingkui Li1,4,5, Dongning Jia9, Guangwen Yang1,3,6, Zhiqiang Wei9, Jingshan Pan7, Ping Chang1,12, Gokhan 10 Danabasoglu1,11, Stephen Yeager1,11, Nan Rosenbloom 1,11, and Ying Guo7 1 International Laboratory for High-Resolution Earth System Model and Prediction (iHESP), Qingdao, China 2 Ministry of Education Key Lab. for Earth System Modeling, and Department of Earth System Science, Tsinghua University, Beijing, China 15 3 National Supercomputing Center in Wuxi, Wuxi, China 4 Laboratory for Ocean Dynamics and Climate, Qingdao Pilot National Laboratory for Marine Science and Technology, Qingdao, China 5 Key Laboratory of Physical Oceanography, the College of Oceanic and Atmospheric Sciences & Institute for Advanced Ocean Study, Ocean University of China, Qingdao, China 20 6 Department of Computer Science & Technology, Tsinghua
    [Show full text]
  • Eithne: a Framework for Benchmarking Micro-Core Accelerators
    Eithne: A framework for benchmarking micro-core accelerators Maurice Jamieson Nick Brown EPCC EPCC University of Edinburgh University of Edinburgh Edinburgh, UK Edinburgh, UK [email protected] [email protected] Soft-core MFLOPs/core 1 INTRODUCTION MicroBlaze (integer only) 0.120 The free lunch is over and the HPC community is acutely aware of MicroBlaze (floating point) 5.905 the challenges that the end of Moore’s Law and Dennard scaling Table 1: LINPACK performance of the Xilinx MicroBlaze on [4] impose on the implementation of exascale architectures due to the Zynq-7020 @ 100MHz the end of significant generational performance improvements of traditional processor designs, such as x86 [5]. Power consumption and energy efficiency is also a major concern when scaling thecore is the benefit of reduced chip resource usage when configuring count of traditional CPU designs. Therefore, other technologies without hardware floating point support, but there is a 50 times need to be investigated, with micro-cores and FPGAs, which are performance impact on LINPACK due to the software emulation somewhat related, being considered by the community. library required to perform floating point arithmetic. By under- Micro-core architectures look to address this issue by implement- standing the implications of different configuration decisions, the ing a large number of simple cores running in parallel on a single user can make the most appropriate choice, in this case trading off chip and have been used in successful HPC architectures, such how much floating point arithmetic is in their code vs the saving as the Sunway SW26010 of the Sunway TaihuLight (#3 June 2019 in chip resource.
    [Show full text]
  • How Amdahl's Law Restricts Supercomputer Applications
    How Amdahl’s law restricts supercomputer applications and building ever bigger supercomputers J´anos V´egha aUniversity of Miskolc, Hungary Department of Mechanical Engineering and Informatics 3515 Miskolc-University Town, Hungary Abstract This paper reinterprets Amdahl’s law in terms of execution time and applies this simple model to supercomputing. The systematic discussion results in a quantitative measure of computational efficiency of supercomputers and supercomputing applications, explains why supercomputers have different efficiencies when using different benchmarks, and why a new supercomputer intended to be the 1st on the TOP500 list utilizes only 12 % of its processors to achieve the 4th place only. Through separating non-parallelizable contri- bution to fractions according to their origin, Amdahl’s law enables to derive a timeline for supercomputers (quite similar to Moore’s law) and describes why Amdahl’s law limits the size of supercomputers. The paper validates that Amdahl’s 50-years old model (with slight extension) correctly describes the performance limitations of the present supercomputers. Using some simple and reasonable assumptions, absolute performance bound of supercomputers is concluded, furthermore that serious enhancements are still necessary to achieve the exaFLOPS dream value. Keywords: supercomputer, parallelization, performance, scaling, figure of arXiv:1708.01462v2 [cs.DC] 29 Dec 2017 merit, efficiency 1. Introduction Supercomputers do have a quarter of century history for now, see TOP500.org (2016). The number of processors raised exponentially from the initial just-a- few processors, see Dongarra (1992), to several millions, see Fu et al. (2016), Email address: [email protected] (J´anos V´egh) Preprint submitted to Computer Physics Communications August 24, 2018 and increased their computational performance (as well as electric power con- sumption) even more impressively.
    [Show full text]
  • Analysis of Performance Gap Between Openacc and the Native Approach on P100 GPU and SW26010: a Case Study with GTC-P
    Analysis of Performance Gap Between OpenACC and the Native Approach on P100 GPU and SW26010: A Case Study with GTC-P Stephen Wang†1, James Lin†1, William Tang†2, Stephane Ethier†2, Bei Wang†2, Simon See†1,3 †1 Shanghai Jiao Tong University, Center for HPC †2 Princeton University, Institute for Computational Science & Engineering (PICSciE) and Plasma Physics Laboratory(PPPL) †3 NVIDIA corporation GTC 2018, San Jose, USA March 27, 2018 1 Background • Sunway TaihuLight is now the No.1 supercomputer on the Top500 list. In the near future, Summit in ORNL will be the next leap in the leadership-class supercomputers. à Maintaining the single code on different supercomputers. • The real-world applications with OpenACC can achieve the portability across NVIDIA GPU and Sunway processors. GTC-P code is a case study. à We proposed to analyze the performance gap between the OpenACC version and the native programming approach on two different architectures. 2 GTC-P: Gyrokinetic Toroidal Code - Princeton • Developed by Princeton to accelerate progress in highly-scalable plasma turbulence HPC Particle-in-Cell (PIC) codes • Modern “co-design” version of the comprehensive original GTC code with focus on using Computer Science performance modeling to improve basic PIC operations to deliver simulations at extreme scales with unprecedented resolution & speed on variety of different architectures worldwide • Includes present-day multi-petaflop supercomputers, including Tianhe-2, Titan, Sequoia, Mira, etc., that feature GPU, CPU multicore, and many-core processors
    [Show full text]
  • Comparative HPC Performance Powerpoint
    Comparative HPC Performance TOP500 Top Ten, Graph and Detail FX700 Actual Customer Benchmarks GRAPH500 Top Ten, Graph and Detail HPCG Top Ten, Graph and Detail HPL-AI Top Five, Graph and Detail Top 500 HPC Rankings – November 2020 500 450 400 350 300 Home - | TOP500 250 200 150 100 50 0 Fugaku Summit Sierra TaihuLight Selene Tianhe Juwels HPC5 Frontera Dammam 7 Rmax (k Tflop/s) Home - | TOP500 Rank Cores Rmax (TFlop/s) Rpeak (TFlop/s) Power (kW) 1 Supercomputer Fugaku - Supercomputer Fugaku, A64FX 48C 2.2GHz, Tofu interconnect D, Fujitsu 7,630,848 442,010 537,212 29,899 RIKEN Center for Computational Science Japan Summit - IBM Power System AC922, IBM POWER9 22C 3.07GHz, NVIDIA Volta GV100, Dual-rail Mellanox EDR 2 2,414,592 148,600 200,795 10,096 Infiniband, IBM DOE/SC/Oak Ridge National Laboratory United States Sierra - IBM Power System AC922, IBM POWER9 22C 3.1GHz, NVIDIA Volta GV100, Dual-rail Mellanox EDR 3 1,572,480 94,640 125,712 7,438 Infiniband, IBM / NVIDIA / Mellanox DOE/NNSA/LLNL United States 4 Sunway TaihuLight - Sunway MPP, Sunway SW26010 260C 1.45GHz, Sunway, NRCPC 10,649,600 93,015 125,436 15,371 National Supercomputing Center in Wuxi China 5 Selene - NVIDIA DGX A100, AMD EPYC 7742 64C 2.25GHz, NVIDIA A100, Mellanox HDR Infiniband, Nvidia 555,520 63,460 79,215 2,646 NVIDIA Corporation United States 6 Tianhe-2A - TH-IVB-FEP Cluster, Intel Xeon E5-2692v2 12C 2.2GHz, TH Express-2, Matrix-2000, NUDT 4,981,760 61,445 100,679 18,482 National Super Computer Center in Guangzhou China JUWELS Booster Module - Bull Sequana XH2000 , AMD EPYC 7402 24C 2.8GHz, NVIDIA A100, Mellanox HDR 7 449,280 44,120 70,980 1,764 InfiniBand/ParTec ParaStation ClusterSuite, Atos Forschungszentrum Juelich (FZJ) Germany 8 HPC5 - PowerEdge C4140, Xeon Gold 6252 24C 2.1GHz, NVIDIA Tesla V100, Mellanox HDR Infiniband, Dell EMC 669,760 35,450 51,721 2,252 Eni S.p.A.
    [Show full text]
  • International Hpc Activities
    INTERNATIONAL HPC ACTIVITIES Jack Dongarra University of Tennessee Oak Ridge National Laboratory 1 State of Supercomputing Today • Pflops (> 1015 Flop/s) computing fully established with 95 systems. • Three technology architecture possibilities or “swim lanes” are thriving. • Commodity (e.g. Intel) • Commodity + accelerator (e.g. GPUs) (93 systems) • Lightweight cores (e.g. ShenWei, ARM, Intel’s Knights Landing) • Interest in supercomputing is now worldwide, and growing in many new markets (around 50% of Top500 computers are used in industry). • Exascale (1018 Flop/s) projects exist in many countries and regions. • Intel processors have largest share, 91% followed by AMD, 3%. 2 H. Meuer, H. Simon, E. Strohmaier, & JD - Listing of the 500 most powerful Computers in the World - Yardstick: Rmax from LINPACK MPP Ax=b, dense problem TPP performance Rate - Updated twice a year Size SC‘xy in the States in November Meeting in Germany in June - All data available from www.top500.org 3 Performance Development of HPC over the Last 24 Years from the Top500 11E+09 Eflop/s 567 PFlop/s 100 Pflop/s 100000000 93 PFlop/s 1000000010 Pflop/s 10000001 Pflop/s SUM 100000100 Tflop/s 286 TFlop/s 10 Tflop/s 10000 N=1 1 Tflop/s 1000 1.17 TFlop/s 100 Gflop/s 100 N=500 59.7 GFlop/s 10 Gflop/s 10 1 Gflop/s 1 100 Mflop/s 400 MFlop/s 0.1 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 PERFORMANCE DEVELOPMENT 1 Eflop/s1E+09 N=1 100000000100 Pflop/s 10 Pflop/s 10000000 N=10 10000001 Pflop/s SUM N=100 100100000 Tflop/s 10 Tflop/s 10000 1 Tflop1000/s
    [Show full text]
  • Conceptual and Technical Challenges for High Performance Computing Claude Tadonki
    Conceptual and Technical Challenges for High Performance Computing Claude Tadonki To cite this version: Claude Tadonki. Conceptual and Technical Challenges for High Performance Computing. 2020. hal- 02962355 HAL Id: hal-02962355 https://hal.archives-ouvertes.fr/hal-02962355 Preprint submitted on 9 Oct 2020 HAL is a multi-disciplinary open access L’archive ouverte pluridisciplinaire HAL, est archive for the deposit and dissemination of sci- destinée au dépôt et à la diffusion de documents entific research documents, whether they are pub- scientifiques de niveau recherche, publiés ou non, lished or not. The documents may come from émanant des établissements d’enseignement et de teaching and research institutions in France or recherche français ou étrangers, des laboratoires abroad, or from public or private research centers. publics ou privés. Conceptual and Technical Challenges for High Performance Computing Claude, Tadonki Mines ParisTech – PSL Research University Paris, France Email: [email protected] Abstract High Performance Computing (HPC) aims at providing reasonably fast computing solutions to scientific and real life problems. Many efforts have been made on the way to powerful supercomputers, including generic and customized configurations. The advent of multicore architectures is noticeable in the HPC history, because it has brought the underlying parallel programming concept into common considerations. At a larger scale, there is a keen interest in building or hosting frontline supercomputers; the Top500 ranking is a nice illustration of this (implicit) racing. Supercomputers, as well as ordinary computers, have fallen in price for years while gaining processing power. We clearly see that, what commonly springs up in mind when it comes to HPC is computer capability.
    [Show full text]
  • Supercomputer Fugaku Takes First Place in the Graph 500 for the Three
    July, 2021 NEWS RIKEN Kyushu University Fixstars Corporation Fujitsu Limited Supercomputer Fugaku takes first place in the Graph 500 for the three consecutive terms A research paper on the algorithm and experimental results at Supercomputer Fugaku was presented at ISC21 A collaborative research group* consisting of RIKEN, Kyushu University, Fixstars Corporation, and Fujitsu Limited has utilized the entire system of Supercomputer Fugaku (Fugaku) at RIKEN and won first place for three consecutive terms following November 2020 (SC20) in the Graph500, an international performance ranking of supercomputers for large-scale graph analysis. The rankings were announced on July 1 (July 1 in Japan) at ISC2021, an international conference on high-performance computing (HPC). A following research paper on the algorithm and experimental results at Supercomputer Fugaku was presented at ISC2021. Masahiro Nakao, Koji Ueno, Katsuki Fujisawa, Yuetsu Kodama and Mitsuhisa Sato, Performance of the Supercomputer Fugaku for Breadth-First Search in Graph500 Benchmark, Intentional Supercomputing Conference (ISC2021), Online, 2021. 1 The performance of large-scale graph analysis is an important indicator in the analysis of big data that requires large-scale and complex data processing. Fugaku has more than tripled the performance of the K computer, which won first place for nine consecutive terms since June 2015. ※A collaborative research group Center for Computational Science, RIKEN Architecture Development Team Team Leader Mitsuhisa Sato Senior Scientist Yuetsu Kodama Researcher Masahiro Nakao Institute of Mathematics for Industry, Kyushu University Professor Katsuki Fujisawa Fixstars Corporation Executive Engineer Koji Ueno The extremely large-scale graphs have recently emerged in various application fields, such as transportation, social networks, cyber-security, and bioinformatics.
    [Show full text]