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DOWNLOAD HPSIM DIGITAL CIRCUIT FUNCTIONAL SIMULATOR
TO PERSONAL COMPUTER
by
Hsi-Ming Chen
A Thesis Submitted to the Faculty of the
DEPARTMENT OF ELECTRICAL ENGINEERING
In Partial Fulfillment of the Requirements For the Degree of
MASTER OF SCIENCE
In the Graduate College
THE UNIVERSITY OF ARIZONA
19 8 5 STATEMENT BY AUTHOR
This thesis has been submitted in partial fulfillment of re quirements for an advanced degree at the University of Arizona and is deposited in the University Library to be made available to borrowers under rules of the Library.
Brief quotations from this thesis are allowable without special permission, provided that accurate acknowledgement of source is made. Requirements for permission for extended quota tion from or reproduction of this manuscript in whole or in part may be granted by the head of the major department or the Dean of the Graduate College when in his or her judgment the proposed use of the material is in the interests of scholarship. In all other instances, however, permission must be obtained from the author.
SIGNED: /cJlsZ-/ft'*
APPROVAL BY THESIS DIRECTOR
This thesis has been approved on the date shown below:
/?/j- FREDRICK/J. HILL Date Professor of Electrical Engineering TABLE OF CONTENTS
Page
LIST OF ILLUSTRATIONS v
LIST OF TABLES vi
ABSTRACT vii
1. INTRODUCTION 1
2. STRUCTURE OF HPSIM II 4
2.1 Overview of HPSIM II 4 2.2 AHPL Sequence File Syntax Analysis 4 2.3 Control Sequence BNF Grammar 6 2.A AHPL Communication File Syntax Analysis 6 2.5 Pass One of HPSIM II 6 2.6 Pass Two of HPSIM II 14 2.7 Memory Allocation Scheme 14 2.8 Using HPSIM II 16 2.9 Application 19
3. IMPLEMENTATION OF HPSIM II USING MICROSOFT FORTRAN 20
3.1 Overview of Languages 20 3.2 Differences between VAX-11 Fortran and Microsoft Fortran . 20 3.3 Differences between General Linker and Overlay Linker . . 25
4. IMPLEMENTATION OF HPSIM II USING IBM PROFESSIONAL FORTRAN ... 35
4.1 Overview of Languages 35 4.2 Differences between Microsoft Fortran and IBM Professional Fortran . . 35
5. SOME TEST CASES 43
5.1 A Simple Multiplier Circuit 43 5.2 Random Process Monitor 46
6. ANALYSIS OF RESULTS 50
6.1 Running HPSIM II on IBM PC 51 6.2 Running HPSIM II on IBM AT 55
iii TABLE OF CONTENTS—Continued
Page
6.3 Running HPSIM II on ITT XTRA PC 59 6.4 Summary of Results 61
7. CONCLUSION 64
APPENDIX A. 8088 ASSEMBLY UNGUAGE SUBROUTINES 65
REFERENCES 73
iv LIST OF ILLUSTRATIONS
Figure Page
2.1 Parsing Organization of AHPL Sequence File 5
2.2 BNF Grammar for AHPL Sequence 7
2.3 BNF Grammar of the Communication File 9
2.4 Interaction Between Phases of Pass One 10
2.5 Pass Two Block Diagram 15
2.6 Memory Allocation 17
2.7 Organization of AHPL Communication File 18
3.1 Memory Organization 23
3.2 Overlays Structure in TURBO Pascal 28
3.3 Linker List using MS General Linker 30
3.4 Linker List using MS Overlay Linker 32
4.1 Different Data Initialization 39
4.2 First Test of Shift Function 40
4.3 Second Test of Shift Function 41
5.1 The Multiplier Block Diagram 44
5.2 HPSIM II Input Files for Multiplier 45
5.3 Random Process Monitor 46
5.4 First Design of Random Sequence Monitor . 48
5.5 Second Design of Random Sequence Monitor 49
6.1 System Memory Map for 64/256K System Board 52
v LIST OF TABLES
Table Page
2.1 Scanner Codes 12
6.1 Specification Data of Diskette Types for IBM PC 53
6.2 Transfer Kate of Disk-Drive for IBM PC 54
6.3 Test Results on IBM PC and VAX 750 56
6.4 Specification Data of Fixed Disk Types for IBM XT AT ... . 58
6.5 Test Results on IBM AT and VAX 750 60
6.6 Summary of Test Results 63
vi ABSTRACT
HPSIM, Hardware Program Simulator, is a digital system function level simulation program and HPSIM II, is an improved version of the simulator, both of which has been implemented on the CDC-6400, DEC-10 and VAX-750. After Intel Corporation introduced the first microprocessor-chip 4004 in 1970, the cost of microprocessor components have been decreased constantly using new advanced technology, so that the microcomputer has played an important role in computer technology.""
This paper discusses the feasibility of implementing HPSIM II on personal computers considering the limitations of hardware and software in these computers.
vii CHAPTER 1
INTRODUCTION
Simulation, in different forms, is used extensively in any design
— electronic circuit, digital system, mechnical, chemical process, etc.
The various forms of simulation in circuit design can be categorized in terms of the level of detail offered, ranging from circuit level
(transistors, resistors, capacitors, etc.) to timing level (e.g.,
M0TIS[1]) to logic gate level (NOR, NAND, etc.) to function level. At the function level, such a simulation program will test the designed digital system, eliminating the designer's need to test and debug his circuit in the laboratory. HPSIM II which was written by Navabi (1977) is such a program.
An effective simulation system needs a powerful design language to support it. A suitable hardware design language for digital system design must permit sufficient detail to describe even bit-by-bit operations and must at the same time have sufficient power to permit concise description of complex operations. AHPL [2], A Hardware
Programming Language written by Fredrick J. Hill and Gerald R. Peterson, meets these two requirements. It is a clocked mode register transfer level language (RTL). This language is based on the APL [3], A
Programming Language, which utilizes much of the syntax of the programming language to describe the hardware implementations of clock-
1 2 mode circuits and expresses very complex operations in compact form.
AHPL inherits these traits but it is constrained by its one-to-one correspondence with the actual hardware. Due to these mentioned advantages, AHPL was chosen to be the design language used by HPSIM II.
When the first 4- and 8-bit microprocessors appeared on the market, the hardware costs associated with a microprocessor system were so high and the speed was so slow as compared to main frame machines that they had a small impact on computer technology. With the constantly decreasing cost of the new microprocessor components and the ceaseless application of new technology, microprocessors have become very important. Because main frame machine supports multiusers and multiprocessing, it is often not convenient to run a big program, especially a large simulation program, even during slow hours.
Sometimes you could have the situation that it will take longer time to run a small program because of the heavy load on the system. On the other hand, because many software packages are now available for personal computers, for example, communication packages between main frames and personal computers, it may be more feasible to run the simulation on personal computer.
This paper is divided into seven chapters. Chapter 2 gives a general description of the algorithm and the internal data structures which have been implemented in HPSIM II. Further information about HPSIM
II is described by Navabi (1977) [4]. 3
Chapter 3 describes the implementation of HPSIM II using the
Microsoft Fortran compiler. This chapter also compares the difference between using the general linker and the overlay linker both of which are supported by the Micro-Soft Fortran compiler. The linker lists are shown to aid in comparison.
The implementation of HPSIM II using the IBM professional Fortran compiler is described in Chapter 4. A comparison between the IBM professional Fortran and Micro-Soft Fortran is given.
Chapter 5 shows some test cases on different personal computers using different versions of HPSIM II. Those tests include ones on IBM
PC, IBM AT, ITT XTRA PC personal computers.
Chapter 6 analyzes these test results from the viewpoint of software and hardware. These results show the feasibility of using
HPSIM II on personal computers.
Chapter 7 discusses the limitation of using HPSIM II on personal computers. CHAPTER 2
STRUCTURE OF HPSIM II
2.1 Overview of HPSIM II
HPSIM II is a two-pass function level simulator which interprets the AHPL description and executes connections, branches and transfers, then prints the user specified circuit value at each clock period. It needs two input files, one of which is the AHPL sequence file which describes the function of the user designed circuit. The other is the
AHPL communication file which specifies the initial values of the controlled inputs and the desired outputs. In this chapter, a general description of these files is given. Further information about these files is given in the user manual for HPSIM and HPCOM. [5]
2.2 AHPL Sequence File Syntax Analysis
There are several methods of parsing the source code of a compiler or an interpreter, one of which is the table-directed method. The table-directed method insures that all illegal syntax constructs will be detected and nothing will be overlooked. Besides that, the computer is able to do the parsing much faster by a table-directed method.
Therefore, HPSIM II applies the table-directed method for syntax parsing.
4 5
The AHPL declaration has a very simple syntax and symbol subscripts are always constants. To take full advantage of this feature, HPS1M II allocates the symbols and replaces them by pointers, then uses the pointers for table-directed parsing. Thus, the partially ad-hoc and partially table-directed method of parsing was chosen in HPSIM II.
Figure 2.1 illustrates the AHPL sequence file parsing organization in
HPSIM II.
AHPL SEQUENCE FILE
DECURATION
DECLARATION POINTERS PARTS SYMBOLS
TABLE DIRECTED PARSER CONTROL SEQUENCE PARTS CONTROL SEQUENCE
Figure 2.1 Parsing Organization of AHPL Sequence File 6
2,3 Control Sequence BNF Grammar
HPSIM II uses the BNF grammar of Figure 2.2 for the control sequence parsing. With this grammar all the legal constructs of control sequences can be recognized and any construct not described is illegal and will be rejected by the parser.
2.4 AHPL Communication File Syntax Analysis
The AHPL communication file of HPSIM II uses a full table directed parser. Figure 2.3 shows the BNF grammar of the communication file.
2.5 Pass One of HPSIM II
The first pass of HPSIM II is divided into seven major phases — scanner, symbol-parser, symbol-manager, main-parser, control sequence semantics, communication section parser and communication section semantics. Pass one will read the input files character by character, assemble the characters into symbols, assign tokens to each symbol, allocate storage for the variables, check the syntax of control sequences, translate the AHPL sequence file into five tables, check the syntax of communication file and finally translate the communication file into a table format. All the ambiguities in semantics or violations in syntax in the input files will be detected in this pass.
If errors are detceted, HPSIM II will issue the appropriate error or warning message then stop. Figure 2.4 shows a flow chart of the interaction in pass one. LEFT HAND SIDE RIGHT HAND SIDE
1 {CIRCUIT} := {SEQUENCE} END .
2 {SEQUENCE} := {CLOCK SEQ} ENDSEQUENCE {UNCL SEQ} 3 := {SEQUENCE} END {SEQUENCE}
{CLOCK SEQ) SEQNUMBER {STEP} 5 , SEQNUMBER {STEP} 6 {CLOCK SEQ} SEQNUMBER {STEP}
7 {STEP} {TIMING} {ACTION} 8 NULL , 9 DEADEND ,
10 {TIMING} NODELAY 11 'EMPTY'
12 {ACTION} {RELATION} {BRANCH} 13 {RELATION} 14 {BRANCH} ,
15 {RELATION} {DLRM} = {GLRM} 16 {DLRM} <= {GLRM} 17 {CLHS} <= {GLRM} 18 {RELATION} ; {RELATION}
19 {DLRM} {DLRM} ! {DLRM} 20 {DLRM} , {DLRM} 21 ( {DLRM} ) 22 SLRM
23 {CLHS} {DLRM} * {GLRM} 24 ( {CLHS} )
25 {GLRM} {GLRM} & {GLRM} 26 {GLRM} + {GLRM} 27 {GLRM} @ {GLRM} 28 {GLRM} , {GLRM} 29 {GLRM} ! {GLRM} 30 {GLRM} * {GLRM} 31 &/ {GLRM} 32 +/ {GLRM} 33 nt {GLRM}
Figure 2.2 BNF Granunar for AHPL Sequence LEFT HAND SIDE RIGHT HAND SIDE
= A {GLRM} = INTEGER $ INTEGER = $ ( INTEGER ; INTEGER ) = DCD ( {FUNC INPUT} ) = INC ( {FUNC INPUT} ) = ADD ( {FUNC INPUT} ) = BUSFN ( {FUNC INPUT} ) = DEC ( {FUNC INPUT} ) « PRI ( {FUNC INPUT} ) = ASSOC ( {FUNC INPUT} ) = COMPARE ( {FUNC INPUT) ) = :: SLRM ( {FUNC INPUT) ) = \ {NUMBER STR) \ = ( {GLRM} ) = SLRM
{FUNC INPUT} {GLRM} {FUNC INPUT) {GLRM}
{NUMBER STR} {NUMBER STR} INTEGER INTEGER
{UNCL SEQ) {START STEP} {ACTION} {START STEP}
{START STEP) := CONTROLRESET ( {NUMBER STR} )
{BRANCH} => ( {GLRM} ) / ( {NUMBER STR} ) => INTEGER => ( {NUMBER STR} )
Note: SLRM — Simple Line, Register, or Memory {DLRM} — Destination Line, Register, or Memory {GLRM} — General Line, Register, or Memory {CLHS} — Conditional Left Hand Side
Figure 2.2 BNF Grammar for AHPL Sequence(contd.) {COMSEC} {BODY} {BODY} {SECTIONS} {OPTSEC} {SECTIONS} {SECTIONS} {SECTIONS} {SECTIONS} {CLMSEC} {EXLSEC} {INTSEC} {OUTSEC} {DMPSEC} {SUPSEC} {OPTSEC} option INTEGER . {CLMSEC} clocklimit INTEGER {EXLSEC} exlines {EXLASSIGN} . {EXLASSIGN} {EXLASSIGN} ; {EXLASSIGN} DECSYM = {EXLDATA} DECSYM = repeat {EXLDATA} DECSYM = {EXLDATA} , repeat {EXLDATA} {EXLDATA} {EXLDATA} , {EXLDATA} INTEGER INTEGER * DECSYM INTEGER * A DECSYM INTEGER # INTEGER {INTSEC} initialize {INITASSIGN} {INITASSIGN} {INITASSIGN} ; {INITASSIGN} {SYMBOL} <= {INITDATA} {SYMBOL} DECSYM DECSYM < INTEGER > DECSYM < INTEGER ! INTEGER > {INITDATA} {INITDATA} ! {INITDATA} INTEGER INTEGER # INTEGER {OUTSEC} outputs {NAMELIST} {NAMELIST} {NAMELIST} ; {NAMELIST} {SYMBOL} {SYMBOL} / INTEGER {DMOSEC} dump all dump {NAMELIST} {SUPSEC} suppress {STEPLIST} . {STEPLIST} {STEPLIST} ; {STEPLIST} INTEGER / INTEGER
Note: DECSYM — ANY DECLARED SYMBOL
Figure 2.3 BNF Grammar of the Communication File START SCANNER
GET SYMBOL ACTIVATE COMMUNICATION YES SECTION PARSE REACH END OF END PASS I
.T-NO SYMBOL PARSER YES /IS IN\ NO DECLARATION V PART / YES
FIND THE LIMIT OF SYMBOL VARIABLE MANAGER
PUT IT IN PUT IT IN SYMBOL DECLARATION REFERENCE TABLE TABLE AND FIND POINTER
NO PRODUCTION BUILD A MAIN SCOMPLETE> PRODUCTION PARSER
YES
BUILD NECESSARY SEMANTICS TABLE
Figure 2.4 Interaction Between Phases of Pass One 11
The scanner reads one line of source code, breaks it into characters, constructs and assigns each a token number and a sub-token
number. Tokens are symbols that appear in the language, token-numbers are numbers that represents the tokens, and sub-tokens are used to
distinguish tokens with the same token-numbers. Table 2.1 lists all
tokens with their token-numbers and sub-tokens.
The symbol-parser does the parsing of the declaration part and the
identifiers. The inputs to this phase are token-numbers and sub-tokens.
If the corresponding token is not part of the declaration or part of a sequence identifier, the input information ( token-number and sub-token)
will be returned to the calling program (main-parser). Otherwise, this
phase keeps calling the scanner until it receives all the information about a symbol. The output of the symbol-parser will be the AHPL
description without the declaration.
The symbol-manager is called by the symbol-parser and receives
information about the symbol along with a code number that tells symbol-
manager what task to perform. When the symbol-manager receives a symbol, it puts the symbol in the SRT table (Symbol Reference Table) and
passes control to the main-parser. If the received symbol is part of the declaration, it will be placed in the SDT (Symbol Declaration Table) and control will be passed to the scanner. The scanner, the symbol-
parser and symbol-manager work together to build the SDT and the SRT
until the declaration part of the AHPL sequence file is finished. Table 2.1 Scanner Codes
TOKEN SYMBOL TOKEN NO. SUB-TOKEN
LETTER A-Z 1 0 DIGIT 0-9 2 0 BACK SLASH \ 4 0 AND & 5 0 OR + 6 0 LEFT ANGULAR BRACKET < 7 0 EQUAL m 8 0 QUOLON I 9 0 RIGHT ANGULAR BRACKET > 10 0 SLASH / 11 0 CONDITION * 12 0 EXCLUSIVE OR @ 13 0 ENCODE $ 14 0 LEFT PARENTHESES ( 15 0 RIGHT PARENTHESES ) 16 0 LEFT SQUARE BRACKET [ 17 0 RIGHT SQUARE BRACKET ] 18 0 COLUMN CATENATION • 19 0 ROW CATENATION ! 20 0 SEPARATOR 1 21 0 TERMINATOR • 22 0 INVERTOR * 23 0 COMMENT DELIMITER 1 24 0 AND REDUCTION «/ 25 0 OR REDUCTION +/ 26 0 TRANSFER <- 27 0 BRANCH -> 28 0 DOUBLE COLON :: 29 0 PROGRAM DELIMITER - 30 0 BLANK CHARACTER 31 0 INTEGERS ALL NUMBERS 35 •THE VALUE' STEP NUMBER ALL NUMBERS 36 •THE STEP' IDENTIFIER ALPHANUMERICS 37 •THE NAME' MODULE BEGINNER AHPLMODULE 38 AHPLMODULE MEMORY ELEMENTS MEMORY 39 MEMORY INPUT LINES INPUTS 40 INPUTS OUTPUT LINES OUTPUTS 41 OUTPUTS BI-DIRECTION LINES BUSES 42 BUSES LABELS LABELS 43 LABELS ONE-SHOTS ONESHOTS 44 ONESHOTS EXTERNAL INPUT LINES EXINPUTS 45 EXINPUTS INCREMENTOR INC 46 INC ADDER ADD 47 ADD DECODER DCD 48 DCD INVERTOR NT 49 NT CONTROL RESET CONTROLRESET 50 CONTROLRES DEAD END STEP DEADEND 51 DEADEND NO DELAY NODELAY 52 NODELAY END SEQUENCE ENDSEQUENCE 53 ENDSEQUENCE MODULE TERMINATOR END 54 END NULL STEP NULL 55 NULL DECREMENTOR INC 56 DEC COMBINATIONAL UNITS CLUNITS 57 CLUNITS BUS FUNCTION BUSFN 58 BUSFN EXTERNAL BI-DIR. LINES EXBUSES 59 EXBUSES ASSOCIATIVE LOGIC ADD 60 ASSOC COMPARATOR ADD 61 COMPARE PRIORITY FUNC. LOGIC INC 62 PR I 13
The main-parser receives the token-number and the sub-token number from the symbol-parser phase. When it receives all characters of a certain production, it finds the code for the LHS (Left Hand Side) and gives the necessary information to the semantics routine. Knowing the
LHS, and the information about each production, the semantics phase will
build the rest of the tables. In this phase, there is an error recovery routine; in case of syntax errors, the analyzer will not stop but will continue checking the syntax of the rest of the source code.
The control sequence semantics phase receives the production number and a code indicating step number from the main-parser. This phase may
be called for any one of the 58 productions of the BNF grammar to do the corresponding semantic action. For some productions no semantic action is needed and the semantic routine will immediately return to the main-
parser. The output of this phase to the main-parser is a temporary symbol pointer which is the row number of the TOTS (Table Of Temporary
Symbol). This phase will finish building the rest of the tables.
The communication section parser and communication section semantics phase are responsible for the compilation of the communication file. The communication section parser analyzes the syntax of the AHPL communication file. This phase calls the scanner for the communication file symbols and passes the production code to the communication semantics.
The communication section semantics phase receives the production from the communication section parser and calls one of the 28 semantic routines to perform the specific action. This phase will extend the
QTABLE table ( Quadruple TABLE ) and generate the EXL1ST table ( EXline
LIST ).
2.6 Pass Two of HPSIM II
Pass two gets activated only after the successful compilation of
pass one. The six tables that are prepared by pass I will be used for execution of each clock cycle in pass two. When pass two begins, the initially active steps are already in the NEST table ( Next Executable
Step Table ). At each clock period and for each active step in the NEST
table the corresponding quadruples that are found from the SQRT table (
Step Quadruple Relation Table ) are sent to the EXECUTE routine. This routine will pass the quadruple to the appropriate routine for execution of that specific quadruple. On return the result of execution will be in the SVT tables ( Symbol Value Table ). Then the next active step in the NEST is looked up and this same process is repeated, this until all active steps are taken care of. Then the result of the current clock execution is printed out, the NEST table is renewed with the new active step, and the execution begins for the next clock period.
Execution continues until either a complete dead end is reached or the number of executed periods reaches the limit which was specified by the user. Figure 2.5 shows the block diagram for the pass two. START
READ BIT VALUE OF EXTERNAL LINE
FIND ACTIVE STEPS
NO YES EXECUTABLE NEST EMPTY QUADRUPLES
PRINT RESULTS
RENEW NEST
Figure 2.5 Pass Two Block Diagram 16
2.7 Memory Allocation Scheme
HPSIM II uses a dynamic storage allocation scheme. There is a storage pool of fixed size in the program. This storage pool is a linear linked list. The first element of the storage pool always points to the second element of the pool which points to the unassigned space. Every table whose size depends on the input AHPL file is dynamic. The first element of the dynamic table contains the number of elements to be used on every request. When a table needs to expand, it asks the storage pool for extra space. After the extra space is granted, the index of the first element of the new assigned space will be placed in the next element of the dynamic table and the second element of the storage pool will be modified to point to the new unassiged space. Thus
HPSIM II can easily access the stored data by looking up the dynamic table. Figure 2.6 shows the diagram of memory allocation.
2.8 Using HPSIM II
It is necessary to generate two files before running HPSIM II as mentioned earlier. The first file will contain the AHPL description which specifies the function of the designed circuit. Chapter 5 of reference 2 has a complete description of all AHPL syntactic constructs.
HPSIM II uses these constructs with some modifications in punctuations, keyword usage and symbols. The HPSIM II requires that all statements be followed by semicolons and every step be terminated by a period. It does not allow the AHPL step numbers to be followed by a period. The 17
LIST
STORAGE POOL
2203
LIST SDT
203 203
SDT
703
SRT SRT
703
1703
SQRT
2202 SQRT 2203
1703 UNUSED AREA
30000
Figure 2.6 Memory Allocation 18 keywords used in HPSIM II cannot contain a blank separator. For example "End sequence" in AHPL should be used as "ENDSEQUENCE".
The second file will contain the input sequences and simulation control information. The format of the communication file is shown in
Figure 2.7. Further information about this file is given in the user manual for HPSIM and HPC0M.[5] The subsections are all optional. The
OPTIONS subsection must appear first, if present. The remaining subsections may appear in any order.
OPTIONS SUBSECTION
CLOCKLIMIT SUBSECTION
EXTERNAL LINES VALUE ASSIGNMENT SUBSECTION
INITIALIZATION SUBSECTION
OUTPUT SUBSECTION
DUMP SUBSECTION
SUPPRESS SUBSECTION
Figure 2.7 Organization of AHPL Communication File 19
2.9 Application
HPSIM II also provides the additional flexibility of simulating multiple hardware descriptions. Several modules may be simulated simultaneously to create a system operating environment to test a hardware description. An example of this is the use of HPSIM II by
Irwin Jacob Robinson [6] as a tool to design a parallel processor. CHAPTER 3
IMPLEMENTATION OF HPSIM II USING MICROSOFT FORTRAN
3.1 Overview of Languages
The VAX-11 Fortran is based on American National Standard Fortran-
77 (ANSI X3.9-1978). It includes support for programs that conform to
the previous standard (ANSI X3.9-1966) with some extended features, for
example, " ENCODE " (do write function) and " DECODE " (do read
function). The VAX-11 Fortran can be used in the VAX series of main
frames. It is also a compatible superset of PDP-11 FORTRAN-77. This
means you can compile existing PDP-11 Fortran-77 source programs, as
well as new programs that incorporate features available in VAX-11
Fortran. The currently used Microsoft Fortran is version 3.2 which
conforms to the ANSI X3.9-1978 Subset FORTRAN requirements, but has many
features of the full language plus extensions designed to optimize
FORTRAN in the microcomputer environment. The Microsoft Fortran compiler accepts programs written in Microsoft Fortran and can run under
version 1.25 or later of the Microsoft Disk Operating System (MS-DOS).
3.2 Differences between VAX-11 Fortran and Microsoft Fortran
The VAX-11 Fortran is based on ANSI X3.9-1978 with some extensions while the Microsoft Fortran conforms to the Subset of ANSI X3.9-1978.
There are several differences between them. In this section, some of
20 21 those differences will be pointed out and compared. The actual differences can be found in the User Guides and Reference Manuals.
1. The upper limit on the size of object code that can be generated
at one time by the Microsoft Fortran compiler is 64K bytes.
Since we can compile any number of compilands separately and
link them together later, the real limit on program size is not
64K but is restricted by the linking capacity of the linker
(approximately 900K bytes) and the amount of main memory
available. However, the only limit on object code size or
program size on VAX-11 Fortran is the memory quota you have.
In practice, a source file large enough to generate 64K bytes of
code would be thousands of line long and unwieldy both to edit
and to maintain. Separate compilation will have no effect on the
final program size, but may increase the total size of object
files. Hence this 64k bytes limit on object code size presents
no difficulty while using Microsoft Fortran for a large program.
2. The 8086 segmented memory addressing scheme makes it
inefficient to address arrays which span more than one
segment. By default, arrays are put in the DGROUP
segment. A segment consists of 65536 bytes aligned on a
paragraph boundary. Microsoft Fortran supports the metacommand,
$LARGE, to specify that an array is "large" and needs to be put
in a separate segment. In VAX-11 Fortran there is no need to
specify that array as "large" as in Microsoft Fortran, because 22
VAX does not have the segment size restriction of the 8086.
3. In Microsoft Fortran, the default data segment (DGROUP) also
contains data defined by the runtime system, the stack, space
for dynamic allocation of file blocks (634 bytes per file) and,
if $DEBUG (one of the metacommands) has been used, some
subprogram entry and exit information. Figure 3.1 shows the
memory organization. This figure shows that each COMMON block
or long array is allocated as many adjacent segments outside
DGROUP as are required to accommodate it, so we can increase
the amount of space available in the DGROUP by moving data
into COMMON blocks, either blank or named. We can also more
conveniently move individual (short) arrays out of the DGROUP
by using the $LARGE metacommand, which causes them to be
allocated in separate segments. Because the indirect
references that must be made to data in other segments are less
efficient and result in more code being generated than
references to the default data segment, the program will be
bigger and slower if the $LARGE metacommand is applied.
A. The VAX-11 Fortran supports many generic and intrinsic
functions, such as bitwise OR, bitwise AND and bitwise SHIFT.
However, the Microsoft Fortran only supports a limited number of
intrinsic functions, so that you may need to write some assembly
language (8086 assembly language) routines to implement special
functions or make a system call. HIGHEST ADDRESS
MS-DOS code for COMMAND
unused memory
HIMEM segment COMMON block $LARGE arrays LONG array
CONST segment COMADS segment DATA segment STACK DGROUP
HEAP
User Code Area
Resident Portion of DOS
INTERRUPT VECTORS
LOWEST ADDRESS
Figure 3.1 Memory Organization 24
5. In VAX-11 Fortran, all the data in a COMMON block can be
initialized in the subprogram it is declared in. But in
Microsoft Fortran, only local variables and array elements can
appear in a DATA statement. Variables in COMMON blocks only
can be assigned initial values in a BLOCK DATA subprogram.
6. In Microsoft Fortran, when a subroutine or function is called,
the addresses of the actual parameters are first pushed on the
stack in the order that they are declared. If the procedure
called is a function and if the function return type is real or
double precision, an additional implicit parameter for the
function is pushed on the stack. This parameter is the two-
byte address of a temporary variable created by the calling
program. After all parameters have been pushed, the return
address is pushed. If the procedure called is a function and
the return value is a two-byte integer or logical value, that
value is expected in the AX register. If the procedure called
is a function and the return value is a four-byte integer or
logical value, that value is expected in the DX,AX pair. If the
return value is a four or eight byte REAL value or an eight or
sixteen byte COMPLEX value, that value is expected in the
temporary variable created by the calling program. The two-
byte address of this temporary variable is the last parameter
pushed on the stack. Appendix A shows the assembly language
routines implemented in HPSIM II to perform bitwise logical and bitwise shift operations.
7. The VAX-11 Fortran compiler is a one pass compiler, while the
Microsoft Fortran compiler is a three passes compiler. The
first and second passes are required but the third pass is
optional. Pass three is needed only if the object listing is
required. If no errors have been detected by the end of pass
one of Microsoft Fortran compiler, it will create two
intermediate files, PASIBF.SYM and PASIBF.BIN. These two files
will be read in pass two to generate the relocated object code.
8. There is one linker that can be used with the VAX-11 Fortran
compiler. There are two linkers that can be used with the
Microsoft Fortran compiler. The first, named LINK.EXE, is the
most current linker for MS-DOS version 1.25 and later. It will
run under MS-DOS 2.0 but will not accept pathnames or
subdirectories. The other version is named LINK.V2. It accepts
pathnames and includes an overlay option, but will only run on
MS-DOS 2.0 or later. The overlay linker must be renamed to be
an .EXE file to use it.
3.3 Differences between General Linker and Overlay Linker
The Microsoft Fortran compiler supports linking 8086 assembly language, Microsoft Fortran and Microsoft Pascal subroutines. This feature of linking together programs and subroutines of MS-FORTRAN source code, as well as assembly language and library routines, allow us to develop a program incrementally. The only limitation when using the 26 general linker is that the first object module given in response to the object module list prompt must be an MS-FORTRAN object module, although it need not be the main program.
An overlay is a portion of a program that is not always needed and is therefore not kept in the limited RAM space. When the overlay is needed, it is read from the disk and overlays another portion of the program in memory that is no longer needed. There are two ways in which programmers can produce overlaid code: with compiler-generated overlays and with linker-generated overlays. Some compilers support overlays directly. IBM Pascal version 2.0, SBB Pascal and Turbo Pascal all support their own versions of overlays. To use these compiler-generated overlays, programmers should include statements in their source code to inform the compiler which pieces of code reside in which overlays and when the overlays should be loaded. Figure 3.2 shows an example of using overlays in TURBO Pascal.
There are some disadvantages to using compiler-generated overlays.
Setting up any overlay structure involves a lot of trial and error. It may be necessary to set up the overlay structure several different ways, testing the program each time to see which set-up produces the best performance. It is difficult to experiment with compiler-generated overlay structure. To change this structure, programmers have to go back to their source code, change some of the statements and recompile the code. 27
The second way to get overlays into a program is to use a linker
that supports overlays. MS-FORTRAN LINK.V2 and Plink 86 are such
linkers. Linker-generated overlays overcome many of the disadvantages
of compiler-generated overlays. It is easy to set up the overlay
structure. To use linker-generated overlays, simply code and compile
the program as if it had no overlays at all. Then, when the separate
modules of the program are linked together, tell the linker how the
overlays should be set up and which modules reside in which overlays.
When the program runs, the overlay manager (which is contained in a
library that should also be linked to the program) intercepts the calls
to the overlaid routines and loads the overlays when needed. Another
advantage that linker-generated overlays have over compiler-generated
ones is that it is not necessary to recode and recompile programs
whenever the overlay structure is changed. Example 1 shows how to
specify the overlays in MS-PORTRAN.
Example 1:
Object Modules [.OBJ]: ROOT1+(OVRL1)+(OVRL2+OVRL3)+ROOT2+(OVRL4) Run File [R00T1.EXE]:
Each parenthetical list represents one overlay, i.e., (0VRL1),
(OVRL2+OVRL3), (0VRL4) are overlays. The remaining modules and any drawn
from the runtime libraries make up the resident part of your program, or
"root". Overlays are loaded into the same region of memory, so only one
can be resident at a time. overlay procedure first; begin
end; overlay procedure second; begin
end; procedure root; begin
end; overlay procedure third; begin
end;
A separate overlay area is reserved in the main program code for each group of overlay subprogram. This example will create the following files:
Main program Overlay Files
Main program code Overlay procedure first Overlay area 0 Overlay procedure second
Procedure root
Overlay area 1 Overlay procedure third
Main program code
Figure 3.2 Overlays Structure in TURBO Pascal 29
Figure 3.3 and 3.4 show the linker lists from the general linker and the overlay linker. From these two figures, we also see that we can have more space in the DGROUP area either declaring variables as "LARGE" or putting them in the COMMON block. Start Stop Length Name Class OOOOOH 0021CH 0021DH MAINH CODE 0021EH 00222H 00005H BLKDQ_ CODE 00224H 05853H 05630H MPARS CODE 05854H 0AC27H 053D4H SCANN CODE 0AC28H 0E898H 03C71H COMSE CODE OE89AH 14640H 05DA7H EXEC CODE 14642H 188D2H 04291H E29T2 CODE 188E0H 188FCH OOOIDH CODE1 CODE 18900H 1891CH OOOIDH CODE2 CODE 18920H 1893CH OOOIDH CODE3 CODE 18940H 18970H 00031H C0DE4 CODE 18980H 189B0H 00031H CODE5 CODE 189C0H 189E8H 00029H CODE6 CODE 189F0H 18A18H 00029H CODE7 CODE 18A20H 19299H 0087AH CODE CODE 192A0H 192A0H OOOOOH INIXQQ CODE 192A0H 1943FH OOIAOH ENTXQQ CODE USER 19440H 194B7H 00078H ERMVQQ CODE CODE 194B8H 1998AH 004D3H AUXVQQjCODE CODE AREA 1998CH 1AB40H 011B5H FILVQQ_CODE CODE 1AB42H 1B89BH 00D5AH FWTVQQ_CODE CODE 1B89CH 1BB74H 002D9H FONG CODE CODE 1BB80H 1BCFDH 0017EH LONGQQ CODE 1BD00H 1C06BH 0036CH MISGQQ CODE 1C06CH 1C322H 002B7H IOPVQQ_CODE CODE 1C330H 1C40EH OOODFH FORWQQ CODE 1C410H 1C4DAH OOOCBH MISYQQ_CODE CODE 1C4DCH 1D271H 00D96H FILUQQ_CODE CODE 1D280H 1D4F3H 00274H ERREEQ CODE 1D4F4H 1D61AH 00127H CONUXM CODE CODE 1D61CH 1D976H 0035BH PORUXM CODE CODE 1D978H 1DD1EH 003A7H LONCQQ_CODE CODE 1DD20H 1DD5AH 0003BH MISOQQ_CODE CODE 1DD5CH 1DF88H 0022DH ERREQQJCODE CODE 1DF8AH 1E0CFH 00146H UTLXQQ_CODE CODE lEODOH 1E26FH OOIAOH HEAHQQ_CODE CODE 1E270H 1E319H OOOAAH MISHQQJCODE CODE 1E320H 1E320H OOOOOH HEAP MEMORY — 1E320H 1E320H OOOOOH MEMORY MEMORY 1E320H 1E51FH 00200H STACK STACK 1E520H 21E53H 03934H DATA DATA DGROI 21E60H 21F86H 00127H DATA DATA AREA 21F88H 21F90H 00009H EINQQQ DATA 21FA0H 2219FH 00200H COMADS COMADS 221AOH 22A6DH 008CEH CONST CONST —J
Figure 3.3 Linker List using MS General Linker 22A70H 22A8FH 00020H XB9$A $XB9 22A90H 22ADFH 00050H XB8$A $XB8 22AE0H 22C8FH OOIBOH XB7$A $XB7 22C90H 22C9FH 0001OH XB6$A $XB6 22CA0H 22CEFH 00050H XB5$A $XB5 22CF0H 22DFFH 00110H XB4$A $XB4 22E00H 22E8FH 00090H XB3$A $XB3 22E90H 22EAFH 00020H XB2$A $XB2 22EB0H 22F2FH 00080H XB16$A $XB16 22F30H 22F5FH 00030H XB15$A $XB15 22F60H 238BFH 00960H XB13$A $XB13 238C0H 238CFH 0001OH XB12$A $XB12 238D0H 249AFH OlOEOH XB11$A $XB11 249B0H 249CFH 00020H XB10$A $XB10 249D0H 24A2FH 00060H XB1$A $XB1 COMMON 24A30H 24A3FH 00010H STL$A $STL BLOCK 24A40H 27B2FH 030F0H SHARE1$A $SHARE1 AREA 27B30H 27B3FH 00010H PUTB$A $PUTB 27B40H 27B5FH 00020H PRIO$A $PRIO 27B60H 27B6FH 0001OH OUT$A $OUT 27B70H 27CFFH 00190H 0RTB2S$A $0RTB2S 27D00H 27D0FH 00010H MODNUM$A $MODNUM 27D10H 27D1FH 00010H MASKS4$A $MASKS4 27D20H 27D3FH 00020H F428$A $F428 27D40H 27D5FH 00020H F2943$A $F2943 27D60H 27D6FH 00010H ESC1$A $ESC1 27D70H 27D7FH 00010H ERR$A $ERR 27D80H 27D8FH 00010H COMS$A $COMS 27D90H 37D8FH 10000H COMMQQ$A $COMMQQ 37D90H 4524FH 0D4C0H COMMQQ$B $COMMQQ 45250H 4525FH 00010H BSZ$A $BSZ 45260H 452FFH OOOAOH ALWAYS$A $ALWAYS 45300H 45300H OOOOOH HIMEM HIMEM 45300H 4534FH 00050H L~CAAA$A LARGE 45350H 4535FH 0001OH L~CAAA$A LARGE —
Origin Group 1BB8:0 CGROUP 12A7:0 DGROUP
Program entry point at 192A:0029
Figure 3.3 Linker List using MS General Linker(contd.) 32
Start Stop Length Name Class Resident OOOOOH 0021CH 0021DH MAINH CODE - 00220H 0023CH 0001DH C0DE1 CODE 00240H 0025CH OOOIDH CODE2 CODE 00260H 0027CH OOOIDH CODE3 CODE 00280H OO2BOH 00031H C0DE4 CODE 002C0H 002F0H 00031H C0DE5 CODE 00300H 00328H 00029H C0DE6 CODE 00330H 00358H 00029H C0DE7 CODE 00360H 00BD9H 0087AH CODE CODE OOBEOH 00D5DH 0017EH LONGQQ CODE OOD5EH 01F12H 011B5H FILVQQ_CODE CODE 01F14H 021CAH 002B7H IOPVQQ_CODE CODE 021CCH 02F25H 00D5AH FMTVQQ_CODE CODE 02F30H 02FA7H 00078H ERMVQQ CODE 02FB0H 03443H 00494H OVLMQQ CODE 03450H 0352EH OOODFH FORWQQ CODE 03530H 03808H 002D9H FONG CODE CODE USER 0380AH 03CDCH 004D3H AUXVQQ_CODE CODE CODE 03CE0H 0404BH 0036CH MISGQQ CODE AREA 04050H 04050H OOOOOH INIXQQ CODE 04050H 041EFH 001A0H ENTXQQ CODE 041F0H 04463H 00274H ERREEQ CODE 04464H 051F9H 00D96H FILUQQ_CODE CODE 051FAH 052C4H OOOCBH MISYQQJCODE CODE 052C6H 05620H 0035BH POROXM CODE CODE 05622H 05748H 00127H CONUXM CODE CODE 0574AH 05784H 0003BH MISOQQ_CODE CODE 05786H 059B2H 0022DH ERREQQ_CODE CODE 059B4H 05D5AH 003A7H LONCQQ_CODE CODE 05D5CH 05EFBH 001A0H HEAHQQ_CODE CODE 05EFCH 06041H 00146H UTLXQQ_CODE CODE 06042H 060EBH OOOAAH MISHQQ_CODE CODE 060F0H 060F0H OOOOOH OVERLAY AREA CODE 09990H 09990H OOOOOH OVERLAY END CODE - 09990H 09990H OOOOOH HEAP MEMORY 09990H 09990H OOOOOH MEMORY MEMORY 09990H 09B8FH 00200H STACK STACK 09B90H OD4C9H 0393AH DATA DATA DGROUP 0D4D0H OD5F6H 00127H DATA DATA AREA 0D600H ODC61H 00662H OVERUY DATA DATA 0DC62H 0DC6AH 00009H EINQQQ DATA 0DC70H ODEEFH 00280H COMADS COMADS ODEFOH OE7FBH 0090CH CONST CONST
Figure 3.4 Linker List using MS Overlay Linker OE8OOH OE81FH 00020H XB9$A $XB9 0E82OH 0E86FH 00050H XB8$A $XB8 0E870H 0EA1FH OOIBOH XB7$A $XB7 0EA20H 0EA2FH OOOIOH XB6$A $XB6 0EA30H 0EA7FH 00050H XB5$A $XB5 0EA80H 0EB8FH 00110H XB4$A $XB4 0EB90H 0EC1FH 00090H XB3$A $XB3 0EC20H 0EC3FH 00020H XB2$A $XB2 0EC40H OECBFH 00080H XB16$A $XB16 OECCOH OECEFH 00030H XB15$A $XB15 OECFOH 0F64FH 00960H XB13$A $XB13 0F650H 0F65FH OOOIOH XB12$A $XB1 0F660H 1073FH 010E0H XB11$A $XB11 10740H 1075FH 00020H XB10$A $XB10 10760H 107BFH 00060H XB1$A $XB1 107C0H 107CFH OOOIOH STL$A $STL 107D0H 138BFH 030F0H SHARE1$A $SHARE1 138C0H 138CFH OOOIOH PDTB$A $PUTB COMMON 138D0H 138EFH 00020H PRIO$A $PRI0 BLOCK 138F0H 138FFH OOOIOH OUT$A $OUT AREA 13900H 13A8FH 00190H 0RTB2S$A $0RTB2S 13A90H 13A9FH OOOIOH MODNUM$A $MODNUM 13AA0H 13AAFH OOOIOH MASKS4$A $MASKS4 13AB0H 13ACFH 00020H F428$A $F428 13ADOH 13AEFH 00020H F2943$A $F2943 13AF0H 13AFFH OOOIOH ESC1$A $ESC1 13B00H 13B0FH OOOIOH ERR$A $ERR 13B10H 13B1FH OOOIOH COMS$A $COMS 13B20H 23B1FH 10000H COMMQQ$A $COMMQQ 23B20H 30FDFH 0D4C0H COMMQQ$B $COMMQQ 30FE0H 30FEFH OOOIOH BSZ$A $BSZ 30FF0H 3108FH OOOAOH ALWAYS$A $ALWAYS 31090H 31090H OOOOOH HIMEM HIMEM 31090H 310DFH 00050H L~CAAA$A LARGE
Figure 3.4 Linker List using MS Overlay Linker(contd.) Overlay 1H 060F0H 08C44H 02B55H MPARS_ CODE Overlay 2H 060F0H 08BCEH 02ADFH SYPAR_ CODE Overlay 3H 060F0H 08361H 02272H SCANN_ CODE Overlay 4H 060F0H 09255H 03166H P42T4_ CODE Overlay 5H 060F0H 096B2H 035C3H COMSE_ CODE Overlay 6H 060F0H 0679AH 006ABH FINDS_ CODE Overlay 7H 060F0H 09987H 03898H EXEC_ CODE Overlay 8H 060F0H 08602H 02513H GETVE_ CODE Overlay 9H 060F0H 0791FH 01830H E29T2_ CODE Overlay AH 060F0H 08B54H 02A65H ONLY_ CODE Overlay BH 060F0H 060F4H 00005H BLKDQ_ CODE
Origin Group 00BE:0 CGROUP FE80:0 DGROUP
Figure 3.4 Linker List using MS Overlay Linker(contd.) CHAPTER 4
IMPLEMENTATION OF HPSIM II USING IBM PROFESSIONAL FORTRAN
4.1 Overview of Languages
There are three standards of Fortran in common use : Fortran 66, which is specified by the document ANSI X3.9-1966, and Fortran 77 and
Subset Fortran 77, both specified by the document ANSI X3.9-1978. The
Microsoft Fortran conforms to the Subset Fortran 77 as mentioned in chapter 3; the IBM Professional Fortran is a Full ANSI 77 Fortran language that operates under the IBM Personal Computer Disk Operating
System (DOS). The currently used IBM Professional Fortran is of version
1.0, designed by the Ryan-McFarland Corporation. It is supported to allow easy migration of mainframe-level programs and can only be used in
IBM personal computers. After version 1.0 appeared on the market, Ryan-
McFarland announced a new version, 1.1, which is more flexible than its predecessor and can work on different computers.
4.2 Differences between Microsoft Fortran and IBM Professional Fortran
Because different standards have been applied to the IBM
Professional Fortran and to the Microsoft Fortran, there are many differences between them. Some of those will be discussed in this section. The actual differences can be found in their User Guides and
Reference Manuals.
35 36
1. The currently used IBM Professional Fortran can only be run
under version 2.1 or later of the DOS operating system while
the Microsoft Fortran can be used under version 1.25 or later
of the Microsoft Disk Operating System or MS DOS compatible
systems.
2. The IBM Professional Fortran compiler requires at least 10 files
to be open at one time. This exceeds the default number for a
DOS configuration. Configuration specifications are contained in
a file called CONFIG.SYS. Besides that, the IBM Professional
Fortran needs to increase the number of buffers allocated by
DOS at system start up. ( The default value for the number of
open files is 8 and the default number of buffers is 2 ). A
disk buffer is a block of memory that DOS uses to hold data
being read from, or written to a disk (fixed disk or diskette),
when the amount of data being transferred is not an exact
multiple of the sector size. Microsoft Fortran can use the
defaults for those values, so it does not require modifying the
CONFIG.SYS file.
3. The version of Microsoft Fortran compiler being used can take
advantage of, but does not require, a math coprocessor ( 8087
for 8088,8086 CPU and 80287 for 80X86 CPU ). IBM Professional
Fortran does require the coprocessor.
A. The Microsoft Fortran compiler has three passes, although only
two of them are necessary to get the relocatable object code. 37
A successful run of pass one will generate two large
intermediate files which are about two or three times the
size of the source code. Thus it will take a longer time to
compile your programs because of changing diskettes, copying
files to different diskettes if you are going to compile many
modules and use the diskette as a storage medium. The IBM
Professional Fortran compiler is designed in one pass only.
5. The Full Fortran 77 (standard) does not allow character data
and integer data in the same common block. Hence, in IBM
Professional Fortran, if a common block includes any character
data, the entire block must contain character data. But
Microsoft Fortran allows character data and integer data in the
same common block.
6. In VAX-11 and Microsoft Fortran, when a hexadecimal or octal
constant is assigned to a variable or array element, the number
of digits that can be assigned depends on the data type of the
component. If the constant contains more digits than can be
stored, the constant is truncated on the left. But the IBM
Professional Fortran will detect this kind of dismatch, issue a
warning message at compile time and truncate to the right. Thus
they produce different results. Figure 4.1 shows the
differences between them.
7. The IBM Professional Fortran supports many generic functions,
such as bitwise OR, bitwise AND and bitwise SHIFT. One of these 38
generic functions, ISHL — a bitwise SHIFT function, has two
arguments. The first is the variable to be shifted, the second
specifies the direction of the shift. If the second argument is
larger than or equal to zero, then it does a left shift.
Otherwise, it performs a right shift. To take advantage
of the 16 data lines in 8086 and 80286, IBM Professional Fortran
has been designed such that the maximum amount of shift that
can be done at one time is 16. As described in the IBM
Professional Fortran Reference Manual , "The shift functions
(ISHL, ISHFT, ISHA and ISHL) have processor-dependent
results". Figures 4.2 and 4.3 show a general test of the shift
functions.
8. The Microsoft Fortran supports some metacommands which are used
to instruct the compiler to process Microsoft Fortran source
text in a specific way. For example, "$DEBUG", one of the
metacommands, will direct the compiler to (1) test integer
arithmetic for overflow and division by zero, (2) test assigned
GOTO values, (3) provide the runtime error-handling system with
source filenames and line numbers. If any runtime error occurs,
the filename and line number are displayed on the screen. In
IBM Professional Fortran, the only compiler directive is
INCLUDE. This command directs the compiler to proceed as
though the specified file were inserted at the point of the
INCLUDE. TEST1:
**************************************************************** * * * THIS IS A TEST FOR DATA INITIALIZATION * * IN IBM PROFESSIONAL FORTRAN * • * **************************************************************** PROGRAM TESDATA IMPLICIT INTEGER (A-Z) DATA ARGU/Z'OOOOOOOFF'/
WRITE(*,1) ARGU 1 1 FORMAT(IX1 ARGU=',15) STOP END
TEST1 RESULT:
ARGU= 15
TEST2: **************************************************************** • » * THIS IS A TEST FOR DATA INITIALIZATION * * IN MICROSOFT FORTRAN * * * **************************************************************** PROGRAM TESDATA IMPLICIT INTEGER (A-Z) DATA ARGU/#OOOOOOOFF/
WRITE(*,1) ARGU 1 F0RMAT(1X,'ARGU=',15) STOP END
TEST2 RESULT:
ARGU= 255
Figure 4.1 Different Data Initialization TEST3:
**************************************************************** * * * THIS IS A TEST PROGRAM THAT WILL TEST THE SHIFT FUNCTION • * * **************************************************************** PROGRAM TSHIFT IMPLICIT INTEGER (A-Z) DATA ARGU/1/
DO 11 1-1,20 RESULT- ISHL(ARGU.I) WRITE(*,2) I,ARGU,RESULT 2 FORMAT(IX, *SHIFT NUMBER-',13,' ARGU-',13,* RESULT-*, - 115) 11 CONTINUE STOP END
TEST RESULTS:
SHIFT NUMBER® 1 ARGU- 1 RESULT- 2 SHIFT NUMBER- 2 ARGU- 1 RESULT- 4 SHIFT NUMBER- 3 ARGU- 1 RESULT- 8 SHIFT NUMBER- 4 ARGU- 1 RESULT- 16 SHIFT NUMBER- 5 ARGU- 1 RESULT- 32 SHIFT NUMBER- 6 ARGU- 1 RESULT- 64 SHIFT NUMBER- 7 ARGU- 1 RESULT- 128 SHIFT NUMBER- 8 ARGU- 1 RESULT- 256 SHIFT NUMBER- 9 ARGU- 1 RESULT- 512 SHIFT NUMBER- 10 ARGU- 1 RESULT- 1024 SHIFT NUMBER- 11 ARGU- 1 RESULT- 2048 SHIFT NUMBER- 12 ARGU- 1 RESULT- 4096 SHIFT NUMBER- 13 ARGU- 1 RESULT- 8192 SHIFT NUMBER- 14 ARGU- 1 RESULT- 16384 SHIFT NUMBER- 15 ARGU- 1 RESULT- 32768 SHIFT NUMBER- 16 ARGU- 1 RESULT- 65536 SHIFT NUMBER- 17 ARGU- 1 RESULT- 0 SHIFT NUMBER- 18 ARGU- 1 RESULT- 0 SHIFT NUMBER- 19 ARGU- 1 RESULT- 0 SHIFT NUMBER- 20 ARGU- 1 RESULT- 0
Figure 4.2 First Test of Shift Function TEST 4:
* * * THIS IS A TEST PROGRAM THAT WILL TEST THE SHIFT FUNCTION * • •
PROGRAM TSHIFT IMPLICIT INTEGER (A-Z) DATA ARGU/1024/
DO 11 1=1,20 RESULT- ISHL(ARGU.I) WRITE(*,2) I,ARGU,RESULT 2 FORMAT(IX,'SHIFT NUMBER-1,13,' ARGU*',16,* RESULT-', - 115) 11 CONTINUE STOP END
TEST RESULTS:
SHIFT NUMBER- 1 ARGU- 1024 RESULT- 2048 SHIFT NUMBER- 2 ARGU- 1024 RESULT- 4096 SHIFT NUMBER- 3 ARGU- 1024 RESULT- 8192 SHIFT NUMBER- 4 ARGU- 1024 RESULT- 16384 SHIFT NUMBER- 5 ARGU- 1024 RESULT- 32768 SHIFT NUMBER- 6 ARGU- 1024 RESULT. 65536 SHIFT NUMBER- 7 ARGU- 1024 RESULT- 131072 SHIFT NUMBER- 8 ARGU- 1024 RESULT- 262144 SHIFT NUMBER- 9 ARGU- 1024 RESULT- 524288 SHIFT NUMBER- 10 ARGU- 1024 RESULT- 1048576 SHIFT NUMBER- 11 ARGU- 1024 RESULT- 2097152 SHIFT NUMBER- 12 ARGU- 1024 RESULT- 4194304 SHIFT NUMBER- 13 ARGU- 1024 RESULT- 8388608 SHIFT NUMBER- 14 ARGU- 1024 RESULT- 16777216 SHIFT NUMBER- 15 ARGU- 1024 RESULT- 33554432 SHIFT NUMBER- 16 ARGU- 1024 RESULT- 67108864 SHIFT NUMBER- 17 ARGU- 1024 RESULT- 0 SHIFT NUMBER- 18 ARGU- 1024 RESULT- 0 SHIFT NUMBER- 19 ARGU- 1024 RESULT- 0 SHIFT NUMBER- 20 ARGU- 1024 RESULT- 0
Figure 4.3 Second Test of Shift Function 42
9. The Microsoft Fortran supports two versions of linker, general
linker and overlay linker while there is only one linker for the
IBM Professional Fortran compiler.
10. There is an interactive symbolic debugging program to help
resolve runtime errors in programs, written in the IBM
Professional Fortran. Because it is a symbolic debugger, we
can easily examine or change the values of variables, arrays
and array elements; this increases the overall efficiency of
program debugging. Microsoft Fortran also supports a debugging
program, but it is a low-level debugger. This debugger can be
an aid for debugging of assembly language routines, but is not
good for Fortran unless you know where variables are in
memory because it can only examine or change the values of the
registers. CHAPTER 5
SOME TEST CASES
To verify the correctness and the effectiveness of a software
package is a serious and tedious job, especially for the first
implementation of it. Because the HPSIM II has been implemented on the
CDC-6400, DEC-10 and VAX-750, the verification of this new version of
HPSIM II on the different computers can be done by comparing test
results to those of the existing version. In this chapter, some of the
tests are shown. These tests include a short time period simulation and
a long time period simulation. Because of limitations in the hardware
and software, long time period simulation is needed to verify the feasibility of this new version of HPSIM on different personal computers. In addition, the diagnostics of the HPSIM II are checked
using tests with incorrect syntax.
5.1 A Simple Multiplier Circuit
The simple multiplier circuit described in the User Manual for
HPSIM and HPCOM has nine input lines and nine output lines as shown in
Figure 5.1.
During the reset state the multiplier will wait for a "1" on the
line "DATAREADY", which indicates that data are on the "INPUTBUS" lines. The four most significant bits of "INPUTBUS" constitute the
43 DATAREADY INPUTBUS INPUTBUS
AC2
ADDER
EXTRA ACl
COUNTER
DONE RESULT RESULT
Figure 5.1 The Multiplier Block Diagram 45 first operand and the other four constitute the second operand. When the operands are accepted, the "BUSY" flip-flop is set to "1" and the multiplier starts the multiplication. When done, "BUSY" is reset back to "0", and the eight bits output is placed on the eight "RESULT" lines and the "DONE" flip-flop is set to "1". Then the multiplier goes to the reset state waiting for another set of input data. Figure 5.2 shows the input files for this multiplier.
AHPL SEQUENCE FILE: AHPLMODULE:MULTIPLIER. MEM0RY:AC1[4]; AC2[A]; C0UNT[2]; EXTRA[5]; BUSY. EXINPUTS:DATAREADY. EXBUSES:INPUTBUS[8]. OUTPUTS:RESULT[8]; DONE. CLUNITS:INC[2](COUNT); ADD[5](EXTRA[1:A];AC2).
1 AC1.AC2 <« INPUTBUS[0:3],INPUTBUS[4:7]; EXTRA <= 5$0; => (ADATAREADY)/(1). 2 BUSY <- \1\; -> (*ACl[3])/(4). 3 EXTRA <- ADD[0:4](EXTRA[1:4];AC2). 4 EXTRA,AC1 <» \0\,EXTRA,AC1[0:2]; COUNT O INC(COUNT); -> (*(&/C0UNT))/(2). 5 RESULT - EXTRA[1:4],AC1; DONE « \1\; BUSY <- \0\; -> (1). ENDSEQUENCE CONTROLRESET(l). END.
AHPL COMMUNICATION FILE: OPTION 0. CLOCKLIMIT 30. EXLINES INPUTBUS-'37, '32, '32, 'B2, '32#4, 'B2, '32#5, •BF, '13, '98, 'D9, '13, 'DA, »10, *00; DATAREADY-0#3, 1, 0113, 1, 0. OUTPUTS DATAREADY; INPUTBUS; BUSY; DONE; EXTRA; AC1; AC2; COUNT; RESULT.
Figure 5.2 HPSIM II Input Files for Multiplier 46
5.2 Random Process Monitor
This random sequence generator is driven by an external clock source. It provides a level, z, which is constant between clock pulses, and may or may not change, on a random basis, when triggered by a clock pulse or leading edge of a one-period level. This random process monitor works on a clock frequency of 1 MHz and provides an output clock to drive the random process at a frequency of 100 KHz. The designed monitor will compute the number of level changes in the random process each second and it will also compute the average number of level changes per 160 microsecond period over the first 16 such periods following the depression of the start button. Figure 5.3 shows the system block diagram.
start
RANDOM RANDOM output PROCESS PROCESS GENERATOR MONITOR
100 KHz Clock
Figure 5.3 Random Process Monitor To test the limitations of hardware and software on personal computers, I used two different AHPL descriptions of the random process monitors. The first is for a medium time period simulation (170 clock periods) and the other is for a long time period simulation (2600 clock periods). Figures 5.4 and 5.5 show these two input files. 48
AHPL SEQUENCE FILE: AHPLMODULE:RANPRO. EXINPUTS:Z;START. OUTPUTS:TRIG;AVEOUT[4] ;OUTREADY. MEMORY:Y;CNT1[4) ;CNT2[8] ;CNT3[8]. CLUNITS: INC 1 [ 4] ( CNT 1) ; INC2 [ 8] ( CNT2) ; INC3 [ 8] ( CNT3).
1 •>(1). ENDSEQUENCE CONTROLRESET(1); CNT2 * START <• 8$0; CNT3 * START <= 8$0; CNT1 <• (INC1(CNT1) ! 4$0) * (A(CNT1[0] & CNT1[3]) , (CNT1[0] & CNT1[3])); TRIG. A(+/CNT1); Y * TRIG <• Z; CNT2 * (TR G & (Y@Z)) <• INC2(CNT2); CNT3 * TR 1~ <= INC3(CNT3); OUTREADY • &/CNT3; , AVEOUT • CNT2[0:3] * (&/CNT3). END.
AHPL COMMUNICATION FILE: OPTION 0. CLOCKLIMIT 170. EXLINES START• 0, 1, 0#18, 0#180; Z·0#9,1#10,0#10,1#10,0#10,1#10,0#10,1#10,0#10,1#10, 0#10,1#10,0#20,1#10,0#10,1#10,0#10,1#10,0#10,1#10, 0#10,1#10,0#10,1#10,0#10,1#20,0#10,1#10,0#10,1#10, 0#10,1#10,0#10,1#10,0#10,1#10,0#20,1#10,0#10,1#10, 0#10,1#10,0#10,1#10,0#10,1#10,0#10,1#10,0#10,1#10, 0#10,1#10,0#10,1#10,0#10,1#10,0#10,1#10,0#10,1#10, 0#90,1#10,0#10,1#10,0#10,1#10,0#10,1#10,0#10,1#10, 0#10,1#10,0#90,1#10,0#10,1#10,0#10,1#10,0#10,1#10, 0#10,1#10~0#10,1#10,0#20,1#10,0#10,1#10,0#10,1#10, 0#10,1#10,0#10,1#10,0#10,1#10,0#10,1#10,0#10,1#10, 0#10,1#10,0#10,1#10,0#10,1#10,0#10,1#10,0#10,1#10, 0#10,1#10,0#10,1#10,0#10,1#10,0#10,1#10,0#10,1#10, . 0#10,1#10,0#10,1#10,0#10,1#10,0#10,1#10,0#10,1#10, 0#10,1#10,0#10,1#10,0#10,1#10,0#10,1#10,0#10,1#10, 0#10,1#10,0#10,1#10,0#10,1#10,0#10,1#10,0#10,1#10, 0#10,1#10,0#10,1#10,0#10,1#10,0#10,1#10,0#10,1#10, 0#10,1#10,0#10,1#10,0#10,1110,0#10,1#10,0#10,1# 10, 0#10,1#10,0#10,1#10,0#10,1#10,0#10,1 # 10,0#10,1#10, 0#10,1#10,0#10,1#10,0#10,1#10,0#10,1#10,0#10,1#10, 0#10,1#10,0#10,1#10,0#10,1#10,0#10,1#10,0#10,1#10, 0#10,1#10,0#10,1#10,0#10,1#10,0#10,1#10,0#10,1#10, 0#10,1#10,0#10,1#10,0#10,1#10,0#10,1#10,0#10,1#10, Otl0,1#10,0#10,1#10,0#10,1#10,0#10,1#10,0#10,1#10, 0#:0,1#10,0#10,1#10,0#10,1#10,0#10,1#10,0#10,1#10, 0#10,1#10,0#10,1#10,0#10,1#10,0#10,1#10,0#10,1#10, 0#10,1#10,0#20,1#10,0#10,1#10,0#10,1#10,0#10,1#9. OUTPUTS Z; START; TRIG; Y; CNT1; CNT2; CNT3; OUTREADY; AVEOUT.
Figure 5.4 First Design of Random Sequence Monitor AHPL SEQUENCE:
AHPLMODULE:RANPRO. FYTNPI1T9 • 7 •
1 FLAG <= 8$0; SUM <= 9$0; COUNTB <= 8$0; => (ASS,SS)/(1,2). 2 => (ATRIG,TRIG)/(2,3). 3 STATUS <= STATUS[1], Z; COUNTB <= INC1(COUNTB). 4 FLAG[7] <= STATUS[0] @ STATUS[1]. 5 SUM <= ADD[0:8](SUM[1:8]; FLAG); => (A(&/COUNTB),&/COUNTB)/(2,l). ENDSEQUENCE CONTROLRESET(1); C <= (INC3(C) ! 4$0) *(A(C[0]&AC[1]&AC[2]&C[3]), C[0]&AC[1]&AC[2]&C[3]); TRIG <= (\0\ ! \1\) * (A(C[0]&AC[l]&AC[2]&C[3j), C[0]&AC[1]&AC[2]&C[3]); SS <= (\1\ ! \0\) * (START, ASTART); AVEOUTl = SUM[1:4]; AVEOUT2 = SUM[5:8]. END.
AHPL COMMUNICATION FILE:
OPTION 7. CLOCKLIMIT 2600. EXLINES Z=0*TRIG,0»TRIG,1*TRIG,0*TRIG,1»TRIG,0*TRIG, 1*TRIG,0*TRIG,0*TRIG,1+TRIG,0*TRIG,1*TRIG, 0*TRIG,1*TRIG,0*TRIG,1*TRIG,1*TRIG,0*TRIG, 1*TRIG,0*TRIG,1*TRIG,0*TRIG,1»TRIG,1*TRIG, l*TRiG,112600; START=*0,0,1#2600. OUTPUTS SUM; AVEOUTl; AVE0UT2; TRIG; Z; FLAG. SUPPRESS 1/1;1/2;1/4;1/5.
Figure 5.5 Second Design of Random Sequence Monitor CHAPTER 6
ANALYSIS OF RESULTS
An important aspect of the simulation is the speed at which the simulation is performed. To be effective, the simulator must operate at a speed which is fast enough to allow the economical simulation of large problems. There are three working versions of HPSIM II that can run on the personal computers. These are — the MS version (using the
Microsoft Fortran compiler and general linker), the MS overlay version
(using the Microsoft Fortran compiler and overlay linker) and the IBM version (using the IBM Professional Fortran compiler). This chapter compares the test results using different version of HPSIM II on different personal computers. There are six test results will be discussed in this chapter. TEST 1 and TEST 2 use the multiplier circuit as a test running for a period of 30 and 40 clock cycles, respectively.
Test 3 simulates the one step random process monitor for a 170 clock cycle period while TEST 4 runs for 2600 clock cycles period using the second (5 step) design for this random process monitor. Test 5 and Test
6 both contain syntax errors to test the diagnostic ability of the HPSIM
II. Those personal computers being used include IBM PC, IBM AT and ITT
XTRA PC. An explanation of the differences amoung these results is also given in this chapter.
50 6.1 Running HPSIM II on IBM PC
The microprocessor used in the IBM PC is the INTEL 8088 which
features an 8-bit external data path and an internal 16-bit
architecture; the address path of the 8088 and 8086 is 20 lines. The
currently used 8088 microprocessor in the IBM PC is working on a 4.77
KHz system clock. This frequency, which is derived from a 14.31818-MHz
crystal, is divided by 3 for the processor clock. Because of the 20
lines of the address path, the 8088 can only support a direct addressing capability of up to 1 Mbytes of memory. The system memory map for a
64/256K system board is shown in Figure 6.1. From this figure we can see that the amount of the RAM (Random Access Memory) in the IBM PC
under the support of PC DOS can only be expanded to 640 Kbytes.
The IBM PC can have either one fixed disk drive and one diskette drive or two diskette drives. The capacity of a double-sided and double density diskette is 360 Kbytes with a 9 sectors/track format or 320
Kbytes with a 8 sectors/track format. Different versions of PC DOS support different disk (or diskette) formats. Table 6.1 shows the specification of different diskettes and the supporting operating systems for the IBM PC family of machines. The fixed disk and the diskette are the important storage media for the personal computers. A good disk (or diskette) performance is vital to the operation of the personal computers. There are four physical factors determining overall disk performance: access time, cylinder size, transfer rate and average latency. Access time is the amount of time it takes to move the 0
64-256K READ/WRITE MEMORY ON SYSTEM BOARD
UP TO 384K READ/ WRITE MEMORY IN I/O CHANNEL
UP TO 384K IN I/O CHANNEL
Monochrome
128K RESERVED
Color/Graphics
Fixed Disk Control 192K ROM EXPANSION AND CONTROL
RESERVED
48K BASE SYSTEM ROM
Figure 6.1 System Memory Map for 64/256K System Board Table 6.1 Specification Data of Diskette Types for IBM PC
FAT BYTE FE FF FC FD F9
NUMBER OF SIDES 1 2 1 2 2
NUMBER OF TRACKS 40 40 40 40 80
SECTORS/ TRACK 8 8 9 9 15
TOTAL SECTORS AVAILABLE 320 640 360 720 2400
DIRECTORY SECTORS 4 7 4 7 14
DIRECTORY ENTRIES 64 112 64 112 224
SECTORS/ CLUSTER 1 2 1 2 1
OPERATING SYSTEM 1.0,1.1 1.1,2.0 2.0,2.1 2.0,2.1 SUPPORTED 2.0,2.1 2.1,3.0 3.0,3.1 3.0,3.1 3.0,3.1 UNDER 3.0,3.1 3.1
Note: FAT — File Allocation Table Table 6.2 Transfer Rate of Disk-Drive for IBM PC
ROTATION BASE RATE INTERLEAVE ACTUAL RATE BITS/SECOND BYTES/SECOND
PC XT FLOPPY DIS 300RPM 250K NONE 31250
AT 360KBYTE FLOPPY DISK 360RPM 300K NONE 37500
AT 1.2MBYTE FLOPPY DISK 360RPM 500K NONE 62500
PC XT HARD DISK 3600RPM 5M 6 104167
PC AT HARD DISK 3600RPM 5M 3 208333
PC AT HARD DISK 3600RPM 5M 2 312500 55
read/write head to the desired track (cylinder) and normally includes
the settling time. This is the time required to settle down the
read/write head from the moving height to the read/write height after
the head has been moved to the desired track. A cylinder is composed of
all tracks that are under the read/write heads at one time. Transfer
rate is the rate at which data comes off the disk. The average latency
is the time required for a disk to spin one-half of a revolution. Table
6.2 shows the data transfer rate of the disk-drive for the IBM personal
computers. The interleave factor is used to cut down the effective data
transfer rate.
As mentioned in Chapter 4, the IBM Professional Fortran compiler
does require a math coprocessor. The currently used IBM PC has two set
of diskette drives and does not have the 8087 coprocessor so that only
the MS version and MS overlay version of HPSIM II can be run on it.
The test results from running on the IBM PC and the VAX-750 are shown on
Table 6.3 as a comparison. From this table, we see that the MS overlay
version takes a very long time to run even for a small test. Despite
the fact that the overlay structure can be changed to get a better
performance, it is still not a practical way to run the simulation.
Hence TEST 3, TEST 4 were not run on the MS overlay version of HPSIM II.
6.2 Running HPSIM II on IBM AT
The microprocessor used in the IBM AT is the INTEL 80286 which is an upgrade version of the 8086 that is designed for use with multiuser Table 6.3 Test Results on IBM PC and VAX 750
TEST 1 TEST 2 TEST 3 TEST 4 TEST 5 TEST 6
CASE 1 5 7 29 445 3 3
CASE 1 4 4.5 27 407 2.5 2.6
CASE 2 7 8 33 490 3 3
CASE 2 4 4.5 27 406 2.5 2.6
CASE 3 8 9 53 900 3 4
CASE 3 4 4.4 27 420 2.5 2.6
CASE 4 27 32 254 4123 12 12
CASE 5 16417 19961 7638 8168
NOTES: 1. UNITS IN SECOND. 2. THE FIRST ROW OF CASE 1, CASE 2 AND CASE 3 ARE SIMULATION TIMES, SECOND ROW OF THOSE CASES ARE THE CPU TIMES WHILE USING VAX 750 ON DIFFERENT SYSTEM LOADS. 3. CASE 4 RUNNING MS VERSION ON IBM PC 4. CASE 5 RUNNING MS OVERLAY VERSION ON IBM PC and multitasking operating systems. The 80286 has 24 address lines and
16 data lines; it is a true 16>bit microprocessor and in the AT is
clocked at 6 MHz. It is substantially faster than the 8086. There are a
number of factors why the AT exceeds the PC's performance. First, the
80286 clock rate is 6 MHz while the PC's 8088 clock rate is 4.77 MHz.
Therefore, even if everything else were comparable between these two
systems, the AT would still be run about 26 percent faster than the PC.
Second, the AT has a 16-bit data bus; the PC has an 8-bit data bus.
Using an 8-bit bus for a 16-bit microprocessor will cost 15 to 20
percent in system performance. Third, the 80286 has four internal units
that each independently do a piece of the total processing job, in
comparison the 8086 has two independent units. When combined with the
additional hardware speedup of some instructions and internal bus and
clock speed enhancements, these features cause the 80286 to run between
two and six times faster than the PC's 4.77 MHz 8088.
The 80286 supports two modes of operation, real and protected. In
protected address mode the 80286 can address 16 megabytes of memory and
manage a virtual address space of one gigabyte.
There are two models of the IBM AT: the Base model and the Enhanced
model. The Enhanced model includes: one 20 MB fixed disk drive, one
quad-density drive, one dual-sided and double density diskette drive and
512 Kbytes of RAM. The base model constitutes: one quad-density drive, one dual-sided and double density diskette drive and 256 Kbytes of RAM.
Table 6.4 shows the specification of the fixed-disk and the supporting Table 6.A Specification Data of Fixed Disk Types for IBM XT AT
FAT BYTE F8 F8 F8
NUMBER OF SIDES 4 4 4
NUMBER OF TRACKS 306 306 615
SECTORS/ TRACK 17 17 17
TOTAL SECTORS AVAILABLE 20723 20723 41735
DIRECTORY SECTORS 32 32 32
DIRECTORY ENTRIES 512 512 512
SECTORS/ CLUSTER 8 8 4
OPERATING SYSTEM 2.0,2.1 2.0,2.1 SUPPORTED 3.0,3.1 3.0,3.1 3.0,3.1 UNDER
Note: FAT — File Allocation Table 59
operating system for the IBM XT and AT. The RAM size can be expanded to
3 Mbytes of primary memory for these two models.
The currently used IBM AT is an Enhanced model with a math coprocessor (INTEL 80287) in its system unit. This allows the use of
IBM Professional Fortran, which needs a math coprocessor. Therefore all three versions of HPSIM II can run on this IBM AT. The test results are shown on Table 6.5. CASE 1, CASE 2 and CASE 3 on Table 6.5 show the test results on the VAX-750 under different system loads. We can easily see that the required time period to run a program on main frame machines is highly dependent on the system load. This time-dependent factor can be overcome by using personal computers for the same task.
CASE 4 and CASE 5 shows the test results using the IBM Professional
Fortran compiler and different storage media, i.e., the fixed disk and the diskette. CASE 6 and CASE 7 shows the test results using the MS version of HPSIM II. There are several factors that cause the differences in simulation speed between them. The AT's fixed disk has a data transfer rate that is about six times that of AT's diskette, as shown on Table 6.2. The average access time for the AT's fixed disk is
40 ms and for AT's diskette is 91 ms. The latency time of AT's diskette is 100 ms while the AT's fixed disk is 8.33 ms.
While comparing CASE 4 of Table 6.3 with CASE 6 of Table 6.5, we can also see that the IBM AT runs about two to four times faster than the IBM PC which falls into the range of two to six as mentioned above. Table 6.5 Test Results on IBM AT and VAX 750
TEST 1 TEST 2 TEST 3 TEST 4 TEST 5 TEST 6
CASE 1 5 7 29 445 3 3
CASE 1 4 4.5 27 407 2.5 2.6
CASE 2 7 8 33 490 3 3
CASE 2 4 4.5 27 406 2.5 2.6
CASE 3 8 9 53 900 3 4
CASE 3 4 4.4 27 420 2.5 2.6
CASE 4 21 25 172 2695 13 14
CASE 5 31 39 218 2820 19 20
CASE 6 7 9 72 1279 3 3
CASE 7 10 12 80 1285 6 5
NOTES: 1. UNITS IN SECOND. 2. THE FIRST ROW OF CASE 1, CASE 2 AND CASE 3 ARE SIMULATION TIMES, SECOND ROW OF THOSE CASES ARE THE CPU TIMES WHILE USING VAX 750 ON DIFFERENT SYSTEM LOADS. 3. CASE 4 AND CASE 5 RUNNING IBM VERSION AND USING FIXED DISK, DISKETTE AS STORAGE MEDIA ON IBM AT 4. CASE 6 AND CASE 7 RUNNING MS VERSION AND USING FIXED DISK, DISKETTE AS STORAGE MEDIA ON IBM AT 6.3 Running HPSIM II on ITT XTRA PC
The ITT XTRA PC is compatible with IBM personal computers. It also
uses the INTEL 8088 as its microprocessor which works on a 5 MHz of
system clock. The ITT XTRA PC runs under the DOS operating system which
was developed by Microsoft.
The currently used ITT XTRA PC has one diskette drive and one 10
Mbyte fixed disk drive but does not have the math coprocessor. Hence,
to test the feasibility of HPSIM II, I ran the MS version of HPSIM II on
the ITT XTRA PC.
6.4 Summary of Results
Table 6.6 shows all test results on all computers I used, i.e., IBM
PC, IBM AT and ITT XTRA PC. All these personal computers at least have
a 512K bytes memory. Although the IBM Professional Fortran does require
the math coprocessor for floating-point number manipulation, we do not
gain any advantage from using it because there are no floating-point
operations in HPSIM II. By comparing the test results from IBM
Professional Fortran and Microsoft Fortran running on IBM AT, we can see
that the IBM Professional Fortran is not more efficient than the
Microsoft Fortran.
From Table 6.2, we can see that the data transfer rate in the fixed
disk is faster than in diskette for IBM AT. This explains why the simulation on the IBM fixed disk runs faster than on the IBM diskette.
The overhead for disk I/O will be a small percentage of the running time 62 for a long simulation while it will take a large percentage of the running time for a small simulation.
The ITT XTRA PC is an IBM PC compatible machine. While the ITT runs with a 5 MHz system clock, the IBM PC runs with a 4.77 MHz clock.
From Table 6.6 we can see that even the ITT XTRA PC runs a system clock faster than the IBM PC, it is still not more efficient than the IBM PC. Table 6.6 Summary of Test Results
TEST 1 TEST 2 TEST 3 TEST 4
AVERAGE VAX CPU TIME 4 4.5 27 411
IBM PROFESSIONAL FORTRAN ON IBM AT FIXED DISK 21 25 172 2695
IBM PROFESSIONAL FORTRAN ON IBM AT DISKETTE 31 39 218 2820
MICROSOFT FORTRAN ON IBM AT FIXED DISK 7 9 72 1279
MICROSOFT FORTRAN ON IBM AT DISKETTE 10 12 80 1285
MICROSOFT FORTRAN ON IBM PC DISKETTE 27 32 254 4123
MICROSOFT FORTRAN OVERLAY ON IBM PC DISKETTE 16417 19961
MICROSOFT FORTRAN ON ITT XTRA PC DISKETTE 28 32 284 5001
MICROSOFT FORTRAN ON ITT XTRA PC HARD DISK 24 29 225 4026
NOTES: 1. UNITS IN SECOND. CHAPTER 7
CONCLUSION
Simulation is every important to most designs. To have a good performance in simulation, you need a good simulation language and a suitable tool (machine) to support it. The most prominent disadvantage of using the personal computer is the speed. In fact, the personal computer runs much slower than in the main frame machine. But after considering these factors — the cost of computers, system loads on computers and portability, it is reasonable to run the HPSIM II on the personal computer. There are only two requirements for running the
HPSIM II on personal computers — an IBM compatible personal computer and a KAM size in the personal computer of at least 512 Kbytes.
64 APPENDIX A
8088 ASSEMBLY UNGUAGE SUBROUTINES
65 **************************************************************** • • * BITWISE "AND" FUNCTION • • * ****************************************************************
NAME HPSMFUN DATA SEGMENT PUBLIC 'DATA 1 EIGHT DB 8 DATA ENDS DGROUP GROUP DATA CODEl SEGMENT •CODE' ASSUME CS:CODEl,DS:DGROUP,SS:DGROUP PUBLIC ASMAND ASMAND PROC FAR PUSH BP MOV BP.SP LES BX,DWORD PTR [BP + 10] MOV AX,ES:[BX] MOV DX,ES:[BX]+2 LES BX,DWORD PTR [BP + 6] AND AX,ES:[BX] AND DX,ES:[BX]+2 MOV SP,BP POP BP RET 08H ASMAND ENDP CODEl ENDS **************************************************************** • * » BITWISE "OR" FUNCTION • * * ****************************************************************
CODE2 SEGMENT •CODE' ASSUME CS:CODE2,DS:DGROUP,SS:DGROUP PUBLIC ASMOR ASMOR PROC FAR PUSH BP MOV BP,SP LES BX,DWORD PTR [BP + 10] MOV AX,ES:[BX] MOV DX,ES:[BX]+2 LES BX,DWORD PTR [BP + 6] OR AX,ES:[BX] OR DX,ES:[BX]+2 MOV SP,BP POP BP RET 08H ASMOR ENDP CODE2 ENDS * * * BITWISE "XOR" FUNCTION * * * *****************************************************************
CODE3 SEGMENT •CODE' ASSUME CS:CODE3,DS:DGROUP,SS:DGROUP PUBLIC ASMXOR ASMXOR PROC FAR PUSH BP MOV BP.SP LES BX,DWORD PTR [BP + 10] MOV AX,ES:[BX] MOV DX,ES:[BX]+2 LES BX,DWORD PTR [BP + 6] XOR AX,ES:[BX] XOR DX,ES:[BX]+2 MOV SP.BP POP BP RET 08H ASMXOR ENDP CODE3 ENDS * • * BITWISE SHIFT RIGHT FUNCTION * • • *****************************************************************
CODE4 SEGMENT 'CODE* ASSUME CS:C0DE4,DS:DGROUP,SS: PUBLIC RSHIFT RSHIFT PROC FAR PUSH BP MOV BP.SP LES BX,DWORD PTR [BP + 10] MOV AX(ES:[BX] MOV DX,ES:[BX]+2 LES BX,DWORD PTR [BP + 6J MOV CX,ES:[BX] JCXZ SKIP1 MOV BX,AX MOV AX.CX DIV EIGHT MOV CX.AX MOV AX,BX LOOPl: MOV AL.AH MOV AH.DL MOV DL.DH XOR DH,DH LOOP LOOPl SKIP1: MOV SP,BP POP BP RET 08H RSHIFT ENDP CODE4 ENDS **************************************************************** * * * BITWISE SHIFT LEFT FUNCTION * * * ****************************************************************
CODE5 SEGMENT •CODE' ASSUME CS:CODE5,DS:DGROUP,SS:DGROUP PUBLIC LSHIFT LSHIFT PROC FAR PUSH BP MOV BP.SP LES BX,DWORD PTR [BP + 10] MOV AX,ES:[BX] MOV DX,ES:[BX]+2 LES BX,DWORD PTR [BP + 6] MOV CX,ES:[BX] JCXZ SKIP MOV BX.AX MOV AX.CX DIV EIGHT MOV CX.AX MOV AX,BX LOOP2: MOV DH.DL MOV DL.AH MOV AH.AL XOR AL.AL LOOP LOOP2 SKIP: MOV SP.BP POP BP RET 08H LSHIFT ENDP CODE5 ENDS **************************************************************** * * » BITWISE SHIFT RIGHT FUNCTION * * * ****************************************************************
CODE6 SEGMENT 'CODE* ASSUME CS:CODE6,DS:DGROUP,SS:DGROUP PUBLIC RRSHFT RRSHFT PROC FAR PUSH BP MOV BP,SP LES BX,DWORD PTR [BP + 10] MOV AX,ES:[BX] MOV DX,ES:[BX]+2 LES BX,DWORD PTR [BP + 6] MOV CX,ES:[BX] JCXZ SKIP6 L00P3: MOV BX.AX MOV AX.DX SHR AX,1 MOV DX.AX MOV AX.BX RCR AX,1 LOOP LOOP3 SKIP6: MOV SP.BP POP BP RET 08H RRSHFT ENDP C0DE6 ENDS **************************************************************** * » * BITWISE SHIFT LEFT FUNCTION * * * ****************************************************************
CODE7 SEGMENT 'CODE' ASSUME CS:CODE7,DS:DGROUP,SS:DGROUP PUBLIC LLSHFT LLSHFT PROC FAR PUSH BP MOV BP,SP LES BX,DWORD PTR [BP + 10] MOV AX,ES:[BX] MOV DX,ES:[BX]+2 LES BX,DWORD PTR [BP + 6] MOV CX,ES:[BX] JCXZ SKIP7 LOOPA: SHL AX,1 MOV BX.AX MOV AX.DX RCL AX,1 MOV DX.AX MOV AX.BX LOOP LOOPA SKIP7: MOV SP,BP POP BP RET 08H LLSHFT ENDP CODE7 ENDS REFERENCES
1. P. Kozak, H.K. Gummel and B.R. Chawla, "Operational Feature of an MOS Timing Simulator". 12th Design Automation Conference
2. Hill, F. J. and Gerald R. Peterson "Digital Systems: Hardware Organization and Design" 2nd ED. Wiley, New York, 1978
3. Iverson, K. E. "A Programming Language" Wiley, New York, 1962
4. Navabi, Z. "Hardware Program Simulator" Department of Electrical Engineering, University of Arizona, Tucson, 1978
5. Navabi, Z. "User Manual for HPSIM and HPCOM" Department of Electrical Engineering, University of Arizona, Tucson, 1978
6. Irwin Jacob Robinson "The Design and Simulation of A Parallel Processor Using HPSIM" Department of Electrical Engineering, University of Arizona, Tucson, 1978
73