Zeichen Journal ISSN No: 0932-4747

A Novel Approach of Merging Serial and Parallel to Enhance Performance on FPGA Ms. Joella Lobo1 and Prof. Sonia Kuwelkar2 1 Student of Maters (Microelectronics), Goa college of Engineering, Farmagudi, Goa India. 2Assistant Professor, Goa college of Engineering, Farmagudi, Goa India.

Abstract: of data is an operation employed in numerous applications and plays a vital role in determining the overall performance, speed, and power. Sorting arranges the data in a particular order. Most previous research on sorting units has focused on implementing the algorithms on software. These require a lot of operational cycles and a large number of iterations. This emphasizes the need for an external sorting unit. FPGA is one of the most commonly used hardware unit for highspeed applications. Numerous sorting techniques have been studied such as the , Quick Sort, , , , Sort, etc. Out of these, the Merge sort works the best when sorting huge data sets and bubble sort works best for a small data set. In this paper, some of these sorting algorithms namely serial merge sort, parallel merge sort, bitonic merge sort, oddeven merge sort, the modified merge sort, serial bubble sort, and odd-even transportation sort are analyzed and comparison based on resource utilization, delay, clock cycles, power and area are made by implementing them on the FPGA. Based on the requirement of the application, the appropriate can be selected. Keywords: FPGA, , sort algorithms, parallel soring,

1. Introduction

Sorting operation arranges a list of data in a particular order which is required by most of the computing applications nowadays [1] . It is easier to manipulate and search data that is in order, thus many other algorithms require that the data is sorted [15]. Sorting is frequently used in modern scientific computing and in commercial data processing. Some of the examples are transaction processing [29], linguistics [30], combinatorial optimization [5], image processing [8], Color sorting [19] weather prediction [14], astrophysics, etc. For many year’s is facing computational problems in sorting of a huge amount of data [4]. Many applications having large databases require faster and better sorting algorithms to yield optimum results. Therefore, we need to increase parallelism so that we can implement efficient sorting primitives [13][20].

Numerous sorting techniques have been studied such as the Bubble Sort, Quick Sort, Selection Sort, Insertion Sort, Merge Sort, Heap Sort, etc. Out of these, the Merge sort works the best when sorting huge data sets and bubble sort works best for a small data set. [11] [12] [21]. Various effective algorithms are known which offer trade- offs in performance, simplicity, cost, memory use, resources used and other factors. But these algorithms do not take into account the features of parallelism on FPGA that significantly affect performance [24].

Reconfigurable gate arrays also referred to as field-programmable gate arrays (FPGA), are extensively utilized in the industry for implementing various digital circuits. FPGA is an integrated circuit that uses gate-level parallelism which multi-core GPPs cannot. It has a large memory that can be approached using a few numbers of pins [28]. Using FPGA has become beneficial to the real-time application [15].

To select among a large number of parallel sorting algorithms, it becomes difficult to select the best algorithm for a particular problem instance [6]. Since there is no identified theoretical model that can be implemented to accurately predict an algorithm's performance, it becomes difficult to make a choice. In the past few years, several implementation studies have been reported in the literature. However, more studies are

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needed before we can approach the point where a certain algorithm can be recommended for a particular application with any degree of confidence.

2. Algorithms

Sort Type Serial Bubble sort O(n2) Parallel Bubble sort O(n) Serial Merge sort O(n log n) Parallel Merge sort O(log n) Batcher’s bitonic merge sort O(log n)2 Batcher’s odd-even merge sort O(log n)2 Modified merge sort O(log n)2

Table 1. Table Label

2.1. Bubble sort algorithms [2]

To select among a large number of parallel sorting algorithms, it Bubble Sort is a simple algorithm that uses internal sorting to sort a given set of 'n' elements provided in the form of an array with 'n' number of elements. It is known as bubble sort, because the largest element with each complete iteration, bubbles up towards the last position or the highest index, similar to how water bubbles rise up to the water surface. Sorting takes place by hopping over all the elements one at a time and comparing it with the neighbouring element and interchanging them if required.

2.1.1 Serial Bubble sort

Bubble Sort is a basic sorting algorithm that performs the sorting operation by iteratively comparing the adjacent pair of the given data items and swaps the items if their order is reversed. There is a repetition of the passes through the list is sorted and no more swaps are needed. It is a simple algorithm, but it lacks in efficiency when the given input data set is large. The worst-case as well as the average-case complexity of Bubble Sort is О (n2 ). It is a simple and straightforward sorting algorithm used in computer science.

Consider the array with ‘n’ elements, we will start with the first two elements in the array. Since they are not in order, they are exchanged and move on comparing the second and third elements and then the rest of the elements. This completes pass1. Again, we start with the second element and perform the same operation for n-1 elements. If we have 100 elements then the total number of comparisons is 10000. So, in general, if we have total n elements, then we need to repeat this process for n-1 times.

Following are the steps involved in bubble sort (for sorting a given array in ascending order):

Starting with the first element (index = 0), compare the current element with the next element of the array.

1. If the current data element is greater than the next element of the array, swap them.

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2. If the data element is less compared to the next element, then move ahead with the next element and repeat Step 1

Figure 1. Serial Bubble sort

2.1.2 Odd-even transportation sort/ parallel bubble sort

Parallelization is a well-known solution to improve performance. Figure 2 shows a hardware design for parallel bubble sort, here comparison blocks in one column are executed in parallel. Odd-Even Transposition Sort is a form of parallel Bubble Sort algorithm. In this method, two adjacent data elements are compared and exchanged, if the first element is found to be greater than the second element. The opposite scenario applies when sorting in descending order. It compares two adjacent numbers and exchanges them, if the first number is greater than the second number to get an ascending order list.

Odd-Even transposition sort functions in two phases namely, odd phase and even phase. In both of these phases, adjacent elements are exchanged in the right.

Figure 2. Parallel Bubble sort

2.2. Merge sort algorithms [3]

When large amounts of data need to be sorted and cannot fit into the main memory of a computing device (usually RAM) it needs to reside within the slower memory which is external to the device (usually a hard drive), in such a situation external sorting is used. Thus, term external sorting is used for a class of sorting algorithms that can manage large amounts of data. It employs a hybrid sort-merge approach. Chunks of data that are small enough to fit in main memory are first read, then sorted, and lastly written out to a temporary file during the sorting phase. In the merge phase, the sorted sub-files are combined into an individual larger file. The merge sort algorithm is an excellent example

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of external sorting. We start by splitting the file into small pieces such that the size of each piece is small enough to fit into the main memory. Then each piece is sorted individually in the main memory employing a merge sort sorting algorithm. Lastly, the resulting pieces are merged together into larger pieces, until the file is completely sorted.

2.2.1. Serial merge

Merge sort sorting algorithm is a very prominent and efficient sorting algorithm. It is a stable sorting algorithm and is very efficient to handle big numbers. It is based on the following three steps:

1. Divide the given list or record into a number of sub lists in such a way that every list or sub list is half divided

2. Conquer the sub list by the recursion method

3. Combine the sorted sub list simply by merging

Figure 3. Serial Merge sort

2.2.2. Parallel merge

With FPGA problems can be solved in a parallel fashion. This sort is very similar to serial merge, only difference is that here all sub arrays are executed in parallel. The number of steps required for computation is much lesser than serial merge sort.

A parallel performs a merge operation on two sorted sequences of length. To produce a single sorted sequence of length equal to its input sequence. Each of the steps engages in n/2-1 divide and n/2 - 1 compare-exchange steps

2.2.3. Batcher’s Bitonic merge [17]

Batcher’s Bitonic sort is a parallel sorting algorithm where the main aim is to merge two bitonic sequences. A sequence is said to be bitonic when part of the sequence is monotonically increasing and part of it is decreasing. For example, 2,4,6,8,9,24,6,3,2,0 is a bitonic sequence. Batcher’s algorithm uses the following steps for sorting an input of ‘n’ numbers.

1. Convert the n numbers of a given sequence into a bitonic sequence with two subsequences having n numbers increasing and n numbers in a decreasing.

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2. After the bitonic sequence with n numbers is obtained, it is merged into an ordered sequence. Three operations are performed during merging operation which consists of log(n) stages. Batcher’s algorithm uses the following steps for sorting an input of ‘n’ numbers.

Figure 4. Bitonic merge sort

2.2.4. Odd-even merge sort [17]

Batcher proposed an odd-even merge sort algorithm. Even part consists of even numbers, and odd part consists of odd numbers. Both the parts are executed one by one, and at last, the combined result is obtained and the records are sorted. This step is iterated until a fully sorted sequence is obtained. It is known as an optimal sorting algorithm.

Figure 5. Odd-even merge sort

2.2.5. Modified merge sort [10]

A modified merge sorter is made up of a combination of odd-even merge sort and a bitonic merge sort. Its initial circuit consist of an odd-even merge circuit which produces a bitonic sequence and the later part consist of bitonic merge circuit. The time complexity of the modified merge sort is same as the odd-even merge sort.

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Figure 6. Modified merge sort

3. Modification of algorithm

3.1 Modification 1

There are many sorting algorithms. Few of which have been discussed in the previous chapter and depending on the environment they are used; they all have some advantages and disadvantages over the other.

In the field of sorting algorithms, there are algorithms, which are very simple, that do not require a lot of space in memory and for a small number of inputs they show faster results. Nevertheless, by increasing the number of inputs these algorithms start to become more complex and slower. On the other hand, there are sorting algorithms that reserve more space in memory, but these algorithms enable faster sorting which is a priority when we have a large number of inputs for sorting. There are a few algorithms that require the sorting speed to be faster while some require the cost to be lower. There are various algorithms that have a very fast speed but with that comes a higher cost.

The proposed modified sorting algorithm is one of the new approaches that it based on bubble sort and Batcher's odd-even merge sort algorithm. It uses a combination of both serial and parallel based sorting to reduce the cost and resource utilization.

3.2. Modification 2

The disadvantage of Modification 1 is that the number of cycles increases for a higher number of inputs. This will increase the timing. Thus, to overcome this problem, modification 2 has been made. The only difference with respect to modification 1 is that the serial bubble sort is replaced with O(1) Parallel Sorting. The O(1) algorithms is described below.

O (1) Parallel Sorting Algorithm. [9]

Every element compares its value to every other element in the array. If the value is equal to or less than it will store a zero, else it will store a 1. The values are then added which gives the relative position of that element.

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3.3 Flowchart of modification 1 and modification 2

Figure 7 explains the modification in the algorithm. The algorithm is divided into 2 parts. In this, we first divide the input sequence of 'n' numbers into four subsequence’s and perform the sequential bubble sort on each of the individual sub-sequences. We then have four sorted sub-sequences. The odd-even algorithm is used in modified form and instead of comparing the pair of neighbour elements (as in standard odd-even algorithm) we use it to compare the sub-sequences of successive elements. These are then merged using Batcher's odd even merge sort. The output is a sorted sequence of the input sequence.

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Figure 7. Flowchart of modification 1 and modification 2

Analysis

Consider the input sequence to be a0, a1, .... an-1. We start the sorting algorithm by dividing the sequence into 4 subsequences.

Thus, the number of elements in each subsequence is 'n/4 '.

In the first part of the sorting algorithm, we will be using serial bubble sort or O(1) which has the time complexity as given in equation Table 1.

For modification 1:

(1) For modification 2:

(2)

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Figure 8. Modification 2

Since the number of elements here are ' n/4'., substitute in equation (1) and (2) become

(3)

(4)

For comparing the 2 sub-sequences, the odd-even transportation sort is used which has the complexity as given in Table 1

(5)

Since here the number of sequences to be compared is 4. Equation 5 becomes

(6)

In order to sort and merge the 2 subsequences, we have used Batcher's odd-even merge sort, which has complexity as given in Table 1.

(7)

Sub n=n/4 in equation 7, and multiplying with equation 6

(8)

Now, combining equation (3) and (8) for modification 1, we get

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(9)

combining equation (4) and (8) for modification 2

(10)

Example

Figure 9. Modification 1 example

3.3. Modification 3

The number of cycles can be reduced even further by merging the O(1) algorithm and the Batcher's odd-even merge sort. This can be done by first splitting array into two subarrays. Then, sorting each induvial subarray using O(1) sorting algorithm and then merging these two sorted subarrays using odd-even merge sort algorithm.

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Figure 10. Modification 3 Analysis

Consider the input sequence to be a0, a1, .... an-1. We start the sorting algorithm by dividing the sequence into 2 subsequences.

Thus, the number of elements in each subsequence is 'n/2 '. We sort the 2 sub-sequences using O(1) sorting algorithm. Thus

(11)

These are then sorted using bitonic merge sort, which given us

(12)

Adding equation (11) and (12)

(13)

4. Hardware Architecture

4.1 System Flowchart

Figure 11. System flow chart of merge sorter

Figure 11 represents how each of the merge sort methology is implemented on the FPGA. When the sorter is triggered using the signal “in_en”, evaluated as high, instantly the serial-to-parallel converter (SPC), receives the data. It waits until a maximum of 16,32,64 bits of data is collected. The collected data is sent to the sorter only once the signal “in_ok” is forced high. After the data is sorted, if “sort_ok” is resolved as true, these incoming input data are forwarded to the parallel-to-serial converter (PSC). On completion of this step data which is sorted is immediately produced at the output. Finally, an “out_ok” signal is for the flow to the start and waits for a new set of inputs.

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4.2 Sorter Architecture

(a) (b) Figure 12 (a)Schematic symbol and (b)hardware schematic of comparator

Comparator's are used as building blocks in a sorter. A schematic of a simple comparator is shown in fig.12(a), while Fig. 12(b) shows its hardware schematics. A pipelined sorter is implemented in the design which makes use of buffers that stores data at each stage and enhances the speed.

5.Simulation results

5.1 Behavioral Simulation The proposed odd-even merge sorter is written in VHDL. The behavior simulation platform is Xilinx 14.7 and the FPGA used is Vertex-5.

Figure 13. Behavioral simulation of a modified merge sorter

5.2 Performance simulation

To evaluate the merge sort algorithms, resource utilization (number of slices, LUT'S comparators and area constraint ratio) parameters, delay and power are evaluated. The evaluations present the performance metrics based on the different merge algorithms and with varying numbers of input streams to merge.

5.2.1 Resource utilization

Table 2 shows the number of comparators used for various sort algorithms. The overhead on resource utilization of merging more streams increases because of the larger number of registers and comparators. As seen number of comparators used for serial merge and bubble sort is much less than parallel algorithms but the number decreases for the bitonic, odd-even and the modified merge sort.

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Table 2. Resource utilization of various sort algorithms 5.2.2 Power and area requirements

As seen in Table 3, the area constraint ratio is least for the serial bubble sort and modification 1 while is seen highest for serial, parallel merge and modification 2.

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Table 3. Power and area utilization of various sort algorithms

5.3 Number of clock cycles

Table 4 shows the number of clock cycles required for each sort. As depicted by the graph the serial merge uses the highest number of clock cycles. The clock cycles of transportation sort increase drastically with an increase in the number of inputs. While modification 3 uses the fewest number of clock cycles.

Table 4. Number of clock cycles required

6.Conclusion

Selecting the best sorting algorithm for a particular application is a very difficult task. This is based on the tradeoff between resource utilization, speed, area and power. It is observed that  The serial sort has the highest number of clock cycles but uses very few comparators compared to parallel sorting algorithms. This implies that Parallel sorts are faster but the cost for serial sorts will be more.  The power analysis does not have a significant difference with an increase in input bit size.  When a comparison between various merge sort algorithm is made odd-even merge has the least resource utilization, area constraint ratio and power. Hence These characteristics make it suitable for modification.  By comparing the different bubble sort algorithms, it is perceived that serial sort has a lesser number of comparators and power requirement while for smaller inputs the odd-even transportation sort shows amazing result’s in terms of comparators, resource utilization, number of clock cycles when the input size is small. However, as the number of inputs increases the results are not very promising.  After implementing modification 1 algorithm the resource utilization was seen to be decreased but it increased the number of clock cycles and the value of the area constraint ratio.  Modification 2 decreased the number of clock cycles but an increase is seen in all the other parameters.

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 Modification 2 decreased the number of clock cycles but an increase is seen in all the other parameters  Modification 3 decreased the number of clock cycles even future but on the other hand, the measure of resources used increased drastically.

All algorithms have their own advantages and disadvantages. The choice of selecting a particular algorithm is based on the requirement of the application. If one wants the clock cycles to be minimal with cost not being a factor than we go ahead using modification 3. If one is concerned with lower cost but the speed is not an issue, they can proceed using modification 1. 7.Future work

In future the algorithm can be modified to have lesser resource utilization along with fewer clock cycles. Also, other serial sort algorithms can be merged with the parallel sort algorithm to yield better results.

REFERENCES

11.1. Textbooks

[1] D.E Knuth. The Art of computer programming, Sorting and Searching volume II, Addison-Wesley, 2011

[2] Astrachan, O., 2003. Bubble sort: an archaeological algorithmic analysis. ACM Sigcse Bulletin, 35(1), pp.1-5

[3] Cormen, T.H., Leiserson, C.E., Rivest, R.L. and Stein, C., 2009. Introduction to algorithms. MIT press.

11.2. Journal Article

[4] Chen, C.P. and Zhang, C.Y., 2014. Data-intensive applications, challenges, techniques and technologies: A survey on Big Data. Information sciences, 275, pp.314-347

[5] George, E.D. and Farid, S.S., 2009. Combinatorial Optimisation Algorithms for Strategic Biopharmaceutical Portfolio & Capacity Management. In Computer Aided Chemical Engineering (Vol. 26, pp. 1063-1068). Elsevier

[6] Mishra, A.D. and Garg, D., 2008. Selection of best sorting algorithm. International Journal of intelligent information Processing, 2(2), pp.363-368.

[7] Inoue, U., Satoh, T., Hayami, H., Takeda, H., Nakamura, T., & Fukuoka, H. (1991). Rinda: a relational database processor with hardware specialized for searching and sorting. IEEE Micro, 11(6), 61-70.

[8] Jeong, S., Lee, Y. M., & Lee, S. (2017). Development of an automatic sorting system for fresh ginsengs by image processing techniques. Human-centric Computing and Information Sciences, 7(1), 41.

[9] Ajdari, J., Raufi, B., Zenuni, X. and Ismaili, F., 2015. A version of parallel odd-even sorting algorithm implemented in cuda paradigm. International Journal of Computer Science Issues (IJCSI), 12(3), p.68

[10] Chang, R. C. H., Wei, M. F., Chen, H. L., Lin, K. H., Chen, H. M., Gao, Y. Y., & Lin, S. C. (2014). Implementation of a high-throughput modified merge sort in MIMO detection systems. IEEE Transactions on Circuits and Systems I: Regular Papers, 61(9), 2730-2737.

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[11] Al-Kharabsheh, K.S., AlTurani, I.M., AlTurani, A.M.I. and Zanoon, N.I., 2013. Review on sorting algorithms a comparative study. International Journal of Computer Science and Security (IJCSS), 7(3), pp.120-126

[12] Mishra, A.D. and Garg, D., 2008. Selection of best sorting algorithm. International Journal of intelligent information Processing, 2(2), pp.363-368.

11.4. Conference Proceedings

[13] Lipu, A. R., Amin, R., Mondal, M. N. I.,& Al Mamun, M. (2016, December). Exploiting parallelism for faster implementation of Bubble sort algorithm using FPGA. In 2016 2nd International Conference on Electrical, Computer & Telecommunication Engineering (ICECTE) (pp. 1-4). IEEE.

[14] Ismail, K.A., Majid, M.A., Zain, J.M. and Bakar, N.A.A., 2016, October. Big data prediction framework for weather temperature based on MapReduce algorithm. In 2016 IEEE Conference on Open Systems (ICOS) (pp. 13-17). IEEE.

[15] Hongyan, C., Junwei, W.,& Xianli, L. (2017, March). Research and implementation of database high performance sorting algorithm with big data. In 2017 IEEE 2nd International Conference on Big Data Analysis (ICBDA)( (pp. 94-99). IEEE.

[16] Kumari, S., & Singh, D. P. (2014, August). A parallel selection sorting algorithm on GPUs using binary search. In 2014 International Conference on Advances in Engineering & Technology Research (ICAETR-2014) (pp. 1-6). IEEE.

[17] Rüb, C., 1998, February. On Batcher's merge sorts as parallel sorting algorithms. In Annual Symposium on Theoretical Aspects of Computer Science (pp. 410-420). Springer, Berlin, Heidelberg.

[18] Long, Z.,& Zhang, Z. (2017, October). FPGA-Based Collaborative Hardware Sorting Unit for Embedded Data Processing System. In 2017 10th International Conference on Intelligent Computation Technology and Automation (ICICTA)(pp. 260-264). IEEE.

[19] Chen, P., Gao, M., Huang, J., Yang, Y., & Zeng, Y. (2018, June). High-Speed Color Sorting Algorithm Based on FPGA Implementation. In 2018 IEEE 27th International Symposium on Industrial Electronics (ISIE) (pp. 235-239). IEEE.

[20] Nanjesh, B. R., Rajesh, T. H., T. Parallel merge sort based performance evaluation and comparison of MPI and PVM. In 2013 IEEE Conference on Information & Communication Technologies(pp. 530-534). Iejonidhi, M. R., & Kumar, H. A. (2013, April). IEEE.

[21] Yang, Y., Yu, P., & Gan, Y. (2011, July). Experimental study on the five sort algorithms. In 2011 Second International Conference on Mechanic Automation and Control Engineering(pp. 1314-1317). IEEE

[22] Durad, M. H., & Akhtar, M. N. (2014, December). Performance analysis of parallel sorting algorithms using MPI. In 2014 12th International Conference on Frontiers of Information Technology (pp. 202-207). IEEE.

[23] Harkins, J., El-Ghazawi, T., El-Araby, E., & Huang, M. (2005, December). Performance of sorting algorithms on the SRC 6 reconfigurable computer. In Proceedings. 2005 IEEE International Conference on Field-Programmable Technology, 2005. (pp. 295-296). IEEE.

[24] Korakoppa, V. P., & Aradhya, H. R. (2017, February). Implementation of highly efficient sorting algorithm for median filtering using FPGA Spartan 6. In 2017 International Conference on Innovative Mechanisms for Industry Applications (ICIMIA) (pp. 253-257). IEEE.

[25] Tariq, A.S., Amin, R., Mondal, M.N., & Hossain, M.A. (2016). Faster implementation of Booth's algorithm using FPGA. 2016 2nd International Conference on Electrical, Computer & Telecommunication Engineering (ICECTE), 1-4.

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[26] Patel, Y. S., Singh, N. K., & Vashishtha, L. K. (2014, September). Fuse sort algorithm a proposal of divide & conquer based sorting approach with O (nloglogn) time and linear space complexity. In 2014 International Conference on Data Mining and Intelligent Computing (ICDMIC) (pp. 1-6). IEEE.

[27] Alquaied, F. A., Almudaifer, A. I., & AlShaya, M. A. (2011, April). A novel high-speed parallel sorting algorithm based on fpga. In 2011 Saudi International Electronics, Communications

11.4. Patents

[28] Chatter, Mukesh. "High performance self modifying on-the-fly alterable logic FPGA, architecture and method." U.S. Patent 5,838,165, issued November 17, 1998.

[29] Dickens, B., McDonnell Douglas Corp, 1998. Date formatting and sorting for dates spanning the turn of the century. U.S. Patent 5,806,063.

[30] De Ley, L., Jenkins, W., Mann,V. and Miller, S., Scientific Learning Corp, 2006. Method for improving vocabulary, concept knowledge, and decoding skills using semantic and linguistic sorting on a computing device. U.S. Patent Application 11/349,700.

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