Digital Logic for Computers

ACOE161: / Digital Logic for Computers / Experiment # 2

Digital Logic for Computers

(ACOE161)

Experiment #2

Logic Gate Input Expansion

Student’s Name:
Semester: / Date:

Assessment:

Assessment Point / Weight / Grade
Methodology and correctness of results
Discussion of results
Participation

Assessment Points’ Grade:

Comments:

Experiment #2:

Logic Gate Input Expansion

Objectives:

The objectives of this experiment are to:

investigate how a logic gate with many inputs can be implemented using gates with less inputs,
examine how to handle unused inputs of logic gates.

Discussion:

The basic logic gates found in integrated circuits have a limited small number of inputs, usually two, three or four. In many applications there is a need for logic gates with more inputs. A number of logic gates can be combined to form a logic gate with more inputs. Figure 1b shows how a 3-input AND gate can be implemented using two 2-input AND gates. Figure 1c and 1d show how a 4-input AND gate can be implemented using three 2-input AND gates. Figure 1f shows how a 3-input OR gate can be implemented using two 2-input OR gates. Figure 1g and 1h show how a 4-input OR gate can be implemented using three 2-input OR gates.

Figure 1: Logic Gate Input Expansion

In many applications there are gates available with more inputs that the required ones. The extra inputs must be connected in such a way not to change the function of the logic gate. The unused inputs are usually connected directly to logic 1, a logic 0, or to another input of the same gate. Figure 2 shows how the unused inputs of logic gates can be connected.

Figure 2: Unused inputs of logic gates

Procedure:

Exercise 1:

(a)
Place the 7408 and the 7432 ICs on the breadboard and make the connections shown in figure 3. Turn on the Digital Lab Trainer power.

Figure 2.

(b)Go through all possible states of the switches S7, S6, S5, S4, S3 and S2 and fill up table 1. Use number 1 to represent the ON state of the LEDs and number 0 to represent the OFF state.

S7 / S6 / S5 / L7 / S4 / S3 / S2 / L3
0 / 0 / 0 / 0 / 0 / 0
0 / 0 / 1 / 0 / 0 / 1
0 / 1 / 0 / 0 / 1 / 0
0 / 1 / 1 / 0 / 1 / 1
1 / 0 / 0 / 1 / 0 / 0
1 / 0 / 1 / 1 / 0 / 1
1 / 1 / 0 / 1 / 1 / 0
1 / 1 / 1 / 1 / 1 / 1
(a) / (b)

Table 1.

Exercise 2:

(a)Turn off the Digital Lab Trainer power. Place the 7400 and the 7486 ICs on the breadboard and make the connections shown in Figure 4. Turn on the Digital Lab Trainer power.

(b)Go through all possible states of the switches S7, S6, S5, S4, S3 and S2 and fill up table 2. Use number 1 to represent the ON state of the LEDs and number 0 to represent the OFF state.

Table 2.

Figure 3.

Exercise 3:

(a)Turn off the Digital Lab Trainer power. Place the 7411 and the 7427 ICs on the breadboard and make the connections shown in Figure 4. Turn on the Digital Lab Trainer power.

(b)Go through all possible states of the switches S7, S6, S5 and S4 and fill up table 4. Use number 1 to represent the ON state of the LEDs and number 0 to represent the OFF state.

S7 / S6 / L7 / S5 / S4 / L6 / S3 / S2 / L4 / S1 / S0 / L3
0 / 0 / 0 / 0 / 0 / 0 / 0 / 0
0 / 1 / 0 / 1 / 0 / 1 / 0 / 1
1 / 0 / 1 / 0 / 1 / 0 / 1 / 0
1 / 1 / 1 / 1 / 1 / 1 / 1 / 1
(a) / (b) / (c) / (b)

Table 4.

Figure 4.

Questions

Discuss the results of exercise 1 (Table 1)

Discuss the results of exercise 2 (Table 2)

Discuss the results of exercise 3 (Table 3)